JP2920947B2 - Method for manufacturing thin film transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) having a channel portion of silicon and a method of manufacturing the same, and particularly to a thin film transistor structure capable of using an inexpensive glass substrate and a low temperature process thereof. The present invention relates to a technique for solid-phase growth of a channel portion useful for adoption.

[Conventional technology]

Conventionally, for example, the structure of a polycrystalline silicon thin film transistor having a staggered structure applied to a low-temperature process or the like,
As shown in FIG. 5, an inexpensive hard glass substrate 1 is used, and a phosphorus-doped source film 3 and a drain film 4 are formed on a passivation film 2 covering the entire surface and are spaced apart from each other. A channel film 5 which is an undoped polycrystalline silicon film having an overlap margin between the film 3 and the drain film 4 and a thin silicon oxide film 6 which is a gate insulating film on which an MOS (MIS) portion is to be formed on the channel film 5. And N-type high concentration polycrystalline silicon gate electrode 7 and gate electrode 7
A silicon oxide film 8 as an interlayer insulating film for covering the source film 3, a source electrode 9 made of aluminum and a pixel electrode (drain electrode) 10 as a transparent electrode (ITO), which are in conductive contact with the source film 3 and the drain film 4 through contact holes. And

In the process up to obtaining the channel film 5 in the thin film transistor (TFT) having such a structure, first, as shown in FIG. 6A, a passivation film 2 of a silicon oxide film is entirely covered on a hard glass substrate 1, and After covering the phosphorus-doped polycrystalline silicon film by a low-pressure CVD method or an ion implantation method, the source film 3 and the drain film 4 are formed by patterning. Next, as shown in FIG. 6 (B), a polycrystalline silicon film is entirely coated on the source film 3 and the drain film 4 and is patterned to form an undoped channel film 5. In order to increase the current capacity, the entire substrate is heated in a heating furnace, and the polycrystalline silicon of the channel film 5 is recrystallized (solid phase growth) to form polycrystalline silicon having a large grain size.

[Problems to be solved by the invention]

However, the solid phase growth process has the following problems.

The solid phase growth step involves heating the entire substrate at a high temperature of about 600 ° C. for several tens of hours in order to obtain an appropriate particle size.
Inexpensive hard glass substrate 1 with low dislocation temperature as substrate material
Since the substrate 1 is used, the substrate 1 itself is easily softened, and the substrate after being heated is deformed such as distortion and expansion and contraction. For this reason, microfabrication after the solid phase growth step is extremely difficult, and cannot be practically used at all. In other words, when an inexpensive hard glass substrate 1 is used in a low-temperature process, the grain size of polycrystalline silicon can be increased by solid-phase growth of the channel film 5 and the hard glass substrate 1 is deformed. Always accompany.

In addition to the difficulty of fine processing due to shape deformation, the soft glass substrate 1 is softened during solid-phase growth, and impurities penetrate into the channel film 5 from the hard glass substrate 1 via the passivation film 2. Although the particle size becomes larger due to this, the intrusion of the impurities rather causes the deterioration of the transistor characteristics.

Therefore, an object of the present invention is to maintain the substrate at a low temperature to the extent that it does not soften, and to heat the channel film so that the polycrystalline silicon is optimally solid-phase grown. An object of the present invention is to provide a thin film transistor in which an inexpensive substrate can be used, a channel film has a large grain size, and transistor characteristics are improved by adopting the improvement of the above and the short-time indirect local heating method.

[Means for solving the problem]

In order to solve the above problems, a method for manufacturing a thin film transistor according to the present invention includes forming a light absorbing film having conductivity and a high melting point on a transparent substrate, and forming a passivation film on the light absorbing film. Forming polycrystalline silicon to be the source / drain and channel of the thin film transistor on the passivation film, performing a lamp annealing process on the polycrystalline silicon, and forming a gate electrode on the polycrystalline silicon via a gate insulating film. And forming the light absorbing film so as to cover the source / drain and the channel in plan view.

[Action]

As described above, by adopting a structure in which the light absorbing film sandwiched between the upper and lower passivation films is interposed between the transparent substrate and the channel portion, when the entire substrate is irradiated with light by a halogen lamp or the like, the irradiation light is increased. Transmits through the transparent substrate itself,
Since the light absorbing film efficiently absorbs the light, the temperature of the light absorbing film rises, and the temperature of the light absorbing film rises, and the light absorbing film itself becomes a local heat source in the vicinity thereof, and heat transmission or heat radiation occurs. Heats the channel. For this reason,
Solid phase growth of the polycrystalline silicon in the channel portion is promoted, and polycrystalline silicon having a large grain size is formed. Therefore, the ON current capacity is increased due to the characteristics of the transistor. In this lamp annealing step, the transparent substrate itself mainly receives conduction heat from the light absorbing film which is a local heat source, but the transparent substrate has a considerably larger heat capacity than the light absorbing film, and the light absorbing film is transparent. Since the transparent substrate is formed in a small size on one side of the substrate, the transparent substrate functions as a heat sink and does not reach a high temperature. Therefore, even if an inexpensive hard glass substrate is used, no substrate deformation occurs, and the obstacle to fine processing of the upper layer is eliminated. It should be noted here that the temperature of the light absorbing film is higher than the dislocation point of the transparent substrate (for example, 700 to 800 ° C).
It can be set to. This benefit contributes to optimization of the solid phase growth temperature without deformation of the transparent substrate, and a transistor having an increased on-current capacity is realized. Further, the lamp annealing time can be shortened (for example, 1 to 2 hours) as compared with the case of the conventional thermal annealing using a heating furnace, and the throughput can be increased.

The light absorbing film and the upper and lower passivation films prevent impurities generated from the transparent substrate immediately below the light absorbing film from entering the channel portion during lamp annealing. Of course, it is desirable that the thickness of the lower passivation film is sufficiently large. However, since only the portion immediately below the light absorbing film is heated by heat conduction, even if the lower passivation film is thin, the light absorbing film itself does not penetrate impurities. Function as a barrier for On the other hand, the upper passivation film prevents impurities from the light-absorbing film from entering the channel portion, but since the material of the light-absorbing film is a high-melting-point material, the amount of evaporated impurities is small.
The upper passivation film thickness may be relatively thin.

The light absorbing film is not only meaningful in the above manufacturing process, but can also be used as a pack gate electrode,
In this case, the number of steps can be reduced. In addition, in the step of forming the light absorbing film, a source wiring or a drain wiring can be simultaneously formed separately, which also leads to a reduction in the number of steps.

〔Example〕

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1A is a longitudinal sectional view showing a structure of a thin film transistor according to an embodiment applied to a low-temperature process of the present invention.
FIG. 1B is a plan view of the same structure.

The structure of this polycrystalline silicon thin film transistor uses an inexpensive hard glass substrate 1 and is formed on a silicon oxide film or a silicon nitride film, a lower passivation film 12 covering the entire surface thereof, and a small size region on the film 12. Light absorption film of high melting point material such as tungsten, molybdenum, titanium, silicide, silicon etc.
13, and an upper passivation film 14 covering this film 13,
An undoped phosphorous-doped source film 15 and a drain film 16 formed on the passivation film 14 immediately above the light absorbing film 13 with a space between the source film 15 and the drain film 16; Channel film as polycrystalline silicon film
17, a thin silicon oxide film 18 as a gate insulating film to form a MOS portion on the channel film 17 and a gate electrode 19 of N-type high-concentration polycrystalline silicon, and a thick as an interlayer insulating film covering the gate electrode 19 and the like. The semiconductor device includes a silicon oxide film 20, an aluminum source electrode 21 which is in conductive contact with the source film 15 and the drain film 16 through a contact hole, and a pixel electrode (drain electrode) 22 as a transparent electrode (ITO).

As shown in FIG. 1 (B), the light absorbing film 13 is patterned so as to include the source film 15 and the drain film 16 and the channel film 17 within its plane occupied area. The width is the source film 15 and the drain film
It is narrower than that of 16.

In the process of obtaining a channel film 17 in this thin film transistor, first, as shown in FIG. 2A, a hard glass substrate 1 is prepared, and a lower passivation film 12 such as a silicon oxide film or a silicon nitride film is formed thereon by CVD. To the entire surface, and on top of it a thickness of 20 by sputtering etc.
After forming a high melting point material film (for example, tungsten, molybdenum, titanium, silicide, silicon) of about 00 to 3000 °, the light absorbing film 13 is obtained by patterning this film. Next, as shown in FIG. 2 (B), an upper passivation film 14 having a thickness of about 500 to 1000 ° is coated on the light absorbing film 14 by CVD. Next, as shown in FIG.
A phosphorus-doped polycrystalline silicon film is coated on the passivation film 14 directly above the low-pressure CVD or ion implantation method, and then a source film 15 and a drain film 16 are formed by patterning. Next, as shown in FIG. 2 (D), a polycrystalline silicon film is entirely coated on the source film 15 and the drain film 16 and is patterned to form an undoped channel film 5.

At this point, the grain size of the polycrystalline silicon of the channel film 5 is relatively small. Here, the entire substrate is subjected to lamp annealing (center wavelength 1.1 μm) by light irradiation using a halogen lamp as a light source.
m) is performed. The irradiation light passes through the transparent hard glass substrate 1, but the irradiation light hitting the area of the light absorbing film 13 is efficiently absorbed by the light. As a result, the temperature of the light absorbing film 13 rises and becomes high, so that the light absorbing film 13 itself serves as a local heat source for its surroundings, and heats the channel film 17 by heat conduction or heat radiation. When the channel film 17 is heated, the polycrystalline silicon grows in a solid phase. Although the temperature of this solid phase growth depends on the temperature, heat capacity, etc. of the channel film 17,
The temperature of the channel film 17 also depends on the illuminance and time of light irradiation. In the present embodiment, light irradiation is performed intermittently in order to keep the light absorbing film 13 at an extremely high temperature and to maintain a certain steady temperature. Also, the temperature of the channel film 17 during the solid phase growth could be maintained at 700 to 800 ° C. This temperature exceeds the dislocation point of the hard glass substrate 1. Moreover, the annealing time could be reduced to 1-2 hours. By this lamp annealing step, polycrystalline silicon having a large grain size can be obtained, the on-current capacity can be increased, and the throughput can be increased by shortening the solid-phase growth treatment. No deformation occurs, and fine workability and flatness of the TFT are not impaired. Since the light absorption film 13 is heated as a local heat source by light irradiation and indirectly heats its surroundings, the hard glass substrate 1 itself is not directly heated, but rather functions as a heat sink. This is because the temperature can be suppressed and maintained at a temperature lower than the glass transition point.

This light absorbing film 13 also functions as an impurity barrier film in the annealing step. In the annealing step, the hard glass substrate 1 under the light absorbing film 13 is heated, and the channel film 17 may be contaminated by the back diffusion of the impurity. However, the light absorbing film 13 prevents the intrusion of the impurity due to the back diffusion. Although the diffusion of impurities from the light absorbing film 13 itself is also conceivable, the problem is not so large because the amount of evaporated impurities itself is very small because of the high melting point material and the diffusion is prevented by the upper passivation film 14.

After this lamp annealing step, an upper thin film is formed by a normal process to obtain a thin film structure as shown in FIG. 1 (A). At the same time as the lamp annealing step, a gate oxide film as a thermal oxide film is formed. Can also be formed.

FIG. 3 is a longitudinal sectional view showing a structure of a thin film transistor according to a second embodiment of the present invention. In FIG. 3, the same portions as those shown in FIG. 1 (A) are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, the light absorbing film 13 on the lower passivation film 12 is used.
A source wiring 13b and a drain wiring 13c are provided on both sides of a and are separated from the source wiring 13b.
In addition, the drain wirings 13c are in conductive contact with the upper drain film 16, respectively. The source wiring 13b and the drain wiring 13c
Are formed simultaneously in the step of forming the light absorbing film 13a.
Therefore, the source wiring 13b and the drain wiring 13c are made of the same material as the light absorbing film 13a, but the material is a conductive material. According to this embodiment, although the material of the light absorbing film 13a has conductivity and the degree of freedom in selecting the film material is slightly reduced, there is an advantage that the number of steps is reduced as compared with the first embodiment. Of course, in the lamp annealing step of the channel film 17, the source wiring 13b and the drain wiring 13c also effectively function as local heat sources like the absorbing film 13a.

FIG. 4 is a longitudinal sectional view showing the structure of a thin film transistor according to a third embodiment of the present invention. In FIG. 4, the same portions as those shown in FIG. 1 (A) are denoted by the same reference numerals, and description thereof will be omitted.

The structure of this embodiment is almost the same as that of the first embodiment, but the light absorbing film 23 is used as a back gate electrode. Therefore, the upper passivation film 14 immediately below the channel film 17 functions as a gate insulating film. According to such a structure, doubling of the on-electrode capacitance is realized.

Although each of the above embodiments shows a thin film transistor structure suitable for a low temperature process, it is suitable for a high temperature process in which a part of a polycrystalline silicon film is used as an undoped channel portion and both sides are a source portion and a drain portion. Also in the thin film transistor structure described above, a light absorbing film may be provided.

〔The invention's effect〕

As described above, the present invention has the following effects.

(A) In the lamp annealing step, the irradiation light is absorbed by the light absorbing film, so that the light absorbing film can promote the solid phase growth of polycrystalline silicon as a heat conductor.

(B) Since the light absorbing film is formed so as to cover the source and the drain in addition to the channel, the crystallinity of the polycrystalline silicon of the source / drain and the channel is improved by annealing the polycrystalline silicon. Accordingly, a thin film transistor with an increased on-state current can be provided.

(C) Impurities generated from within the substrate can be prevented from entering the channel by the light absorbing film during solid phase growth, and deterioration of transistor characteristics can be prevented.

[Brief description of the drawings]

Fig. 1A is a longitudinal sectional view showing the structure of a thin film transistor according to an embodiment applied to the low-temperature process of the present invention, and Fig. 1B is a plan view of the same structure. 3) to 3 (D) are longitudinal sectional views for explaining main processes in the embodiment, respectively, and FIG.3 is a longitudinal sectional view showing a structure of a thin film transistor according to a second embodiment of the present invention. Fig. 4 is a longitudinal sectional view showing a structure of a thin film transistor according to a third embodiment of the present invention, and Fig. 5 is a longitudinal sectional view showing a structure of a thin film transistor applied to a conventional low-temperature process. 7A and 7B are longitudinal cross-sectional views for explaining a process until a channel film is obtained in the conventional structure [Description of Main Symbols] 1 ... Hard glass substrate, 12 ... Lower passivation film 13, 13a, 23 …… Light absorbing film 14 …… Passivation on top Film 15 source film 16 drain film 17 channel film 18 silicon oxide film 19 gate electrode 20 silicon oxide film as interlayer insulating film 21 source electrode 22 pixel electrode ( Drain electrode) 13b: Source wiring 13c: Drain wiring.

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/786 H01L 21/336

Claims (1)

(57) [Claims] 1. A light absorbing film having conductivity and made of a high melting point material is formed on a transparent substrate, a passivation film is formed on the light absorbing film, and a source / drain of a thin film transistor and a thin film transistor are formed on the passivation film. Forming a polycrystalline silicon serving as a channel, lamp annealing the polycrystalline silicon, and forming a gate electrode on the polycrystalline silicon via a gate insulating film; A method of manufacturing a thin film transistor, wherein the film is formed so as to cover the source / drain and the channel in plan view.