JP2862504B2 - Microcomputer security system for gaming machine control - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a security system for a microcomputer for controlling a gaming machine represented by a pachinko gaming machine, an arrangement type pachinko gaming machine, a slot machine or the like.

[0002]

2. Description of the Related Art Conventionally, a microcomputer program for controlling a game machine is developed and developed by a development and manufacturing company and stored in a read only memory (ROM) of the microcomputer. Take a third-party test to determine if you pass. Only a microcomputer having a read-only memory in which a passing program that has passed the examination of a third-party organization is stored in the gaming machine and loaded into the game arcade, where a sound game that passes a certain standard is passed. Only the gaming machines that can perform the game will be installed.

[0003]

However, even if the only gaming machines that are shipped to the amusement arcade are those that can play sound games that pass a certain standard, the present invention relates to a gaming machine carried into the amusement arcade. In some cases, an unauthorized program other than a passing program was created, and the central processing unit could be operated by the unauthorized program.If such unauthorized modification was performed, a third-party organization performed a test. However, there is a disadvantage in that a gaming machine that operates in a manner that does not conform to a certain standard is available in an actual game arcade.

[0004] In view of the above circumstances, it is an object of the present invention to minimize the control of a gaming machine by an illegally modified program other than a pass program.

[0005]

A security system for a microcomputer for controlling a gaming machine according to the present invention develops a program for a central processing unit of the microcomputer for controlling the gaming machine and stores the program in a read-only memory. A step of testing whether or not the developed program passes a predetermined standard, and installing a gaming machine equipped with a microcomputer having a read-only memory in which the program that has passed the test is stored. A system comprising a step of using in a game arcade, a step of giving predetermined security information to the program only when the result of the test step passes a certain standard; Writing information to a read-only memory; Making the mounted microcomputer determine whether or not the program stored in the mounted read-only memory has passed the test based on the security information as a clue. The gaming machine is configured to operate only when it is determined to be appropriate.

[0006]

According to the present invention, a development program for controlling a gaming machine developed by a development and manufacturing company is stored in a read-only memory of a microcomputer. Then, a test is performed by a testing organization to determine whether or not the development program stored in the read-only memory passes a certain standard. Then, predetermined security information is given to a passing program that has passed the test of the third party organization, and the security information is written in the read-only memory. On the other hand, the microcomputer incorporates a program for judging whether or not the program stored in the read-only memory is an appropriate program that has passed the test, based on the security information. As a result, when a game machine equipped with a microcomputer having a read-only memory in which the control program is stored is carried into a game arcade, when the game machine is operated, the appropriateness determination means included in the microcomputer is included. By the operation, it is determined whether or not the program stored in the read-only memory mounted on the microcomputer is an appropriate one that has passed the test by the third party. As a result, the game machine is configured to operate only when the microcomputer determines that the program is appropriate, so that the game machine incorporating the unauthorized program cannot operate.

[0007]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an overall system block diagram showing a security system for a gaming machine control microcomputer according to the present invention.

A microcomputer chip used in the present invention is manufactured by a semiconductor chip maker 1. The semiconductor chip maker 1 manufactures a semiconductor chip in which an MPU, a RAM, and an input / output port (I / O port) in a microcomputer are integrated into one chip. The chips manufactured by the semiconductor chip maker 1 include a mass-production chip 23a and a development chip 23b, which will be described later in detail. The mass production chip 23a is the mass production chip 23.
The program has a determination function of determining whether or not the program stored in the ROM connected to a is appropriate and has passed the test by the third-party testing institution 11 described later. The development chip 23b is a chip that does not have the above-described determination function, and is the same as the mass-production chip 23a except that it does not have the determination function.

[0010] Of the chips received from the semiconductor chip maker 1 to the chip distribution company 2, the mass production chips 23 a are distributed by the mass production chip distribution division 28 and carried into the chip distribution management organization 3. On the other hand, the development chip 23 b is distributed by the development chip distribution section 29 of the chip distribution company 2 and is carried into the chip distribution management organization 3. Note that the chip distribution company 2 may be a completely private company, or may be a public company formed by the government. The chip distribution management institution 3 is an organization for managing whether or not chips are properly distributed and mediating distribution of chips to a predetermined game machine maker or the like. The chip distribution management organization 3 may be omitted and chips may be directly carried in from the chip distribution company 2 to the game machine maker.

The mass production chip 23a and the development chip 23b carried into the chip distribution management organization 3 are carried into the mass production section 6 and the development section 5 of the gaming machine maker 4, respectively.
The development section 5 of the gaming machine maker 4 develops a program using the development chip 23b carried in as shown in FIG. A game machine for application is created by mounting the application master ROM 10a storing the developed program, and a document for application is created, and a game machine for application and creation document 9 on which the application master ROM 10a is mounted. To the third-party testing institution 11.

The third-party testing institution 11 is composed of, for example, a commissioned agency of a public supervisory institution such as the police. The third-party testing institution 11 includes a test service section 12 and an appraisal service section 13. The test submission 8 is carried into the test service section 12, and the test application is accepted as shown in FIG. The test service section 12 tests the received test submission 8 as shown in FIG. 15 and determines whether or not the test result is acceptable as shown in FIG. If it is determined that the application is unsuccessful, the application submitter 8 is returned to the gaming machine maker as shown in FIG. On the other hand, the competent supervising organization 25 composed of the police and the like in each prefecture also conducts tests on the application gaming machines,
If the third party testing organization 11 determines that the test is passed and the competent supervising organization 25 determines that the test is appropriate, a security code is issued and stored in the mass production master ROM 10b as shown in FIG. The third-party testing institution 11 and the jurisdiction supervisory institution 25 constitute a third-party institution that tests whether the development program stored in the read-only memory (ROM) passes a certain standard. ing. The security code is
In order to determine whether the program stored in the ROM mounted on the game machine that has been released to the market after being judged by the third party has passed the examination of the third party is appropriate. Security information used for

As the security code, for example, a method in which program data of a passed program is converted according to a predetermined conversion format to be a security code can be considered. In this case, all of the program data may be used as a reference for creating a security code, or a particularly important portion of the program data (for example, a data portion such as a jackpot probability or an opening time of a variable winning ball device) may be used as a reference for creating a security code. It may be. This security code may be issued when the third-party testing organization determines that the test has passed without waiting for the result of the certification from the competent supervisory agency 25.

The mass production master ROM 10b to which the security code has been added by an organization such as the test service department 12 of the third party testing organization 11 is used for the mass production department 6 of the gaming machine maker 4.
And the storage information stored in the mass production master ROM 10b is copied as shown in FIG.
Then, the ROM in which the copied storage information of the mass production master ROM 10 b is stored is mounted on the board 22. Further, the chips for mass production carried in from the chip distribution management organization 3 are mounted on the substrate 22 as shown in FIG. The mounting chip 23 mounted on the substrate 22 and the mounting ROM 10
A microcomputer for controlling the gaming machine is constituted by c. Chip 23 and ROM 10 on substrate 22
c, and after the power is turned on, the mounting RO
The security code included in the storage information of M10c is stored in the mounting chip 23 as described later. As described above, the mounting chip 23 composed of the mass-production chip 23a has a function of storing only the security code stored in the ROM 10c attached to the substrate 22 and connected first. Based on the stored security code, it is determined whether or not the program stored in the mounting ROM 10c is an appropriate program that has passed the test of the third party.
In the case where the program stored in the ROM is falsified after the ROM is mounted, or the mounted ROM 10c is replaced with a ROM storing the illegally created program, the security code stored in the mounted chip 23 is And the security code stored in the ROM are different from each other and lose consistency, thereby making it possible to determine that the program has been tampered with. Instead of having the gaming machine maker 4 copy the program and security code to the ROM and mount it on the board,
The master ROM 10b for mass production is carried into the chip distribution company 2, and the chip distribution company 2 performs ROM copying and mounting work of the ROM on the board.
You may make it carry in. The gaming machine maker 4 constitutes a development / manufacturing company which develops a program for operating a central processing unit of a microcomputer for controlling the gaming machine and stores the development program in a read-only memory of the microcomputer. ing. In addition, this development and manufacturing company is not limited to game machine manufacturers,
It may be constituted by a program development / manufacturing company which is a subcontractor of the gaming machine maker.

As described above, if the program stored in the ROM connected to the mass-production chip 23a is different from the first program by remodeling or the like, the fact that the program has been tampered with is modified. The microcomputer 23a has a function of making the microcomputer not operate in a normal state by determining
In the case where the development is performed by the development section 5 described above, the program stored in the ROM is debugged or the like, and each time the program is changed, it is determined that the program is inappropriate and the microcomputer is The inconvenience of malfunctioning occurs. However, as described above, since the development chip 23b does not have the security check function, the microcomputer operates in a normal state even if the debugging or the like is performed, and has an advantage that it is convenient for program development. The package for the mass production chip 23a is made of, for example, plastic and the package for the development chip 23b is made of, for example, ceramic so that the mass production chip 23a and the development chip 23b can be distinguished from the appearance of the chip. I have.

A game machine 21 on which a board on which a chip and a ROM are mounted is assembled is carried into a game hall 24. In the amusement arcade 24, a plurality of carried-in gaming machines 21 are installed so that a player can play a game.

The jurisdiction supervising organization 25 performs a random inspection of the gaming machine 21 installed in the amusement arcade 24, and performs a process of collating the ROM of the gaming machine which seems to be malfunctioning as shown in FIG. Third-party testing institutes 1 whose ROMs have been verified but whose suitability is difficult to determine
A request for appraisal is made to the appraisal business unit 13 of the first section. For example,
If both the mounting chip 23 and the mounting ROM 10c are replaced with other illegally manufactured ones, the gaming machine will operate according to the remodeling program without performing the security check described above. In such a case, an appraisal request is made to the appraisal business unit 13.

In the appraisal business unit 13, the board 2 on which the mounting chip 23 and the mounting ROM 10c requested for the appraisal are mounted is mounted.
Inspection and verification of the game machine are performed as shown in FIG. This gaming machine verification / collation 33 removes the ROM 10c mounted on the board 22 and mounts the mass production master ROM 10b storing an appropriate program in place of the ROM 10c to determine whether the mounting chip 23 operates normally. Verification and collation of As a result, as shown in FIG. 28, an appraisal work / document is prepared, and the appraisal result is reported to the competent supervisory authority 25. The above-mentioned application master ROM 10a, mass production master ROM 10b, and mounting ROM 10c are configured by, for example, an EPROM.

FIG. 2 is a block diagram showing a mounting chip in which a mass-production chip is mounted on a substrate and various devices and circuits connected to the mounting chip.

The mounting chip 23 has a central processing unit (CP) capable of executing a control operation in a predetermined procedure.
A U40, a RAM 41 capable of writing and calling required data, and an I / O port 44 for receiving input signals and providing input data to the CPU 40 and receiving output data from the CPU 40 and outputting the data to the outside are integrated into one chip. It is configured. A crystal oscillation signal from an externally provided crystal oscillator 45 is input to a clock generation circuit 46 provided on the mounting chip 23. The crystal oscillation signal from the crystal oscillator 45 has a frequency twice as high as the operation clock. Note that a vibration signal from a ceramic oscillator using ceramic as an oscillator instead of the crystal oscillator 45 may be input to the clock generation circuit 46. The programmable clock dividing circuit 47, to which the clock signal from the clock generating circuit 46 is inputted, divides the inputted clock signal and converts a predetermined clock signal into the sound generator 4
8 or the variable display device display drive IC 49. The sound generator 48 outputs a control signal for generating sound to a speaker provided in the gaming machine.

The programmable interrupt request timer 0 (5
Reference numerals 0) and 1 (51) each comprise a 16-bit programmable counter timer, and include a free running counter and a compare register (two sets).
The programmable interrupt request timers 0 (50) and 1 (5
1) The main functions are interval timer function,
Event count function, one-shot output function, PW
Not only has an M (pulse width modulation) output function, but also a pulse width measurement function and a time difference measurement function. The pulse width measurement function is a function for measuring the waveform length of a detection signal of a start winning switch or a 10-count detection switch provided in, for example, a gaming machine. This function measures the time from the detection signal to the next detection signal. The pulse width measurement function and the time difference measurement function can be achieved when the clock source of the counters of the programmable interrupt request timers 0 (50) and 1 (51) is selected as an external input. As a clock source of the counter, a clock can be selected and used as a refresh counter, and an output from the other programmable interrupt request timer can be selected as a clock source and used as a 32-bit count. . As a method of selecting these clock sources, a method of selecting them inside a program is adopted. In other words, there is a register at a certain address, a predetermined number is written in this register, and a clock source is selected according to the type of the written number.

This programmable interrupt request timer 0 (5
For 0) and 1 (51), an interrupt can be set by a counter output and a compare output, and the interrupt can be set to be routed to any one of exception processing of a user reset, a maskable interrupt, and a non-maskable interrupt. Further, by the function of the prescaler, the clock unit time of the timer can be arbitrarily set, and the values of the compare registers (two sets) can be arbitrarily set. Output signals from the programmable interrupt request timers 0 (50) and 1 (51) are input to the reset / interrupt controller 52.

This reset / interrupt controller 52
Has a system reset function and a user reset function. The system reset refers to initializing the entire mounting chip 23 including the I / O port 44 and restarting from the power-on state. On the other hand, the user reset is to perform a warm restart of the mounted chip 23 by resetting only the CPU 40. This user reset is performed, for example, once every 2 msec to enable interrupt processing. The reset / interrupt controller 52 receives a system reset signal, a user reset signal for performing a warm restart, a non-maskable interrupt request signal, and a maskable interrupt request signal from the interrupt request signal generating circuit 54. Outputs a system reset output signal to interrupt request signal generation circuit 54. The system reset signal input to the reset / interrupt controller 52 has a low active level input.
That is, it is reset when the input signal switches from the high level to the low level. Similarly, the user reset signal input to the reset / interrupt controller 52 is low active and level input. The interrupt request signal generating circuit 54 may not be provided.

The mounting chip 23 is provided with an address decode circuit 57 and a data output time adjustment circuit 58. An external I / O is provided to the address decode circuit 57.
O67 is connected to the external ROM 10c. The address decode circuit 57 sets an external input / output map area and an external ROM area to a space on a memory (physical address) (address select signal generation). Has a function. This external input / output map area has an external input / output map area size of 256B to 2KB.
And chip select signals (six) can be assigned to each of the eight divided areas. Also,
The external ROM area generates a chip select signal for the external ROM 10c. The data output time adjustment circuit 58 is used to interface with low-speed input / output devices.
Provides a weight function to extend the machine cycle. By setting, a wait state for a maximum of four machine cycles is possible. The output signal from the address decode circuit 57 is also input to the I / O port 44, and the input / output port is specified by specifying the bit of the I / O port 44 according to the output address. I have.

The I / O port 44 has 8 bits (port A
And a 4-bit (for port B) peripheral device interface port (PIP). These port terminals serve as a chip select terminal for external input / output and a handshake terminal (for one port) in addition to a general-purpose input / output port function. As shown in FIG.
There are three modes, a, b, and c, and a selection command for selecting one of the three modes is given from the external ROM 10 c to the I / O port 44 via the CPU 40. When the mode c is selected, an 8-bit general-purpose input / output port for setting input / output in units of bits and 6b
It provides a chip select function for it. To have a handshake function, the mode a or b is selected. Then, 8b that I / O setting can be done in Byte unit
It provides a general purpose input / output port. However, two terminals (P8, P9) are set as handshake terminals for port A, and timing signals and read / write signals are input / output to / from these handshake terminals P8, P9. This handshake terminal can be set to interrupt. In addition, routing of the handshake terminal interrupt can be set for maskable interrupt exception processing. Mode a
Is selected, the terminals P10 to P13 become chip select signal ports, and when mode b is selected, the terminals P10 to P13 become PIPs for port B without the handshake function.

Various drive circuits 55 and various switch circuits 56 of the gaming machine are connected to the I / O port 44. Then, signals from the various switch circuits 56 are given to the CPU 40 via the I / O port 44, and control signals from the CPU 40 are given to the various drive circuits 55 via the I / O port 44.

The watchdog timer 60 provided on the mounting chip 23 provides a function of detecting a malfunction (runaway) due to a cause such as a noise or a drop in a power supply voltage and returning to a normal state. The signal from watchdog timer 60 is applied to system check circuit 61 and reset / interrupt controller 52. The watchdog timer 60 is configured to output a watchdog timer signal when the reset timing of the timer is equal to or longer than the maximum allowable reset interval time. The maximum allowable reset interval time can be set by the gaming machine maker 4 to a desired time. Furthermore, this watchdog timer 60 is an 8-bit
The clock unit time of the timer can be set by the function of the prescaler. The output of this watchdog timer signal can be set for routing to any one of the exception processing of user reset, maskable interrupt, and non-maskable interrupt. The system check circuit 61 may not be provided.

Address bus terminals (16 terminals) and data bus terminals (8 terminals) are connected to the external bus interface 43 provided on the mounting chip 23, and address bus signals and data bus signals are output respectively. You.
From the external bus interface 43, a signal indicating that the data bus is in a read cycle, a signal indicating that the data bus is in a write cycle, a signal indicating that access to the memory space is being performed, and an operation code fetch cycle is being executed. A signal indicating the presence is output. These output signals are output to the one-chip microcomputer ICE adapter boat 59 (see FIG. 5) during program development. All of the input / output terminals of the mounting chip 23 except for the output terminal from the security check circuit 62 to the monitor device 60 are connected to the one-chip microcomputer ICE adapt board 59. Further, the address bus signal from the address bus terminal and the data bus signal from the data bus terminal are connected to external I / O
It is also output to port 67 and external ROM 10c.

In the figure, reference numeral 69 denotes a large-capacity capacitor;
This is for backing up the power supply of AM41.
In some cases, the capacitor 69 is not provided. This R
The AM 41 is configured to be able to perform bank switching by a bank switching signal from the security check circuit 62. This will be described with reference to FIG.

FIG. 3 is an explanatory diagram showing a memory map. As shown in FIG. 3, addresses 0000 to 7FFF
Are the addresses allocated to the external ROM 10c,
8000 to 81FF are addresses allocated to the RAM 41, and F000 to F7FF are external I / O.
Address assigned to 67, from FF00 to FFF
Addresses up to F are addresses allocated to the internal I / O 44.
Then, the RAM 41 stores the address from 8000 to 81FF.
Up to 256 / 512B (capacitor 6
9 is possible) and 256B. In the case of a general user mode described later, a working area of 256 / 512B is used. In the case of a user test mode described later, bank switching is performed and the working area of 256B is used. Of the 256 / 512B, 256 is for a pachinko game machine and 512 is for a slot machine.

The security check circuit 62 provided on the mounting chip 23 includes a CPU 63, a ROM 64, an R
It has an AM 65, and the ROM 64 stores a program shown in FIG.

The program will be described with reference to FIG. The power is turned on, the system is reset, and in step S (hereinafter simply referred to as S) 1, it is determined whether a security code is written in the security check circuit 62 or not. When the power is turned on for the first time after the ROM 10c is mounted on the same base as the substrate 22 on which the mounting chip 23 is mounted, the process proceeds to S2 because the security code has not yet been written in the security check circuit. In S2, a process of checking the consistency between the security code written in the external ROM 10c and the program data in the external ROM 10c is performed. The security code written in the external ROM 10c is, as described with reference to FIG. 1, a security code added to a development program deemed to be passed by a third-party testing institution or the supervisory authority 25. This is a code obtained by converting the program data of the external ROM 10c according to a certain conversion format. Then, the conversion format is already stored in the ROM 64 of the security check circuit 62, and the consistency between the security code written in the external ROM 10c and the program data is checked in accordance with the stored conversion format. The conversion format is stored in the ROM 64 of the security check circuit 62 in advance.
Instead, the conversion format may be written in the ROM 10b determined to be acceptable by a third-party testing organization. In that case, the security check circuit 62 checks the consistency between the security code written in the ROM and the program data based on the conversion format and the security code. Next, the process proceeds to S3, where it is determined whether the result of the check is proper. If the result is proper, the process proceeds to S4. After the process of writing the security code in the security check circuit 62 is performed, the process proceeds to S7. In this case, the program data in the ROM may be directly written as security data into the security check circuit. In S7, a process is performed in which the CPU 40 is activated without a time limit to enter a general user mode in which normal gaming machine control is performed. Also in this case, if there is a system runaway or the like, the system is reset and the processes after S1 are performed again. In addition,
In this embodiment, the substrate 2 on which the mounting chip 23 is mounted
The security code is written in the security check circuit 62 when the power is turned on for the first time after the ROM 10c is mounted on the same board as the game machine 2.
May receive the mass-production master chip in which the security code corresponding to the mass-production master ROM 10b is written from the third-party test institution 11, copy it to the mass-production chip 23a, and mount it on the board 22. Also, the mounting chip 23 is provided by a dedicated security code writing device.
The security code may be written in the (mass production chip 23a).

On the other hand, when the power is turned on and the system is reset, and the security code has already been written in the security check circuit, YES is determined in S1.
Is determined, the flow advances to S5, and the consistency between the security code in the ROM 10c and the security code already written in the security check circuit is checked. It should be noted that, even when the determination of YES is made in S1, the same determination as in S2 and S3 may be performed, and the process may proceed to S5 only when the consistency of the security code in the ROM with the program data is proper. Next, the process proceeds to S6, and it is determined whether or not the result of the check is proper. If the result is proper, the process proceeds to S7. If not, the process proceeds to S8, and the CPU 40 is controlled for a predetermined time (for example, Activation processing is performed only for 60 seconds), and the mode shifts to the user test mode. Then, if a certain time has elapsed or if there is a system runaway or the like, the system is reset again, and the processing after S1 is performed. By this S5, predetermined security information is stored in a state where the read-only memory storing the passing program is mounted, and the security information is used as a clue to store the program stored in the mounted read-only memory. Is a means for judging whether or not is a proper one that has passed the test of the third party. On the other hand, if it is determined that the result of the check in S3 and S6 is appropriate, the ROM 41 uses the working area of 256 / 512B as described above, while the result of the check in S3 and S6. When it is determined that the data is incorrect, the security check circuit 62 outputs a bank switching signal to the RAM 41 as shown in FIG.
The working area is switched to the working area 56B. When the CPU is activated only during the time limit (for example, 60 seconds) by S8, the operation of the microcomputer within the time limit is 256 times of the RAM 41.
It will be performed in the working area of B. One of the reasons why the CPU 40 is activated only for a predetermined time (for example, 60 seconds) even if the result of this check is inappropriate is, for example, the shipment of the gaming machine 21 shown in FIG. In some cases, the board may be checked again or the control of the variable display device or the like provided on the game board may be checked again. In this case, the mounting ROM 10c already mounted on the board 22 may be pulled out once and another check program may be executed. This is for performing a check by inserting the ROM in which the ROM is stored, and even if a ROM in which a program different from the passing program is stored is mounted, a predetermined time (for example, 6
Only for 0 second), the microcomputer operates so that the above-mentioned check can be performed. Another reason is that a program development company for controlling a gaming machine creates a program, passes the test of the third-party testing institution 11 and passes the test, and then stores the ROM 10c storing the passed program and the chip 23 on the substrate 22. This is because a board check may be performed before mounting and shipping to the gaming machine maker 4. In this case, the board check is performed by replacing the test ROM with a test ROM in which a test program in which the control time is shortened, for example, by shortening the opening period of the variable prize ball device at the time of a big hit, is used instead of the pass ROM. It is mounted on the substrate 22 so that an input / output test can be quickly performed within a short time limit (for example, 60 seconds). In the case of such a user test mode, the reason for switching the working area of the RAM 41 to 256B is that if the working areas of the general user mode and the user test mode are made the same, a program for program modification is stored. The illegally inserted ROM is improperly inserted into the board 22, and the microcomputer is operated according to the program for the program modification for a limited time (for example, 60 seconds) to rewrite various constants and the like stored via the RAM 41, and later passed. Even if the external ROM 10c in which the program is stored is mounted on the board 22, the constants and the like have already been rewritten, which causes a problem that the microcomputer operates improperly. In the test mode, general user mode The de is to so as to operate in different working areas.

Further, S1 to S3 or S3 shown in FIG.
The time required for the security check in steps S1, S5 and S6 is set to, for example, about 3 to 5 seconds. Such 3
The reason why the configuration is such that the time is set to a relatively long time of about 5 seconds is that when a ROM storing an illegally modified program other than the passing program is mounted on the board 22, the above-mentioned 3 times is required every time the time limit elapses. Perform security check for ~ 5 seconds and make CPU inoperable during that time,
This is because the CPU is stopped for a long period of about 3 to 5 seconds and the gaming machine is intentionally not operated normally, so that an illegally remodeled program may interfere with the game. If the time limit (for example, 60 seconds) has elapsed in S8, the CPU may not be activated until the power is turned on next time. This 3-5
The security check processing time on the order of seconds and the above-mentioned time limit (for example, 60 seconds) become shorter when the oscillation frequency of the crystal oscillator 45 becomes higher, and become longer when the oscillation frequency becomes lower. When the monitor device 60 is connected to the security check circuit 62 as shown in FIG. 2, it is possible to determine whether the current mode of the chip is the general user mode or the user test mode. In the figure, 66 and 68 are data buses.

The development chip 23b is the same as the mass production chip 23a except that the security check circuit 62 shown in FIG. 2 does not exist. In addition,
The security check circuit 62 is also provided for the development chip 23b.
May be provided so that a program for performing a security check is not stored in the ROM 64.

The mass production chip 23a and the development chip 2
3b is a so-called ASIC (application)
specific integrated circuit
t), which is a chip dedicated to pachinko gaming machines and slot machines. Further, a chip for limiting the gaming machine maker 4 may be used.

FIG. 6 is a block diagram showing a part of a microcomputer development system when a program is developed using a development chip in a development section of a gaming machine maker.

In the figure, reference numeral 80 denotes an ICE for CPU, which is a commercially available product. ICE (in-circuit emulato
r) is MDS (microcomputer de
The emulation of the hardware of the microcomputer system is performed under the "development system". The CPU ICE 80 is an ICE for a gaming machine control microcomputer before being made into a single chip, and develops a microcomputer program by effectively utilizing this commercially available conventional CPU ICE 80. For this purpose, the one-chip microcomputer ICE adapter board 59 is required. This one-chip microcomputer ICE
The adapter board 59 is sold by the chip distribution company 2 shown in FIG. The CPU probe 81 of the CPU ICE 80 is connected to the CPU socket 84 of the one-chip microcomputer ICE adapter board 59, and the one-chip microcomputer probe 82 and the product development board 83 of the one-chip microcomputer ICE adapter board 59 are connected. The microcomputer program can be developed with the one-chip microcomputer socket 84 connected. Reference numeral 10 denotes a ROM connected to the development chip 23b.

[0039]

The system according to the present invention relates to a gaming machine carried into a game arcade, and when an unauthorized modification to operate the central processing unit by an unauthorized program other than the passing program is performed, the appropriateness is determined by the appropriateness determining means. Therefore, it is easy to prevent the gaming machine from being controlled by the unauthorized program.

[Brief description of the drawings]

FIG. 1 is a system block diagram schematically showing a security system of a gaming machine control microcomputer according to the present invention.

FIG. 2 is a block diagram showing a mounting chip constituting a gaming machine control microcomputer used in the present invention and circuits of peripheral devices connected thereto.

FIG. 3 is an explanatory diagram showing a memory map of a gaming machine control microcomputer used in the present invention.

FIG. 4 is an explanatory diagram for explaining a function corresponding to a mode of an I / O port.

FIG. 5 is a flowchart showing a program stored in a ROM provided in a security check circuit of the gaming machine control microcomputer.

FIG. 6 is a block diagram showing a part of a development system of the gaming machine control microcomputer.

[Explanation of symbols]

 21 Pachinko machine as an example of a game machine 23 Mounting chip 10c Mounting ROM 4 Game machine maker as an example of a development and manufacturing company

Claims (1)

(57) [Claims] 1. A step of developing a program for a central processing unit of a microcomputer for controlling a gaming machine and storing the program in a read-only memory, and determining whether the developed program passes a certain standard. And a step of using in a game arcade where a gaming machine equipped with a microcomputer having a read-only memory storing a program that has passed the test is installed. Providing predetermined security information to the program only when the program passes a certain standard; writing the provided security information to a read-only memory; and Using the security information as a clue to the computer, Determining whether or not the program stored in the only memory is appropriate and has passed the test.The microcomputer is configured to operate only when the microcomputer determines that the program is appropriate in the step. A microcomputer security system for gaming machine control.