JP3565174B2 - Control device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a control device, and more particularly, to a control device that determines whether a program storage element is a genuine product during operation of a control computer.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, this type of control device usually includes a program storage element (for example, a PROM, a mask ROM, etc.) for storing a control program describing a control rule, and reads and executes the control program from the program storage element in a predetermined order. And a logic circuit centered on a controlling computer. Therefore, if a predetermined control program is stored in the program storage element in advance, the device incorporating this control device is controlled according to a certain control procedure according to the description of the control program.
[0003]
In addition, the control device configured as described above can easily change a control procedure of a device incorporating the control device by changing a control program stored in a program storage element, and has a system flexibility. And reduce the system development load.
[0004]
[Problems to be solved by the invention]
However, the control device configured as described above has a problem in that the control program can be easily modified because the system has a high flexibility, which is a feature of the control device. In particular, when there is a regulation or the like on the control contents, modification of the control program is illegal and it is necessary to prevent this sufficiently. It was difficult to take sufficient precautionary measures against fraud.
[0005]
In order to solve such a problem, the applicant has previously filed a separate application for identifying whether or not a program storage element is a genuine product before executing device control in accordance with a control program (Japanese Patent Application Laid-Open No. 2002-214,009). Hei 4-168487). The control device of the present invention has the following configuration for the purpose of obtaining high reliability against such a problem and against human and organizational fraud.
[0006]
[Means for Solving the Problems and Their Functions and Effects]
The control device of the present invention
A control device used for a gaming machine, has a control computer that reads a program stored in a program storage element in a predetermined procedure, and controls the operation of the device according to the program, and during the operation of the control computer, A control device for determining whether the program storage element is a genuine product,
Bus unoccupied state detection means for detecting a bus unoccupied state in which the control computer does not occupy a bus in order to exchange data with the program storage element;
When detecting the bus non-occupancy state,Stored in the program storage element using a busPredetermined dataReading means for reading
Read by the reading meansPredetermined dataStorage element determining means for determining whether the program storage element is a genuine product based on
When the storage element determination unit determines that the program storage element is not a genuine product, the operation unit includes an operation change unit that changes an operation of the control computer,
The gist is that the operation changing means is means for causing the control computer to execute a demonstration program.
[0007]
The control device of the present invention configured as described above can store a program using the bus by the readout unit at a predetermined timing, for example, when the bus unoccupied state detection unit detects the unoccupied state of the bus by the control computer. The stored content is read from the element, and the storage element determining means determines whether or not the program storage element is a genuine product based on the read content. When the storage element determining means determines that the program storage element is not a genuine product, the operation changing means causes the control computer to execute the demonstration program.
[0008]
In such a control device, while the control computer is operating, it is determined whether or not the program storage element is a genuine product. Illegal fraud can be effectively prevented, and high reliability can be obtained. Moreover, when the control computer determines at a predetermined timing, for example, when the bus is not occupying the bus, the program storage element is used to determine whether or not the program storage element is a genuine product. It is possible to make it difficult to determine whether the data is read by the computer or read by the reading means.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
In order to further clarify the configuration and operation of the present invention described above, a preferred embodiment of the control device of the present invention will be described below. FIG. 1 is a schematic configuration diagram showing a main part of a control system of a pachinko machine equipped with a pachinko machine control device as one embodiment of the present invention.
[0010]
As shown in the figure, the pachinko machine control device 1 has a one-chip microcomputer 2, a ROM 30 as a program storage element, an oscillation crystal 18 external to the one-chip microcomputer 2, and a stabilized whole circuit. It comprises a power supply circuit 28 for supplying power, a driver 40 and a waveform shaping circuit 50. The one-chip microcomputer 2 and the ROM 30 are connected by a control bus CB, an address bus AB and a data bus DB. The one-chip microcomputer 2 is composed of a logic circuit mainly including a CPU 10 for controlling the pachinko machine and a CPU 20 for checking whether the ROM 30 is a genuine product.
[0011]
The CPU 10 is an 8-bit microcomputer of the "Z80" system, and has a control bus control circuit 10a having control ports for signals MREQ #, RD #, M1 #, etc., an address bus control circuit 10b having an address port, and data having a data port. A bus control circuit 10c is provided. Here, "@" appended to the signal name means that the port is low active.
[0012]
The control port and the address port of the CPU 10 are connected to the control bus CB and the address bus AB via the bus driver 16, and the data port is connected to the data bus DB. The various buses CB, AB, and DB are connected to a RAM 12 for temporarily storing necessary data and an input / output interface circuit (hereinafter, referred to as I / O) 14. The control port of the CPU 10 is connected to the control signal control circuit 21.
[0013]
The control signal control circuit 21 is a logic circuit that generates control signals such as the signal G1, the signal G2, the signal CL1, the signal MREQ2 #, and the signal RD2 # based on the signal RFSH # or the like output from the CPU 10. The control signal control circuit 21 is connected to the CPU 20, the bus driver 16, the bus driver 23 and the latch circuit 25 via the control sub-bus SB, and outputs the signals G1 and G2 to output the bus driver 16 and the bus driver 23. The state is controlled, the latch timing of the latch circuit 25 is controlled by the output of the signal CL1, and the CPU 20 is notified of where the control bus CB and the like are being used. Further, the control signal control circuit 21 is connected to the control bus CB via the control sub-bus SB and the bus driver 23, and transmits a signal MREQ2 # and a signal RD2 # generated based on the signal RFSH # or the like to the control bus. Each logic circuit is controlled by outputting a signal MREQ # and a signal RD # to the CB.
[0014]
Of the control signals, signal G1 is output as a signal indicating the same output as signal RFSH #. The signal G2 becomes high level (hereinafter, described as "H") slightly after the signal RFSH # becomes low level (hereinafter, described as "L"), and the signal RFSH # becomes "H". It is output as a signal that becomes "L" slightly earlier. The signal CL1 is output as an inverted pulse signal in the latter half of the refresh time of the CPU 10. Signal MREQ2 # and signal RD2 # are output as "L" when signal G2 is "H", and are output as "H" when signal G2 is "L".
[0015]
The bus driver 16 is composed of a tri-state buffer, and inputs a signal G1 output from the control signal control circuit 21 via the control sub-bus SB to enable or disable the output from the control port and the address port. Set to impedance state. That is, when the signal G1 is "H", the output from each port is made valid, the CPU 10 issues various control signals to the ROM 30, RAM 12, and I / O 14 via the control bus CB, and outputs the address via the address bus AB. Can be specified. Conversely, when the signal G1 is "L", the state is set to the high impedance state, and the CPU 10 is not connected to the buses CB and AB.
[0016]
The RAM 12 is a storage element in which necessary data is temporarily stored when the CPU 10 executes the control program stored in the ROM 30. To temporarily store data in the RAM 12, the CPU 10 outputs an address to store data to the address bus AB via the bus driver 16, sets the signal MREQ # to "L", and stores data to be stored from the data bus DB. When the signal WR # indicating that the data to be output and stored is being output to the data bus DB is set to "L", the operation is performed by the RAM 12 taking in the data from the data bus DB. When the CPU 10 needs the data stored in the RAM 12, the CPU 10 outputs an address storing data to be read via the bus driver 16 from the address bus AB, sets the signal MREQ # to "L", and sets the signal RD By setting ＼ to “L”, data output to the data bus DB from the designated address of the RAM 12 is read.
[0017]
The I / O 14 is a circuit for matching signals between the pachinko machine control device 1 and various electric devices provided in the pachinko machine. Therefore, the I / O 14 is connected to the buses CB, AB, and DB and is incorporated in a logic circuit centering on the CPU 10 and is connected to electrical equipment provided in the pachinko machine, for example, the main unit winning switch 52, the digital start switch 51, and the like. The waveform shaping circuit 50, the hit lamp 43 of the pachinko machine main body, the display device 42 which is a set of LEDs in the digital part of the center role, the driver 40 connected to the solenoid 41 for opening a big winning opening, and the like. ing.
[0018]
In addition to the above configuration centering on the CPU 10, a logic circuit for determining whether or not the ROM 30 is genuine is provided centering on the CPU 20. The CPU 20 has a ROM 20d and a RAM 20e built therein, and a check program to be described later is non-volatilely burned into the internal ROM 20d. The CPU 20 includes a data input circuit 20c having input ports Q0 to Q7, a data output circuit 20f having output ports P0 to P15, a control signal input port P17 of the CPU 20, and a control signal output port P18 #. Have.
[0019]
The data output circuit 20f of the CPU 20 is connected to the address bus AB via the bus driver 23, sets predetermined address data in the output ports P0 to P15 according to a program stored in the internal ROM 20d, and outputs the data. Output. The bus driver 23 interposed between the data output circuit 20f and the address bus AB is formed of a tri-state buffer similarly to the bus driver 16, and transmits the signal G2 output from the control signal control circuit 21 to the control sub-bus SB. , The output from the output ports P0 to P15 to the address bus AB is set to a valid or high impedance state. That is, when the signal G2 is "H", the output from the output ports P0 to P15 to the address bus AB is enabled, and when the signal G2 is "L", the output ports P0 to P15 and the address bus AB are set to a high impedance state. And are not connected.
[0020]
Therefore, by adjusting the signals G1 and G2 output from the control signal control circuit 21, the data from the address bus control circuit 10b of the CPU 10 and the data from the output ports P0 to P15 of the CPU 20 are stored in the address bus AB. Is selectively output. That is, when the signal G2 is set to “L”, the output of the bus driver 23 is set to a high impedance state, and when the signal G1 is set to “H”, the control bus control circuit 10a and the address bus control of the CPU 10 are controlled via the bus driver 16. The connection between the circuit 10b and the control bus CB and the address bus AB is made valid. Conversely, when the signal G1 is set to "L", the output of the bus driver 16 is set to a high impedance state, and when the signal G2 is set to "H", the output ports P0 to P15 of the CPU 20 are connected to the address bus via the bus driver 23. The connection with AB is made valid.
[0021]
A data bus DB is connected to input ports Q0 to Q7 of the CPU 20 via a latch circuit 25. The latch circuit 25 inputs and holds data output to the data bus DB when a control signal is input to its CLK terminal. The CLK terminal of the latch circuit 25 is connected to the control signal control circuit 21 via the control sub-bus SB. When the signal CL1 output from the control signal control circuit 21 changes from “L” to “H”, the data is output. The data output to the bus DB is latched and then held until the signal CL1 changes from "L" to "H".
[0022]
The output port P18 # of the CPU 20 is connected to the port RESET # of the CPU 10 via the OR circuit 26 together with a signal line from outside the pachinko machine controller 1, and the CPU 20 sets the signal P18 # to "L". The CPU 10 can be in a reset state.
[0023]
On the other hand, the ROM 30 is a storage element for storing a control program executed by the CPU 10 and various data necessary for executing the program in a nonvolatile manner, and receives an address designation from the CPU 10 and outputs data stored at the address. I do. That is, the ROM 30 stores information such as a control program based on a game rule to be executed as the pachinko machine control device 1.
[0024]
Next, the operation of the pachinko machine control device 1 during the instruction fetch cycle of the CPU 10 will be described with reference to FIG. FIG. 2 is an explanatory diagram showing an instruction fetch cycle of the CPU 10 and timings of operations of the CPU 20 and the like. As shown in FIG. 2, the CPU 10 of the "Z80" system sets the signal M1 # to "L" to indicate that it is the first cycle of the instruction fetch cycle (Machine cycle one) while synchronizing with the clock Φ. The signal MREQ # for indicating a request to access the storage element and the signal RD # for indicating a read request are set to "L" a little later. In addition, the storage element does not output the signal WAIT # at the falling edge of the clock Φ in the T2 state so as not to hinder data reading even if the access time of the storage element is slow. In this case, a wait cycle is provided to delay the data read timing.
[0025]
Therefore, the actual instruction fetch by the CPU 10 is executed when certain conditions determined by the above-mentioned signals are satisfied, and is stored in the address AD1 designated by the address bus AB at that time, and is stored in the data bus DB. The output data D1 is captured as an instruction. As is well known, the instruction fetched in this way is stored in an instruction register in the CPU 10, and the operation of the CPU 10 in the next execution cycle is determined.
[0026]
In the T3 and T4 states of the instruction fetch cycle of the CPU 10, the signal RFSH # is set to "L" to refresh the dynamic RAM. In the "Z80" CPU 10, when the signal RFSH # becomes "L", a refresh signal is output to the lower 8 bits of the address ports A0 to A15.
[0027]
On the other hand, the CPU 20 sets and outputs predetermined address data AD2 to the output ports P0 to P15 according to the program stored in the internal ROM 20d.
[0028]
When the signal RFSH # of the CPU 10 becomes "L", the control signal control circuit 21 changes the signal G1 to "L" based on this signal, and further slightly delays the signal G2 to "H". The bus driver 16 puts its output into a high impedance state when the signal G1 goes "L", and the bus driver 23 sends the output ports P0-P15 of the CPU 20 to the address bus when the signal G2 goes "H". The connection with AB and the connection between control sub-bus SB and control bus CB are made valid. Therefore, no refresh signal is output from the address port of CPU 10 to address bus AB.
[0029]
Further, a signal MREQ2 # and a signal RD2 # are output from the control signal control circuit 21 to the control bus CB as a signal MREQ # and a signal RD # via the control sub-bus SB and the bus driver 23. Address data AD2 set in advance by the CPU 20 in the output ports P0 to P15 is output. With this output, the ROM 30 outputs the data D2 stored at the specified address AD2 to the data bus DB. The data D2 is latched by the latch circuit 25 by inputting the inverted signal CL1 to the CLK terminal of the latch circuit 25, and is output to the input ports Q0 to Q7 of the CPU 20. Thereafter, the CPU 20 adjusts the timing based on the signal G2 input to the input port P17, and then takes in the data D2 from the input ports Q0 to Q7.
[0030]
Among the above operations, the operation until the address data AD2 is output from the output ports P0 to P15 to the address bus AB and the data D2 output from the ROM 30 is latched by the latch circuit 25 with the output of the data AD2 is as follows. This is performed within one refresh time of the CPU 10. As described above, since the data D2 is read using the various buses CB, AB, and DB during the refresh time of the CPU 10, the operation of the CPU 10 is not hindered. Further, in this embodiment, since the pachinko machine control device 1 does not have a dynamic RAM, there is no limitation due to the refresh signal not being output to the address bus AB.
[0031]
In this embodiment, the CPU 20 reads data from the ROM 30 every time the CPU 10 is refreshed. However, when an address to be read from the ROM 30 is set in the data output circuit 20f, the data is ready to be read. It is also preferable that the control signal is output from the CPU 20 to the control signal control circuit 21, the control signal control circuit 21 operates only when the control signal is output, and the data in the ROM 30 is read when the CPU 10 is subsequently refreshed. It is. In this case, the port P17 of the CPU 20 is used as a control signal input / output port, and the CPU 20 outputs a control signal to the control signal control circuit 21 from the port P17.
[0032]
The pachinko machine control device 1 configured as described above operates as follows. When the power supply circuit of the pachinko machine control device 1 is turned on, the CPU 10 of the one-chip microcomputer 2 receives power supply, sequentially reads out the control programs stored in the ROM 30 according to a predetermined procedure, and writes the control programs described in the programs. Execute the instruction. By the processing of the CPU 10 based on this control program, the pachinko machine behaves in accordance with the game rules described in the control program, and the game described in the control program becomes possible.
[0033]
When the pachinko machine is controlled by the processing of the CPU 10, the CPU 20 executes the check program shown in the flowchart of FIG. The check program shown in FIG. 3 is a program burned into the internal ROM 20d of the CPU 20, and as soon as the power supply to the CPU 20 is started, a process based on the check program is started. Is repeatedly executed. First, the CPU 20 reads an identification code stored in advance at a predetermined address of the ROM 30 (step S100). Next, it is determined whether or not the identification code is a predetermined correct value (step S110). If the identification code is correct, the routine ends. If it is determined that the identification code is not correct, the signal P18 # from the output port P18 # is set to "L" (step S120), and the CPU 10 is reset.
[0034]
Here, whether or not the ROM 30 is legitimate is determined by writing a value correlated with the program code written in the ROM 30 to the internal ROM 20d and determining the value. A predetermined calculation result for the stored data is described in advance at a specific address in the ROM 30, and the CPU 20 reads the data at each address in the ROM 30, performs a predetermined calculation, and compares the result with the value of the specific address to determine. A method for writing a predetermined identification code into both the internal ROM 20d and the ROM 30 of the CPU 20 in advance, and a method for judging the coincidence of the identification code, and recording the same program code described in the ROM 30 in the internal ROM 20d in advance. In advance, the contents of the ROM 30 and the contents of the internal ROM 20d are collated and determined. The method calculates the checksum of the program code described in the ROM 30, determines whether this is a value previously written in the internal ROM 20d, reads the values of a plurality of addresses of the ROM 30 and performs a predetermined calculation. Various methods can be used, such as a method of comparing a calculation result with a value described in advance at a predetermined address of the ROM 30 or a predetermined address of the internal ROM 20d to make a determination.
[0035]
In the present embodiment, the CPU 10 is reset when it is determined that the identification code is incorrect. However, any means that inhibits the normal operation of the CPU 10 may be used. May be stopped. Further, since it is sufficient to stop the normal operation, various measures such as executing a demonstration can be considered.
[0036]
In the pachinko machine control device 1 of the present embodiment configured as described above, immediately after the power is turned on, the check program executed by the CPU 20 repeatedly determines whether or not the ROM 30 is a genuine product. Since the CPU sets the CPU 10 in the reset state and prohibits the operation, no processing based on an illegal control program described in an unauthorized ROM is performed. In addition, since the operation of the CPU 20 for accessing the bus CB and the like is performed only when the CPU 10 is refreshed, which is a time not used for controlling the pachinko machine, there is no hindrance to the control of the pachinko machine by the CPU 10. Therefore, there is no need to change the control program of the pachinko machine control device 1 by the CPU 10 from the conventional one. Further, since the main logic circuit of the pachinko machine control device 1 except for the ROM 30 is formed as a single chip, the determination as to whether the data read command to the ROM 30 is a command from the CPU 10 or a command from the CPU 20 is made by an external device. Is essentially impossible. Therefore, it is not permissible to read illegal program data in the case of a data read command from the CPU 10 and to read regular program data in the case of a data read command from the CPU 20.
[0037]
In addition, the pachinko machine control device 1 of this embodiment performs a check of the ROM 30 after the power is turned on, as compared with the pachinko machine that controls the pachinko machine after checking whether or not the ROM 30 is genuine immediately after the power is turned on. Does not require special time for. Further, since the check of the ROM 30 is always performed during the operation, it is possible to detect a fraud such as operating with the regular ROM 30 from a power-on to a predetermined time and switching to an invalid ROM after a predetermined time has elapsed.
[0038]
Next, a second embodiment of the present invention will be described. FIG. 4 is a schematic configuration diagram showing a main part of a control system of a pachinko machine equipped with a pachinko machine control device as a second embodiment. For the sake of convenience of explanation, components constituted by the same logic circuits as in the first embodiment are given the same reference numerals, and their explanation is omitted.
[0039]
As shown, the pachinko machine control device 1 of the second embodiment includes a one-chip microcomputer 2, a ROM 30, an oscillation crystal 18 externally attached to the one-chip microcomputer 2, as in the first embodiment, It comprises a power supply circuit 28, a driver 40 and a waveform shaping circuit 50.
[0040]
The CPU 60 has a built-in ROM 60d and a RAM 60e therein, and a check program described later is non-volatilely burned into the internal ROM 60d. The CPU 60 includes a control bus control circuit 60a having a control port, an address bus control circuit 60b having an address port, a data bus control circuit 60c having a data port, output ports P61 # and P62 #, and an input port P63.ポ ー ト and INT＼ ports for inputting an interrupt signal.
[0041]
The control port, the address port, and the data port of the CPU 60 are connected to a control bus CB, an address bus AB, and a data bus DB connected to each port of the CPU 10, respectively. Each port of the CPU 60 connected to the various buses CB, AB, and DB is normally in a high-impedance state, and outputs "L" from the port P62 #, and as a result, when "L" is input from the port P63 #. Only the connection by each bus control circuit 60a, 60b, 60c is valid.
The output port P61 # of the CPU 60 is connected to the port RESET # of the CPU 10 via the OR circuit 26 together with a signal line from outside the pachinko machine controller 1, and the CPU 10 is set by setting the signal P61 # to "L". Reset state. The output port P62 # of the CPU 60 is connected to the input port BUSRQ # of the CPU 10, and requests the CPU 10 to have the bus occupation right by setting the signal P62 # to "L". When receiving signal P62 #, CPU 10 sets the connection to buses CB, AB, and DB to a high impedance state. At this time, the CPU 10 sets the output port BUSAK # to "L". Since output port BUSAK # is connected to input port P63 # of CPU 60, CPU 60 detects the occupation state of CPU 10 for buses CB, AB, and DB by inputting signal BUSAK #. After the CPU 60 uses the bus, the signal P62 # is set to "H" to re-enable the connection between the CPU 10 and the buses CB, AB, and DB.
[0042]
Input port INT # of CPU 60 is connected to interrupt signal generation circuit 62. The interrupt signal generating circuit 62 is a logic circuit that generates an interrupt signal at random. When a signal generated by the interrupt signal generation circuit 62 is input to the input port INT #, the CPU 60 activates an interrupt process according to a predetermined sequence and executes a check program described later. The frequency of occurrence of the interrupt signal is determined by the frequency at which the CPU 60 checks the ROM 30, the number of times data is read into the ROM 30 required for checking by the check program, and the like. In the second embodiment, it is set so that the number of machine cycles of the CPU 10 is once every 55 times between 10 and 100 times. In the second embodiment, the configuration is such that the interrupt signal is randomly generated. However, a configuration in which the interrupt signal is generated at a constant cycle may be used.
[0043]
In the pachinko machine control device 1 of the second embodiment configured as described above, when the pachinko machine is controlled by the processing of the CPU 10, the CPU 60 executes the check program shown in the flowchart of FIG. The check program shown in FIG. 5 is a program burned into the internal ROM 60d of the CPU 60. Every time a signal from the interrupt signal generation circuit 62 is input to INT #, processing based on this check program is started, Is repeatedly executed while the is supplied. First, when interrupt signal INT # is input to CPU 60, signal P62 # is set to "L" (step S200). When signal P62 # is set to "L", CPU 10 sets the connection to buses CB, AB, and DB to a high impedance state after the end of the currently executed machine cycle, and suspends the control of the pachinko machine. As will be described later, the pachinko machine control is interrupted for only a few machine cycles of the CPU 60, so that the game is apparently continued without any trouble.
[0044]
Next, waiting for the signal input to input port P63 # to become "L" (step S210), the connection between CPU 60 and buses CB, AB, and DB is validated (step S220). When the connection to the buses CB, AB, and DB is in a high impedance state, the CPU 10 sets the signal BUSAK # to "L". Therefore, the CPU 60 receives this signal and enables the connection to the buses CB, AB, and DB. For example, the connection of the CPU 10 and the CPU 60 to the buses CB, AB, and DB at the same time is not effective.
[0045]
The identification code is read from the predetermined address of the ROM 30 using the buses CB, AB, and DB for which the connection has been made effective (step S230). When the identification code is read, the connection between the CPU 60 and the buses CB, AB, and DB is set to a high impedance state (step S240), and the signal P62 # is set to "H" (step S250). By setting signal P62 # to "H", the connection between CPU 10 and buses CB, AB, and DB is made valid, and control of the pachinko machine by CPU 10 is restarted. Accordingly, the interruption of the control of the pachinko machine by the CPU 10 is only an access time to the ROM 30 and is extremely small, so that the interruption of the control does not affect the pachinko machine user.
[0046]
Next, it is determined whether or not the identification code read from the ROM 30 is a predetermined correct value (step S260). If the identification code is correct, the routine ends. If it is determined that the identification code is not correct, signal P61 # from the output port is set to "L" (step S270), and CPU 10 is reset.
[0047]
Here, the method of determining whether the ROM 30 is genuine and the method of determining when the identification code is incorrect can be considered in various ways and various ways as described in the first embodiment. . For example, a predetermined calculation result for data stored in a plurality of addresses of the ROM 30 is described in a specific address of the ROM 30 in advance, the data of each address of the ROM 30 is read by the CPU 20 and a predetermined calculation is performed. And a method of discriminating by comparing with the value of.
[0048]
In the pachinko machine control device 1 of the second embodiment configured as described above, immediately after the power is turned on, the check program executed by the CPU 60 repeatedly determines whether or not the ROM 30 is genuine, and determines that the ROM 30 is genuine. At this time, the operation is prohibited by setting the CPU 10 in a reset state, so that no processing based on an illegal control program described in an unauthorized ROM is performed. In addition, since the timing at which the CPU 60 executes the check program is determined by an interrupt signal generated at random, it is possible to prevent the CPU 60 from reading the ROM 30 in advance. Therefore, no unauthorized ROM control is performed. Further, since the CPU 60 checks the ROM 30 using the buses CB, AB, and DB for a time that does not hinder the control of the pachinko machine by the CPU 10, there is no hindrance to the game. The other effects are the same as in the first embodiment.
[0049]
The configuration and operation of the pachinko machine control device 1 have been described above as an example of the control device of the present invention. However, the present invention is not limited to such an example. The reliability of the control program, such as the configuration incorporated as a control device, the configuration of the control computer and the logic circuit for judging the program storage element using different chips, the lock management system for building entrances, office entrances, safe doors, etc. Of course, the present invention can be implemented in various modes without departing from the gist of the present invention, such as a configuration incorporated in a security system in which importance is particularly attached.
[Brief description of the drawings]
FIG. 1 is a block diagram of a pachinko machine control device as one embodiment of the present invention.
FIG. 2 is an explanatory diagram showing an instruction fetch cycle in the CPU of the pachinko machine control device 1 and timings of operations of the CPU 20 and the like.
FIG. 3 is a flowchart of a check program executed by a CPU 20.
FIG. 4 is a block diagram of a pachinko machine control device as a second embodiment.
FIG. 5 is a flowchart of a check program executed by a CPU 60;
[Explanation of symbols]
1 ... Pachinko machine controller
2. One-chip microcomputer
10 CPU
10a: Control bus control circuit
10b: Address bus control circuit
10c: Data bus control circuit
12 ... RAM
14 ... I / O
16 Bus driver
18… Crystal for oscillation
20 ... CPU
20c Data input circuit
20d ROM
20e ... RAM
20f Data output circuit
21 ... Control signal control circuit
23 Bus driver
25 ... Latch circuit
26 ... OR circuit
28 Power supply circuit
30 ROM
40 ... Driver
41 ... Solenoid
42 ... Display device
43… Lamp
50 ... waveform shaping circuit
51 Digital start switch
52 ... Winning switch
60 CPU
60a: control bus control circuit
60b: Address bus control circuit
60c Data bus control circuit
60d ROM
60e ... RAM
62 ... Interrupt signal generation circuit
AB: Address bus
CB: Control bus
DB: Data bus
SB: Control sub bus

Claims (3)

A control device used for a gaming machine, has a control computer that reads a program stored in a program storage element in a predetermined procedure, and controls the operation of the device according to the program, and during the operation of the control computer, A control device for determining whether the program storage element is a genuine product,
Bus unoccupied state detection means for detecting a bus unoccupied state in which the control computer does not occupy a bus in order to exchange data with the program storage element;
Reading means for reading predetermined data stored in the program storage element using the bus when detecting the bus non-occupancy state ;
Storage element determining means for determining whether or not the program storage element is a genuine product, based on predetermined data read by the reading means;
When the storage element determination unit determines that the program storage element is not a genuine product, the operation unit includes an operation change unit that changes an operation of the control computer,
The control device, wherein the operation changing unit is a unit that causes the control computer to execute a demonstration program. 2. The control device according to claim 1, wherein said reading means and said storage element determining means repeatedly perform said reading and determination at predetermined intervals. 2. The control device according to claim 1, wherein said read means and said storage element judgment means perform said read and judgment at random timing.

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