JP3501129B2 - Control device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a control device,
More specifically, the present invention relates to a control device that determines whether a program storage element is a genuine product during operation of a control computer.

[0002]

2. Description of the Related Art Conventionally, a control device of this type usually controls a program storage element (for example, PROM, mask ROM, etc.) for storing a control program describing a control rule, and controls the program storage element in a predetermined order. It is composed of a logic circuit centering on a control computer that reads and executes a program. Therefore, if a predetermined control program is stored in the program storage element in advance, the device incorporating this control device is controlled by a certain control procedure according to the description of the control program.

Further, the control device configured as described above is
By changing the control program stored in the program storage element, it is possible to easily change the control procedure of the device incorporating this control device, increase the flexibility of the system, and reduce the development load of the system. .

[0004]

However, the control device thus constructed has a problem that the control program can be easily modified because the system, which is a characteristic of the control device, has high flexibility. In particular, if the control contents are regulated by law etc., modification of the control program is illegal and it is necessary to sufficiently prevent it.
It was difficult to take sufficient preventive measures against artificial and systematic fraud such as replacing the program memory element.

To address such a problem, the applicant has previously separately applied for a configuration for identifying whether or not the program storage element is a genuine product before executing the device control according to the control program. (Japanese Patent Application No. 4-168487). With respect to such a problem, the control device of the present invention has the following configuration for the purpose of obtaining high reliability against artificial and organizational fraud.

[0006]

Means for Solving the Problem and Its Action / Effect The control device of the present invention reads a program stored in a program storage element in a predetermined procedure, and controls the operation of the equipment according to the program. A control device for determining whether or not the program storage element is a genuine product during operation of the control computer , wherein the program storage element is the control computer.
Installed outside the computer and inside the control computer.
The parts, a first CPU for performing arithmetic and logic operations, the CP
A bus unoccupied state detecting means for detecting a bus unoccupied state in which U does not occupy the bus for exchanging data with the program storage element, and the bus is used when the bus unoccupied state is detected. Reading means for reading the contents stored in the program storage element, and storage element judging means for judging whether or not the program storage element is a genuine product based on the contents read by the reading means, When the storage element determination unit determines that the program storage element is not a genuine product, the first CPU
The gist is to provide an operation prohibiting means for prohibiting the normal operation of.

[0007] The above control device of the present invention configured as described above, when the bus unoccupied condition detection means detects the unoccupied state of the bus by the first CPU, program storage using the bus by reading means The stored element is read from the element, and the storage element determination means determines whether or not the program storage element is a genuine product based on the read content.
When the storage element determining means determines that the program storage element is not a genuine product, the operation inhibiting means inhibits the normal operation of the first CPU .

In such a control device, the control computer is provided inside the control computer during operation of the control computer.
A second CPU is provided outside the control computer
Since it determines whether or not the program memory element is a genuine product, it is possible to effectively prevent artificial and systematic fraud such as illegal rewriting of the control program and illegal replacement of the program memory element. High reliability can be obtained. Moreover, when the control computer does not occupy the bus, the bus is used to determine whether the program storage element is a genuine product. Therefore, the control computer can read or read from the program storage element. It is possible to make it difficult to determine whether to read by the means.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION In order to further clarify the configuration and operation of the present invention described above, preferred embodiments of the control device of the present invention will be described below. FIG. 1 is a schematic configuration diagram showing a main part of a control system of a pachinko machine equipped with a pachinko machine controller as an embodiment of the present invention.

As shown, a pachinko machine controller 1
Is a one-chip microcomputer 2, a ROM 30 that is a program storage element, an oscillation crystal 18 externally attached to the one-chip microcomputer 2, a power supply circuit 28 that supplies a stabilized power supply to the entire circuit,
It is composed of a driver 40 and a waveform shaping circuit 50, and the one-chip microcomputer 2 and the ROM 30 are connected by a control bus CB, an address bus AB and a data bus DB. The one-chip microcomputer 2 is a CPU 10 that controls a pachinko machine.
And the CPU 2 that checks whether the ROM 30 is a genuine product
It is composed of a logic circuit centered on 0 and.

The CPU 10 is an "Z80" type 8-bit microcomputer, and uses signals MREQ \, RD \, M1.
A control bus control circuit 10a having a control port such as \, an address bus control circuit 10b having an address port, and a data bus control circuit 10c having a data port are provided. Here, "\" added after the signal name means that the port is low active.

The control port and address port of the CPU 10 are connected to the control bus CB and address bus AB via the bus driver 16,
The data port is connected to the data bus DB. The various buses CB, AB, and DB are connected to a RAM 12 that temporarily stores necessary data and an input / output interface circuit (hereinafter, referred to as I / O) 14. Also, CP
The control port of U10 is connected to the control signal control circuit 21.

The control signal control circuit 21 is a CPU
Signal G based on the signal RFSH \ output from 10
1, a signal G2, a signal CL1, a signal MREQ2 \ and a signal RD2 \. The control signal control circuit 21 includes the CPU 20 and the bus driver 1 via the control sub bus SB.
6, is connected to the bus driver 23 and the latch circuit 25, and controls the output states of the bus driver 16 and the bus driver 23 by the output of the signals G1 and G2,
The output of the signal CL1 controls the latch timing of the latch circuit 25 and informs the CPU 20 where the control bus CB or the like is used. The control signal control circuit 21 is connected to the control bus CB via the control sub-bus SB and the bus driver 23, and controls the signal MREQ2 \ and the signal RD2 \ created based on the signal RFSH \ and the like. Each logic circuit is controlled by outputting to the CB as the signal MREQ \ and the signal RD \.

Of the control signals, the signal G1 is output as a signal showing the same output as the signal RFSH \. Further, the signal G2 becomes a high level (hereinafter referred to as “H”) with a slight delay from the time when the signal RFSH \ becomes a low level (hereinafter referred to as “L”), and the signal RFSH.
It is output as a signal which becomes "L" slightly earlier than when "\" becomes "H". The signal CL1 is output as an inverted pulse signal in the latter half of the refresh time of the CPU 10. The signal MREQ2 \ and the signal RD2 \ are the signals G
It is output as a signal which becomes "L" when 2 becomes "H" and becomes "H" when the signal G2 becomes "L".

The bus driver 16 is composed of a tri-state buffer and outputs the signal G1 output from the control signal control circuit 21 to the control sub-bus S.
By inputting through B, the output from the control port and the address port is made effective or in a high impedance state. That is, when the signal G1 is “H”, the output from each port is validated and the CPU 10 causes the R
Various control signals are issued to the OM 30, the RAM 12 and the I / O 14 via the control bus CB, and the address bus A
It can be addressed via B. On the contrary, when the signal G1 is "L", the high impedance state is set, and the CPU 10 and the buses CB and AB are not connected.

The RAM 12 is a storage element in which necessary data is temporarily stored when the CPU 10 executes the control program stored in the ROM 30. RAM12
For temporary storage of data into the CPU, the CPU 10 outputs an address to store data to the address bus AB via the bus driver 16, sets the signal MREQ \ to "L", and outputs data to store from the data bus DB. Then, when the signal WR \ indicating that the data to be stored is output to the data bus DB is set to “L”, the RAM 12 becomes the data bus DB.
This is done by fetching data from. Also, C
When the PU 10 needs the data stored in the RAM 12, it outputs the address storing the data to be read via the bus driver 16 from the address bus AB, sets the signal MREQ \ to "L", and outputs the signal RD \. "L"
By doing so, the data output to the data bus DB is read from the specified address of the RAM 12.

The I / O 14 is a circuit for matching signals between the pachinko machine control device 1 and various electric equipments provided in the pachinko machine. Therefore, the I / O 14 is the bus C
B, AB, DB is connected to the electrical circuit equipment that is incorporated in the logic circuit centering on the CPU 10 and is equipped in the pachinko machine, for example, the waveform shaping circuit 50 connected to the main body winning switch 52, the digital start switch 51, and the like,
The hit lamp 43 of the main body of the pachinko machine, the display device 42 which is a set of LEDs in the digital part of the center character, and the driver 40 connected to the solenoid 41 for opening the special winning opening.
Etc. are connected to.

In addition to the above-described configuration centering on the CPU 10, a logic circuit for determining whether the ROM 30 is a genuine product is provided centering on the CPU 20. CPU20
Has a ROM 20d and a RAM 20e therein, and a check program described later has its internal RO
It is non-volatilely printed on M20d. Also, CP
U20 includes a data input circuit 20c having input ports Q0 to Q7, a data output circuit 20f having output ports P0 to P15, a control signal input port P17 of the CPU 20 and a control signal output port P18 \. There is.

The data output circuit 20f of the CPU 20 is connected to the address bus AB via the bus driver 23, and sets predetermined address data to the output ports P0 to P15 according to the program stored in the internal ROM 20d. Output the data. Data output circuit 2
The bus driver 23 interposed between 0f and the address bus AB is composed of a tri-state buffer like the bus driver 16, and outputs the signal G2 output from the control signal control circuit 21 to the control sub-bus S.
By inputting through B, the output from the output ports P0 to P15 to the address bus AB is made effective or in a high impedance state. That is, when the signal G2 is "H", the output from the output ports P0 to P15 to the address bus AB is enabled, and when the signal G2 is "L", the output ports P0 to P15 and the address bus AB are in a high impedance state. And are not connected.

Therefore, the control signal control circuit 2
By adjusting the signal G1 and the signal G2 output from 1, the data from the address bus control circuit 10b of the CPU 10 and the data from the output ports P0 to P15 of the CPU 20 are selectively output to the address bus AB. It That is, the output of the bus driver 23 is set to a high impedance state by setting the signal G2 to "L", and the control bus control circuit 10a and the address bus control of the CPU 10 via the bus driver 16 are set by setting the signal G1 to "H". Circuit 10b and control bus CB
And the connection with the address bus AB is enabled. vice versa,
By setting the signal G1 to "L", the output of the bus driver 16 is set to a high impedance state, and the signal G2 is set to "H".
And the CPU 20 via the bus driver 23
The connection between the output ports P0 to P15 and the address bus AB is enabled.

The input ports Q0 to Q7 of the CPU 20 have
The data bus DB is connected via the latch circuit 25. The latch circuit 25 inputs and holds the data output to the data bus DB when the control signal is input to the CLK terminal. CL of the latch circuit 25
The K terminal is connected to the control signal control circuit 21 via the control sub-bus SB, and is output to the data bus DB when the signal CL1 output from the control signal control circuit 21 changes from "L" to "H". Latched data, and then the signal CL1 changes from "L" to "H".
Hold that data until.

The output port P18 \ of the CPU 20 is connected to the OR circuit 2 together with a signal line from the outside of the pachinko machine controller 1.
It is connected to the port RESET \ of the CPU 10 via 6, and the CPU 20 can bring the CPU 10 into the reset state by setting the signal P18 \ to "L".

On the other hand, the ROM 30 is a storage element for storing a control program executed by the CPU 10 and various data necessary for executing the program in a nonvolatile manner.
When an address designation from 0 is received, the data stored at that address is output. That is, the ROM 30 stores information such as a control program based on the game rules to be executed by the pachinko machine controller 1.

Next, the operation of the pachinko machine controller 1 during the instruction fetch cycle of the CPU 10 will be described with reference to FIG. FIG. 2 is an explanatory diagram showing the instruction fetch cycle of the CPU 10 and the operation timing of the CPU 20 and the like. As shown in FIG. 2, the CPU 1 of the "Z80" system
0 is the first cycle (Machine cycle on) of the instruction fetch cycle in synchronization with the clock Φ.
The signal M1 \ is set to "L" to indicate that it is e), and a signal MREQ \ for indicating that the request is an access to the storage element and a read request for indicating that the request is an access request to the storage element after a slight delay. Signal RD \ and "L". Also, even if the access time of the storage element is slow, the storage element does not output "H" at the time of the falling edge of the signal WAIT \ in the T2 state of the clock Φ so that the data reading is not hindered. In this case, a waiting cycle is provided to delay the data read timing.

Therefore, the actual instruction fetch by the CPU 10 is executed when a certain condition judged by each of the above signals is satisfied, and is stored in the address AD1 designated by the address bus AB at that time, and the data is fetched. The data D1 output to the bus DB is fetched as an instruction. As is well known, the instruction thus fetched is stored in the instruction register in the CPU 10, and the operation of the CPU 10 in the next execution cycle is determined.

In the T3 and T4 states of the instruction fetch cycle of the CPU 10, the signal RFSH \ is set to "L" to refresh the dynamic RAM. In the "Z80" CPU 10, when the signal RFSH \ becomes "L", a refresh signal is output to the lower 8 bits of the address ports A0 to A15.

On the other hand, in the CPU 20, the internal ROM 20d
According to the program stored in, the predetermined address data AD2 is set to the output ports P0 to P15 and output.

When the signal RFSH \ of the CPU 10 becomes "L", the control signal control circuit 2 is based on this signal.
1 sets the signal G1 to "L", and further, the signal G2 is set to "H" with a slight delay. The bus driver 16 brings its output into a high-impedance state when the signal G1 becomes “L”, and the bus driver 23 outputs the signal G2 becomes “H”, whereby the output ports P0 to P of the CPU 20.
The connection between 15 and the address bus AB and the connection between the control sub-bus SB and the control bus CB are enabled. Therefore, the refresh signal from the address port of the CPU 10 is not output to the address bus AB.

A signal MREQ2 \ and a signal RD2 \ are output from the control signal control circuit 21 to the control bus CB as a signal MREQ \ and a signal RD \ via the control sub-bus SB and the bus driver 23, and the address bus AB is output. The address data AD2 which is set in the output ports P0 to P15 by the CPU 20 in advance is output to. By this output, ROM30
Is the data D2 stored at the specified address AD2
Is output to the data bus DB. This data D2 is latched by the latch circuit 25 by inputting the inverted pulse signal CL1 to the CLK terminal of the latch circuit 25, and is output to the input ports Q0 to Q7 of the CPU 20. After that, the CPU 20 adjusts the timing based on the signal G2 input to the input port P17, and then takes in the data D2 from the input ports Q0 to Q7.

Among the above operations, the output ports P0 to P1
5, the address data AD2 is output to the address bus AB, and the operation of latching the data D2 output from the ROM 30 by the latch circuit 25 according to the output of the data AD2 is performed within one refresh time of the CPU 10. Be done. As described above, since the data D2 is read using the various buses CB, AB, and DB during the refresh time of the CPU 10, the operation of the CPU 10 is not hindered. Further, in the present embodiment, the pachinko machine control device 1 does not have a dynamic RAM, and therefore is not limited by the fact that the refresh signal is not output to the address bus AB.

In this embodiment, the CPU 20 reads the data from the ROM 30 each time the CPU 10 is refreshed. However, the data output circuit 20f includes the ROM 3 therein.
When the address to be read is set to 0 and the data is ready to be read, the CPU 20 outputs a control signal to the control signal control circuit 21, and the control signal control circuit 21 operates only when the control signal is output. Then, when the CPU 10 is refreshed thereafter, the ROM 3
It is also preferable that the data of 0 is read. In this case, the port P17 of the CPU 20 is used as a control signal input / output port, and the CPU 20 outputs a control signal from the port P17 to the control signal control circuit 21.

The pachinko machine control device 1 configured as described above operates as follows. When the power supply circuit of the pachinko machine control device 1 is turned on, the CPU 10 of the one-chip microcomputer 2 is supplied with electric power, and the control program stored in the ROM 30 is sequentially read according to a predetermined procedure and is described in the program. Execute an instruction. By the processing of the CPU 10 based on this control program, the pachinko machine shows the behavior according to the game rule described in the control program, and the game described in the control program becomes possible.

As described above, when the pachinko machine is controlled by the processing of the CPU 10, the CPU 20 is executing the check program shown in the flowchart of FIG.
The check program shown in FIG. 3 is an internal R of the CPU 20.
CPU that is a program burned in OM20d
Immediately after the power supply to 20 is started, the processing based on this check program is started, and is repeatedly executed while the power is supplied. First, the CPU 20
The identification code stored in advance at a predetermined address of the ROM 30 is read (step S100). Next, it is judged whether or not this identification code is a predetermined correct value (step S110), and if it is correct, this routine is ended. If it is determined that the identification code is incorrect, the signal P18 \ from the output port P18 \ is set to "L" (step S120), and the CPU 10 is reset.

Here, whether or not the ROM 30 is a proper one is judged by a method of writing a value having a correlation with the program code written in the ROM 30 in the internal ROM 20d and discriminating the value, and the ROM 30 of the ROM 30. The predetermined calculation result for the data stored in the plurality of addresses is described in advance in the specific address of the ROM 30, and the CPU 20
A method of reading the data of each address of the ROM 30 and performing a predetermined calculation, and comparing the result with the value of the specific address to determine the internal ROM 20d and the ROM 30 of the CPU 20.
And a predetermined identification code is written in both
Internal ROM 20: a method for determining whether the identification codes match
The same program code described in the ROM 30 is previously recorded in d, and the contents of the ROM 30 and the internal ROM are stored.
20d, a method of comparing and determining the contents, a method of calculating the checksum of the program code written in the ROM 30 and determining whether or not this is a value previously written in the internal ROM 20d, a value of a plurality of addresses in the ROM 30 Various methods can be used, such as a method of reading and performing a predetermined calculation, and comparing the calculated result with a value described in advance at a predetermined address of the ROM 30 or a predetermined address of the internal ROM 20d to make a determination.

In the present embodiment, the CPU 10 is reset when it is determined that the identification code is incorrect. However, any means for prohibiting the normal operation of the CPU 10 may be used. It may be configured to stop its own operation. Further, since it is sufficient to stop the normal operation, various measures such as executing a demo can be considered.

In the pachinko machine control device 1 of the present embodiment configured as described above, the check program executed by the CPU 20 immediately after the power is turned on repeatedly determines whether or not the ROM 30 is a genuine product, and determines that the product is an unauthorized product. When the determination is made, the CPU 10 is reset and the operation is prohibited, so that the processing based on the illegal control program written in the illegal ROM is not performed at all. Moreover, CPU2
Since the operation of accessing the 0 bus CB or the like is performed only when the CPU 10 is refreshed, which is a time that is not used to control the pachinko machine, there is no problem in controlling the pachinko machine by the CPU 10. Therefore, the control program of the pachinko machine control device 1 by the CPU 10 does not need to be changed from the conventional one. Further, since the main logic circuit excluding the ROM 30 of the pachinko machine control device 1 is a single chip, the ROM 30
It is essentially impossible from the outside to judge whether the read command for reading data is a command from the CPU 10 or a command from the CPU 20. Therefore, it is possible to prevent illegal actions such as reading invalid program data when a data read command is issued from the CPU 10 and reading normal program data when a data read command is issued from the CPU 20.

Also, the pachinko machine control device 1 of the present embodiment.
Does not require a special time for checking the ROM 30 after the power is turned on, as compared with the case where the pachinko machine is controlled after checking whether the ROM 30 is a genuine product immediately after the power is turned on. Further, since the ROM 30 is constantly checked during the operation, the regular ROM 30 operates from the power-on to a predetermined time, and after the predetermined time elapses, an illegal RO
Fraud such as switching to M can also be detected.

Next, a second embodiment of the present invention will be described. FIG. 4 is a schematic configuration diagram showing a main part of a control system of a pachinko machine equipped with a pachinko machine controller as a second embodiment. For the sake of convenience of explanation, the same reference numerals are given to those constituted by the same logic circuit as that of the first embodiment, and the explanation thereof will be omitted.

As shown in the figure, the pachinko machine control device 1 of the second embodiment has a one-chip microcomputer 2, a ROM 30 and an oscillation crystal externally attached to the one-chip microcomputer 2 as in the first embodiment. 18
A power supply circuit 28, a driver 40 and a waveform shaping circuit 50.

The CPU 60 has a ROM 60d and a RAM 60e built therein, and a check program to be described later is nonvolatilely burned in the internal ROM 60d. Also, the CPU 60 has a control bus control circuit 60a having a control port, an address bus control circuit 60b having an address port, a data bus control circuit 60c having a data port, output ports P61 \, P62 \, and an input port P63. \ And each INT \ port for inputting an interrupt signal.

The control port, address port and data port of the CPU 60 are a control bus CB and an address bus AB connected to the respective ports of the CPU 10.
And the data bus DB. Each port of the CPU 60 connected to the various buses CB, AB, and DB is normally in a high impedance state, and outputs "L" from the port P62 \, resulting in the port P63 \.
Each bus control circuit 60 only when "L" is input from
The connection by a, 60b, 60c is validated. CPU6
The output port P61 \ of 0 is connected to the CPU 10 via the OR circuit 26 together with the signal line from the outside of the pachinko machine controller 1.
Connected to port RESET \ of signal P61 \
Is set to “L” to reset the CPU 10. The output port P62 \ of the CPU 60 is the CPU 10
Connected to the input port BUSRQ \ of the
By requesting 2 \ to be "L", the bus occupancy right is requested to the CPU 10. When receiving the signal P62 \, the CPU 10 sets the connection with the buses CB, AB, and DB to the high impedance state. At this time, the CPU 10
Sets its output port BUSAK \ to "L". This output port BUSAK \ is the input port P of the CPU 60.
It is connected to the bus C of the CPU 10 by inputting the signal BUSAK \.
The occupancy states for B, AB, and DB are detected. CPU6
After 0 uses the bus, the signal P62 \ is set to "H" to re-enable the connection between the CPU 10 and the buses CB, AB, and DB.

The input port INT \ of the CPU 60 is connected to the interrupt signal generation circuit 62. The interrupt signal generation circuit 62 is a logic circuit that randomly generates an interrupt signal. When the signal generated by the interrupt signal generation circuit 62 is input to the input port INT \, the CPU 60 activates the interrupt process according to a predetermined sequence and executes the check program described later. The frequency of the interrupt signal is CPU
It is determined by the frequency with which the ROM 60 checks the ROM 30, the number of times the ROM 30 reads data necessary for checking by the check program, and the like. In the second embodiment,
It is set to be once every 55 times on average between 10 to 100 machine cycles of the CPU 10. In the second embodiment, the interrupt signal is randomly generated, but the interrupt signal may be generated at a constant cycle.

In the pachinko machine control device 1 of the second embodiment configured as described above, when the pachinko machine is controlled by the processing of the CPU 10, the CPU 60 executes the check program shown in the flowchart of FIG. There is.
The check program shown in FIG.
The program is burned in the OM 60d, and the processing based on this check program is started every time a signal from the interrupt signal generation circuit 62 is input to INT \, and is repeatedly executed while power is supplied. . First, C
When an interrupt signal INT \ is input to PU60, signal P62
\ Is set to "L" (step S200). Signal P62 \
Is set to “L”, the CPU 10 sets the connection with the buses CB, AB, and DB to the high impedance state after the end of the currently executed machine cycle, and suspends the control of the pachinko machine. As will be described later, the interruption of the control of the pachinko machine is only for a few machine cycles of the CPU 60, so that the game is apparently continued without any trouble.

Next, wait for the signal input to the input port P63 \ to become "L" (step S210), and then the CP
The connection between U60 and the buses CB, AB and DB is validated (step S220). The CPU 10 uses the buses CB and A
When the connection with B and DB becomes a high impedance state,
Since the signal BUSAK \ is set to "L", if the CPU 60 receives this signal and validates the connection with the buses CB, AB, DB, the CPU 10 and the CPU 60 simultaneously receive the bus CB,
The connection with AB and DB is never valid.

The buses CB and A for which the connection has become effective in this way
The identification code is read from a predetermined address of the ROM 30 using B and DB (step S230). When the identification code is read, the connection between the CPU 60 and the buses CB, AB, DB is set to a high impedance state (step S240),
The signal P62 \ is set to "H" (step S250). By setting the signal P62 \ to "H", the connection between the CPU 10 and the buses CB, AB, and DB is validated, and the control of the pachinko machine by the CPU 10 is restarted. Therefore, C
The interruption of the control of the pachinko machine by the PU 10 is the ROM 3
There is no effect on the pachinko machine user due to the interruption of the control, since it is only a time to access 0, which is very small.

Next, it is judged whether or not the identification code read from the ROM 30 is a predetermined correct value (step S260), and if it is correct, this routine is ended.
If it is determined that the identification code is incorrect, the signal P61 \ from the output port is set to "L" (step S270),
The CPU 10 is reset.

Here, regarding the method of determining whether the ROM 30 is authentic and the countermeasure when it is determined that the identification code is incorrect, various methods and various countermeasures are considered as described in the first embodiment. be able to. For example, ROM
Predetermined calculation results for the data stored in the plurality of addresses of 30 are described in advance in the specific addresses of the ROM 30, the CPU 20 reads the data of each address of the ROM 30 and performs the predetermined calculation, and the result is the value of the specific address. And a method of making a determination by comparing with.

In the pachinko machine control device 1 of the second embodiment configured as described above, it is repeatedly judged whether or not the ROM 30 is a genuine product by the check program executed by the CPU 60 immediately after the power is turned on, and the illegal product is determined. If it is determined that the CPU 10 is reset, the operation is prohibited, so that no processing based on the illegal control program written in the illegal ROM is performed. Also, the CPU 60
Since the timing for executing the check program is determined by the randomly generated interrupt signal, it is possible to prevent the CPU 60 from detecting the reading from the ROM 30 in advance. Therefore, it is possible to prevent illegal control by the ROM. Further, the CPU 60 is the CPU 10
Since the ROM 30 is checked using the buses CB, AB, and DB only for a time that does not hinder the control of the pachinko machine by, the game is not hindered. The other effects are similar to those of the first embodiment.

Although the configuration and operation of the pachinko machine control device 1 have been described as the embodiments of the control device of the present invention, the present invention is not limited to these embodiments.
For example, a configuration incorporated as a control device for other gaming equipment such as a throttle machine, a configuration using a chip for which a control computer and a logic circuit for determining a program storage element are different, a doorway of a building, an office doorway, a lock of a safe door, etc. Needless to say, the present invention can be implemented in various modes without departing from the scope of the present invention, such as a configuration incorporated in a crime prevention system such as a management system in which reliability of a control program is particularly important.

[Brief description of drawings]

FIG. 1 is a block diagram of a pachinko machine controller according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an instruction fetch cycle in the CPU 10 of the pachinko machine control device 1 and the timing of operations of the CPU 20 and the like.

FIG. 3 is a flowchart of a check program executed by a CPU 20.

FIG. 4 is a block diagram of a pachinko machine control device as a second embodiment.

FIG. 5 is a flowchart of a check program executed by a CPU 60.

[Explanation of symbols]

1. Pachinko machine controller 2 ... One-chip microcomputer 10 ... CPU 10a ... Control bus control circuit 10b ... Address bus control circuit 10c ... Data bus control circuit 12 ... RAM 14 ... I / O 16 ... Bus driver 18 ... Crystal for oscillation 20 ... CPU 20c ... Data input circuit 20d ... ROM 20e ... RAM 20f ... Data output circuit 21 ... Control signal control circuit 23 ... Bus driver 25 ... Latch circuit 26 ... OR circuit 28 ... Power supply circuit 30 ... ROM 40 ... driver 41 ... Solenoid 42 ... Display device 43 ... Lamp 50 ... Waveform shaping circuit 51 ... Digital start switch 52 ... Prize switch 60 ... CPU 60a ... Control bus control circuit 60b ... Address bus control circuit 60c ... Data bus control circuit 60d ... ROM 60e ... RAM 62 ... Interrupt signal generation circuit AB ... Address bus CB ... control bus DB ... Data bus SB: Control sub bus

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Claims (6)

(57) [Claims] 1. A control computer for reading a program stored in a program storage element according to a predetermined procedure and controlling the operation of a device according to the program,
A control device for determining whether or not the program storage element is a genuine product during operation of the control computer , wherein the program storage element is a control device of the control computer.
An externally provided control computer internally occupies a bus for exchanging data with a first CPU that performs arithmetic and logical operations and the first CPU. A bus unoccupied state detecting means for detecting an unoccupied bus unoccupied state; a reading means for reading the contents stored in the program storage element using the bus when the bus unoccupied state is detected; Based on the read content, a storage element determination unit that determines whether the program storage element is a genuine product, and when the program storage element is determined to be a non-genuine product by the storage element determination unit, A control device comprising: an operation prohibiting unit that prohibits a normal operation of the first CPU . 2. The control device according to claim 1, wherein the storage element determination means is different from the first CPU.
The second CPU is different from the program storage element in R
The above judgment is performed according to a program stored in advance in the OM.
A control device realized by the configuration. 3. The control device according to claim 2, wherein the operation prohibiting means is a genuine product of the program storing means.
If it is determined that the second CPU does not
A control device that outputs a reset signal to the CPU 1. Wherein said second CPU is the determination, the control unit of repetition is performed according to claim 2, wherein at predetermined intervals. Wherein said second CPU is the determination, the control device according to claim 2, wherein performing at random timing. Wherein said second CPU is, when performing the determination, the control device according to claim 2 wherein the stop over the first CPU to a plurality of machine cycles of said 1CPU.