JP2703716B2 - Microcomputer for controlling game machines - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for controlling a game machine represented by a pachinko game machine, an arrangement type pachinko game machine, a slot machine, or the like.

[0002]

2. Description of the Related Art Conventionally, a game machine control microcomputer program for controlling a game machine is developed after a development and manufacturing company develops the program and stores it in a read only memory (hereinafter referred to as ROM) of the microcomputer. Take a third-party test to determine if your program passes certain criteria. And the R which memorized the passing program which passed the examination of the third party organization
Only the microcomputer having the OM is mounted on the game machine and carried into the game room, and only the game machine that can perform a healthy game that passes a certain standard is installed in the game room.

[0003]

However, even if the only gaming machines that are shipped to the amusement arcade are those that can play sound games that pass a certain standard, the present invention relates to a gaming machine carried into the amusement arcade. In some cases, an unauthorized program other than a passing program was created, and the central processing unit could be operated by the unauthorized program.If such unauthorized modification was performed, a third-party organization performed a test. However, there is a disadvantage in that a gaming machine that operates in a manner that does not conform to a certain standard is available in an actual game arcade.

An object of the present invention is to provide a gaming machine control microcomputer capable of minimizing the control of a gaming machine by an illegally modified program other than a passing program.

[0005]

A microcomputer for controlling a gaming machine according to the present invention comprises a read-only memory (hereinafter referred to as a ROM) in which a control program for controlling the gaming machine is stored, and security information in a regular ROM. (Hereinafter referred to as security information storage means) for converting the control program stored in the ROM into security information, and the converted security information and the security information already stored in the security information storage means. A validity determining means for checking consistency with legitimate security information. Only when the determination result is appropriate, the gaming machine control microcomputer having a function of operating the gaming machine in accordance with the control program is used. Achieve the goal. According to a second aspect of the present invention, there is provided a read-only memory (hereinafter referred to as a ROM) in which a control program for controlling a gaming machine is stored.
Storage means for storing security information of the OM (hereinafter referred to as security information storage means); a control program stored in the ROM being converted into security information, and the converted security information and security information already stored in the security information storage means. Aptitude judging means for checking the consistency with the stored legitimate security information,
A gaming machine having a function of operating the gaming machine in accordance with the control program in the ROM when the determination result is proper and operating the gaming machine in accordance with the control program only for a predetermined time if the determination result is not appropriate; This is a microcomputer for machine control. According to a third aspect of the present invention, when it is determined that the compatibility between the control program stored in the ROM and the legitimate security information already stored in the security information storage means is not appropriate, This is a gaming machine control microcomputer configured to reset the microcomputer.

[0006]

According to the present invention, a ROM storing security information consisting of a control program and a security code for controlling a gaming machine is suitable for judging whether or not a format for converting the control program into security information is stored. It is mounted on a gaming machine control microcomputer including a (security check circuit). The suitability judging means of the gaming machine control microcomputer converts the control program stored in the ROM into security information when the switch of the gaming machine is turned on, and obtains the security information stored in advance in the security information storage means. The information is compared with the information or the presence or absence of the security information is confirmed, and it is determined whether or not the security information is appropriate. When the result of the determination is appropriate, a predetermined control operation for the gaming machine is performed according to the control program stored in the ROM. As a result, if the ROM is erroneously replaced with a ROM in which a different type of control program and security code have been written after the game machine has been mounted in the hall, it is determined to be inappropriate. When the determination result is determined to be inappropriate, the gaming machine operates only for a predetermined time or the system is reset, as described in claim 2 or 3.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

[0008]

FIG. 1 is an overall system block diagram showing a security system using a one-chip microcomputer for games according to the present invention.

A microcomputer chip according to the present invention is manufactured by a semiconductor chip maker 1. The semiconductor chip maker 1 is an MPU in a microcomputer.
(Micro Processing Unit), RAM (Random Access Memo)
ry), and a semiconductor chip in which input / output ports (I / O ports) are integrated into one chip is manufactured. This semiconductor chip maker 1
The chip manufactured by will be described in detail later,
There are a mass production chip 23a and a development chip 23b. The mass-production chip 23a is a judgment function for judging whether or not a program stored in a ROM connected to the mass-production chip 23a is an appropriate one that has passed a test by a third-party testing organization 11 described later. It has. The development chip 23b is a chip that does not have the above-described determination function, and is the same as the mass-production chip 23a except that it does not have the determination function.

[0010] Of the chips received from the semiconductor chip maker 1 to the chip distribution company 2, the mass production chips 23 a are distributed by the mass production chip distribution division 28 and carried into the chip distribution management organization 3. On the other hand, the development chip 23 b is distributed by the development chip distribution section 29 of the chip distribution company 2 and is carried into the chip distribution management organization 3. Note that the chip distribution company 2 may be a completely private company, or may be a public company formed by the government. The chip distribution management institution 3 is an organization for managing whether or not chips are properly distributed and mediating distribution of chips to a predetermined game machine maker or the like. The chip distribution management organization 3 may be omitted and chips may be directly carried in from the chip distribution company 2 to the game machine maker.

The mass production chip 23a and the development chip 23b carried into the chip distribution management organization 3 are carried into the mass production section 6 and the development section 5 of the gaming machine maker 4, respectively.
The development section 5 of the gaming machine maker 4 develops a program using the development chip 23b carried in as shown in FIG. Then, the development section 5 stores an application master ROM 10a in which the developed development program is stored.
In addition to creating a gaming machine for application with the application, and preparing documents for application, submit a submission 8 for application consisting of a gaming machine for application / creation document 9 with the application master ROM 10a and the like. Apply for a test to the Tripartite Testing Institute 11.

The third-party testing institution 11 is composed of, for example, a commissioned agency of a public supervisory institution such as the police. The third-party testing institution 11 includes a test service section 12 and an appraisal service section 13. The test submission 8 is carried into the test service section 12, and the test application is accepted as shown in FIG. The test service section 12 tests the received test submission 8 as shown in FIG. 15 and determines whether or not the test result is acceptable as shown in FIG. If it is determined to be unsuccessful, the test service section 12 sends back the application submission 8 to the gaming machine maker as shown in FIG.

On the other hand, the competent supervising organization 25 composed of polices in each prefecture also conducts an examination on the application gaming machine, and is judged to be passed by the third-party testing institution 11 and judged to be appropriate by the competent supervising organization 25. In this case, as shown in FIG. 18, a security code converted from the control program is issued according to a predetermined conversion format and stored in the mass production master ROM 10b. The third-party testing institution 11 and the jurisdiction supervisory institution 25 constitute a third-party institution that tests whether the development program stored in the read-only memory (ROM) passes a certain standard. ing. The security code is a program stored in a ROM mounted on a game machine that has been released to the market after being judged to be passed by a third-party organization and is an appropriate one that has passed the examination of the third-party organization. This is security information used to determine whether or not the information is valid.

As the security code, for example, a method in which program data of a passed program is converted according to a predetermined conversion format to be a security code can be considered. In this case, all of the program data may be used as a reference for creating a security code, or a particularly important portion of the program data (for example, a data portion such as a jackpot probability or an opening time of a variable winning ball device) may be used as a reference for creating a security code. It may be. This security code may be issued when the third-party testing organization determines that the test has passed without waiting for the test result of the competent supervisory authority 25.

The mass production master ROM 10b to which the security code has been added by the test service department 12 of the third party testing organization 11 is carried into the mass production department 6 of the gaming machine maker 4. The mass production section 6 copies the storage information stored in the mass production master ROM 10b as shown in FIG. The ROM on which the storage information of the mass production master ROM 10b is copied is mounted on the board 22. Further, the chips for mass production carried in from the chip distribution management organization 3 are shown in FIG.
As shown in FIG. The mounting chip 23 mounted on the board 22 and the mounting ROM 10c
A microcomputer for controlling the gaming machine is configured.

After the chip 23 and the ROM 10c are mounted on the board 22, the power is turned on for the first time.
The security code included in the storage information of M10c is stored in the mounting chip 23 as described later. The mounting chip 23 composed of the mass production chip 23a is mounted on the substrate 22.
And has a function of storing only the security code stored in the ROM 10c which is attached first and is connected first. Then, based on the stored security code, it is determined whether or not the program stored in the mounting ROM 10c is an appropriate program that has passed the test of the third party organization. Once the ROM is mounted, the program stored in the ROM is altered,
In the case where 0c is replaced with a ROM storing a program created illegally, the security code stored in the mounting chip 23 and the security code stored in the ROM are inconsistent with each other, and the consistency is lost. lose. Therefore, it is possible to determine that the program has been tampered with.

Instead of having the game machine maker 4 copy the program and security code to the ROM and mount it on the board, the master ROM 1 for mass production is used.
0b may be carried into the chip distribution company 2, the chip distribution company 2 may copy the ROM and mount the ROM on the board, and then carry the board into the gaming machine maker 4. The gaming machine maker 4 constitutes a development / manufacturing company which develops a program for operating a central processing unit of a microcomputer for controlling the gaming machine and stores the development program in a read-only memory of the microcomputer. ing. The development and manufacturing company is not limited to the game machine maker, but may be a program development and manufacture company subcontracted to the game machine maker.

As described above, the mass-production chip 23a
If the program stored in the connected ROM is modified to make it different from the first program, it is determined that the program has been illegally modified so that the microcomputer does not operate in a normal state. Has the function of Therefore, when the development is performed by the development section 5 using the mass production chip 23a,
Each time the program stored in the ROM is debugged or the like, the program is determined to be inappropriate each time the program is changed, and the microcomputer does not operate properly. However, as described above, the development chip 23b does not have the security check function.
Therefore, if the debugging or the like is performed using the development chip 23b, the microcomputer operates in a normal state, which is convenient for program development. The package of the mass production chip 23a is made of plastic, for example, and the package of the development chip 23b is made of ceramic, for example, so that the mass production chip 23a and the development chip 23b can be distinguished from the appearance of the chip.

The gaming machine 21 on which the board on which the chip and the ROM are mounted is mounted is carried into a game hall 24. In the amusement arcade 24, a plurality of carried-in gaming machines 21 are installed so that a player can play a game.

The jurisdiction supervising organization 25 performs a random inspection of the gaming machine 21 installed in the game arcade 24, and performs a collation process of the ROM of the gaming machine which seems to be malfunctioning as shown in FIG. Third-party testing institutes 1 whose ROMs have been verified but whose suitability is difficult to determine
A request for appraisal is made to the appraisal business unit 13 of the first section. For example,
If both the mounting chip 23 and the mounting ROM 10c are replaced with other illegally manufactured ones, the gaming machine will operate according to the remodeling program without performing the security check described above. In such a case, an appraisal request is made to the appraisal business unit 13.

In the appraisal business section 13, the board 2 on which the mounting chip 23 and the mounting ROM 10c requested for the appraisal are mounted is mounted.
Inspection and verification of the game machine are performed as shown in FIG. This gaming machine verification / collation 33 removes the ROM 10c mounted on the board 22 and mounts the mass production master ROM 10b storing an appropriate program in place of the ROM 10c to determine whether the mounting chip 23 operates normally. It is performed by verifying and collating. As a result, as shown in FIG. 28, an appraisal work / document is prepared, and the appraisal result is reported to the competent supervisory authority 25. Application master RO mentioned above
M10a, master ROM 10b for mass production, mounting ROM 10
c is formed of, for example, an EPROM.

FIG. 2 is a block diagram showing a mounting chip in a state where a chip for mass production is mounted on a substrate and various devices and circuits connected to the mounting chip.

The mounting chip 23 has a central processing unit (CP) capable of executing a control operation in a predetermined procedure.
U (Central Processing Unit) 40, RAM 41 capable of writing and calling required data, receiving input signals and providing input data to CPU 40
An I / O port 44 for receiving output data from 40 and outputting the data to the outside is formed as a single chip. A crystal oscillation signal from an externally provided crystal oscillator 45 is input to a clock generation circuit 46 provided on the mounting chip 23. The crystal oscillation signal from the crystal oscillator 45 has a frequency twice as high as the operation clock. In addition,
A vibration signal from a ceramic oscillator using ceramic as an oscillator instead of the crystal oscillator 45 may be input to the clock generation circuit 46.

The programmable clock dividing circuit 47 to which the clock signal from the clock generating circuit 46 is inputted,
The input clock signal is frequency-divided and a predetermined clock signal is output to the sound generator 48 and the variable display device display driving IC 49. The sound generator 48 outputs a control signal for generating sound to a speaker provided in the gaming machine.

The programmable interrupt request timer 0 (5
Reference numerals 0) and 1 (51) each comprise a 16-bit programmable counter timer, and include a free running counter and a compare register (two sets).
The programmable interrupt request timers 0 (50) and 1 (5
1) The main functions are interval timer function,
Event count function, one-shot output function, PW
Not only has an M (pulse width modulation) output function, but also a pulse width measurement function and a time difference measurement function.

The pulse width measurement function is a function for measuring the waveform length of a detection signal of a start winning switch or a 10-count detection switch provided in a gaming machine, for example. The time difference measurement function is a function of measuring the time from when there is a detection signal from the above-described various switches to when there is a next detection signal. The pulse width measurement function and the time difference measurement function correspond to programmable interrupt request timers 0 (50) and 1 (5).
This can be achieved when the clock source of the counter of 1) is selected as an external input.

As the clock source of the counter, a clock can be selected and used as a refresh counter, and the output from the other programmable interrupt request timer can be selected as a clock source and used as a 32-bit counter. Can also. As a method of selecting these clock sources, a method of selecting them inside a program is adopted. In other words, there is a register at a certain address, a predetermined number is written in this register, and a clock source is selected according to the type of the written number.

This programmable interrupt request timer 0 (5
For 0) and 1 (51), an interrupt can be set by a counter output and a compare output, and the interrupt can be set to be routed to any one of exception processing of a user reset, a maskable interrupt, and a non-maskable interrupt. Further, by the function of the prescaler, the clock unit time of the timer can be arbitrarily set, and the values of the compare registers (two sets) can be arbitrarily set. Output signals from the programmable interrupt request timers 0 (50) and 1 (51) are input to the reset / interrupt controller 52.

This reset / interrupt controller 52
Has a system reset function and a user reset function. The system reset refers to initializing the entire mounting chip 23 including the I / O port 44 and restarting from the power-on state. On the other hand, the user reset is to perform a warm restart of the mounted chip 23 by resetting only the CPU 40. This user reset is performed, for example, once every 2 msec to enable interrupt processing. The reset / interrupt controller 52 receives a system reset signal, a user reset signal for performing a warm restart, a non-maskable interrupt request signal, and a maskable interrupt request signal from an interrupt request signal generating circuit 54. A system reset output signal is output from the reset / interrupt controller 52 to the interrupt request signal generation circuit 54.

The system reset signal input to the reset / interrupt controller 52 has a low active level input. That is, it is reset when the input signal switches from the high level to the low level. Similarly, the user reset signal input to the reset / interrupt controller 52 is low active and level input. The interrupt request signal generating circuit 54 may not be provided.

The mounting chip 23 is provided with an address decode circuit 57 and a data output time adjustment circuit 58. The address decode circuit 57 has an external I / O 67
And the external ROM 10c are connected. A microcomputer is formed by the mounting chip 23 and the external ROM 10c. The address decode circuit 57 has an address decode (chip select signal generation) function for setting an external input / output map area and an external ROM area to a space on a memory (physical address).

The external input / output map area can be set to an external input / output map area size of 256 B to 2 KB, and a chip select signal (6
Book). The external ROM area generates a chip select signal for the external ROM 10c.

The data output time adjusting circuit 58 provides a wait function for extending a machine cycle in order to interface with a low-speed input / output device. By setting, a wait state for a maximum of four machine cycles is possible. The output signal from the address decode circuit 57 is also input to the I / O port 44, and the input / output port is specified by specifying the bit of the I / O port 44 according to the output address. I have.

The I / O port 44 has 8 bits (port A
And a 4-bit (for port B) peripheral device interface port (PIP). These port terminals serve as a chip select terminal for external input / output and a handshake terminal (for one port) in addition to a general-purpose input / output port function. As shown in FIG.
There are three modes, a, b, and c, and a selection command for selecting one of the three modes is given from the external ROM 10 c to the I / O port 44 via the CPU 40. When the mode c is selected, an 8-bit general-purpose input / output port for setting input / output in units of bits and 6b
It provides a chip select function for it. To have a handshake function, the mode a or b is selected. Then, 8b that I / O setting can be done in Byte unit
It provides a general purpose input / output port. However, two terminals (P8, P9) are set as handshake terminals for port A, and timing signals and read / write signals are input / output to / from these handshake terminals P8, P9. This handshake terminal can be set to interrupt. In addition, routing of the handshake terminal interrupt can be set for maskable interrupt exception processing. Mode a
Is selected, the terminals P10 to P13 become chip select signal ports, and when mode b is selected, the terminals P10 to P13 become PIPs for port B without the handshake function.

Various drive circuits 55 and various switch circuits 56 of the gaming machine are connected to the I / O port 44. Then, signals from the various switch circuits 56 are given to the CPU 40 via the I / O port 44, and control signals from the CPU 40 are given to the various drive circuits 55 via the I / O port 44.

The watchdog timer 60 provided in the mounting chip 23 provides a function of detecting a malfunction (runaway) due to a cause such as noise or a drop in power supply voltage, and returning to a normal state. The signal from watchdog timer 60 is applied to system check circuit 61 and reset / interrupt controller 52. The watchdog timer 60 is configured to output a watchdog timer signal when the reset timing of the timer is equal to or longer than the maximum allowable reset interval time. The maximum allowable reset interval time can be set by the gaming machine maker 4 to a desired time. Furthermore, this watchdog timer 60 has an 8-bit
The clock unit time of the timer can be set by the function of the prescaler. The output of the watchdog timer signal can be set to be routed to any one of the exception processing of user reset, maskable interrupt, and non-maskable interrupt. The system check circuit 61 may not be provided.

An address bus terminal (16 terminals) and a data bus terminal (8 terminals) are connected to the external bus interface 43 provided on the mounting chip 23, and an address bus signal and a data bus signal are respectively output. You.
From the external bus interface 43, a signal indicating that the data bus is in a read cycle, a signal indicating that the data bus is in a write cycle, a signal indicating that access to the memory space is being performed, and an operation code fetch cycle is being executed. A signal indicating the presence is output. These output signals are output to the one-chip microcomputer ICE adapter board 59 (see FIG. 5) during program development. All the input / output terminals of the mounting chip 23 except the output terminal from the security check circuit 62 to the monitor device 60 are connected to the one-chip microcomputer ICE adapter board 59. The address bus signal from the address terminal and the data bus signal from the data bus terminal are also output to the external I / O port 67 and the external ROM 10c, respectively.

In the figure, reference numeral 69 denotes a large-capacity capacitor;
This is for backing up the power supply of AM41.
In some cases, the capacitor 69 is not provided. This R
The AM 41 is configured to be able to perform bank switching by a bank switching signal from the security check circuit 62. This will be described with reference to FIG.

FIG. 3 is an explanatory diagram showing a memory map. As shown in FIG. 3, addresses 0000 to 7FFF
Are the addresses allocated to the external ROM 10c,
8000 to 81FF are addresses allocated to the RAM 41, and F000 to F7FF are external I / O.
Address assigned to 67, from FF00 to FFF
Addresses up to F are addresses allocated to the internal I / O 44.
Then, the RAM 41 stores the address from 8000 to 81FF.
Up to 256 / 512B (capacitor 6
9 is possible) and 256B. However, the capacity of the RAM 41 is 256B
At the time, the address is from 8000 to 80FF. Then, in the case of a general user mode described later, 25
A working area of 6 / 512B is used, and in the case of a user test mode described later, bank switching is performed and a working area of 256B is used. Of the 256 / 512B, 256 is for a pachinko game machine and 512 is for a slot machine.

The external ROM 10c is assigned addresses 70000 through FFFF as described above.
An appropriate program is created to fit within this address. If a program is created to execute an instruction outside this address, it is determined that this program has been tampered with. In such a case,
The CPU 40 is configured to stop automatically and not execute an instruction.

The RAM 41 is backed up by a capacitor 69. However, if the power supply is momentarily interrupted for any reason, the CPU operation becomes unstable, and R
An abnormal access to the AM 41 may destroy data in the RAM 41. Therefore, the RAM 41 is provided with an access control function for prohibiting access to the RAM 41 in response to the output from the backup power supply at the moment of a power interruption.

That is, the RAM 41 is provided with an access control register, which controls whether or not access to the RAM 41 is possible according to the value of a predetermined bit. The rewriting of this bit is performed while the operation of the CPU 40 is still stable in response to a non-maskable interrupt generated by the backup power supply at the moment of a power interruption. When this bit is a value indicating that access is not allowed, neither data reading nor writing from the RAM 41 can be performed, so that an abnormal operation of the gaming machine can be prevented.

The security check circuit 62 provided on the mounting chip 23 includes a CPU 63, a ROM 64, an R
It has an AM 65, and the ROM 64 stores a program shown in FIG.

The program will be described with reference to FIG. The power is turned on, the system is reset, and in step S (hereinafter simply referred to as S) 1, the external ROM 1
Security code written in 0c and external RO
A process of checking the consistency with the program data of M10c is performed. The security code written in the external ROM 10c is, as described with reference to FIG.
The security code is a security code given to a development program that is deemed to be passed by the third party testing organization or the competent supervisory authority 25, for example, a code obtained by converting program data in the external ROM 10c according to a certain conversion format. The conversion format is already stored in the ROM 64 of the security check circuit 62, and the internal CPU 63, which is a determination unit, checks the consistency between the security code written in the external ROM 10c and the program data according to the stored conversion format. Check. Note that instead of writing the conversion format in the ROM 64 of the security check circuit 62 in advance, an R
The conversion format may be written in the OM 10b. In that case, a security check circuit 6 is provided based on the conversion format and the security code.
2 checks the consistency between the security code written in the ROM and the program data. Next, the process proceeds to S2, where it is determined whether the result of the check is proper. If the result is proper, the process proceeds to S3, and whether the security code is written in the security check circuit 62 is performed. It is. When the power is turned on for the first time after the ROM 10c is mounted on the same substrate as the substrate 22 on which the mounting chip 23 is mounted, the process proceeds to S6 because the security code has not yet been written in the security check circuit. In S6, after the process of writing the security code in the security check circuit 62 is performed, the process proceeds to S7. In this case, the program data in the ROM may be directly written as security information into the security check circuit (security information storage means). In S7, a process is performed in which the CPU 40 is activated without a time limit to enter a general user mode in which normal gaming machine control is performed. Also in this case, if there is a system runaway or the like, the system is reset and the processes after S1 are performed again. In this embodiment, the security code is written in the security check circuit 62 when the power is turned on for the first time after the ROM 10c is mounted on the same substrate as the substrate 22 on which the mounting chip 23 is mounted. The manufacturer 4 sends the master ROM 10 for mass production from the third party
Alternatively, a mass-production master chip in which the security code corresponding to b is written may be received, copied to the mass-production chip 23a, and mounted on the board 22. Also,
The security code may be written in the mounting chip 23 (mass production chip 23a) by a dedicated security code writing device.

On the other hand, if the security code has already been written in the security check circuit, a determination of YES is made in S3 and the control proceeds to S4 where the ROM 10
The security code of c is checked for consistency with the security code already written in the security check circuit. Next, the control proceeds to S5, where it is determined whether or not the result of the check is appropriate. If the result is appropriate, the control proceeds to S7. For a certain time (for example, 60
(Seconds), the process shifts to the user test mode. Then, if a certain time has elapsed or if there is a system runaway or the like, the system is reset again, and the processing after S1 is performed. This S1, S
2 and S4, S5 constitute an adequacy determining means for determining whether or not the control program stored in the read-only memory is an appropriate one that has passed the test by the third party. On the other hand, if it is determined that the result of the check in S2 and S5 is appropriate, the ROM 41 uses the working area of 256 / 512B as described above, while the result of the check in S2 and S5 If the security check circuit 62 determines that the data is improper, the security check circuit 62 sends the data to the RAM 41 as shown in FIG.
The bank switching signal is output as shown by
Is switched to the working area of 256B. When the CPU is activated only within the time limit (for example, 60 seconds) by S8, the operation of the microcomputer within the time limit is limited to 25 times in the RAM 41.
6B will be performed in the working area.

One of the reasons for activating the CPU 40 only for a predetermined time (for example, 60 seconds) even if the result of this check is inappropriate is, for example, a game machine 24 shown in FIG. Before shipment to the board, the board may be checked or the control of the variable display device or the like provided on the game board may be checked again. In such a case, the mounting ROM 10c already mounted on the board 22 is pulled out once and other checks are performed. The purpose of this is to insert a ROM in which a program for use is stored and perform a check. Even if a ROM in which a program different from the passing program is stored is mounted, the microcomputer operates for a predetermined time (for example, 60 seconds). This is so that the above-described check can be performed. Another reason is that a program development company for controlling a gaming machine creates a program, passes the test of the third-party testing institution 11 and passes the test, and then stores the ROM 10c storing the passed program and the chip 23 on the substrate 22. This is because a board check may be performed before mounting and shipping to the gaming machine maker 4. In this case, the board check is performed by replacing the test ROM with a test ROM in which a test program in which the control time is shortened, for example, by shortening the opening period of the variable prize ball device at the time of a big hit, is used instead of the pass ROM. Short time limit (for example, 60 seconds) after mounting on the substrate 22
I / O tests can be performed quickly within the system. In the case of such a user test mode, the reason for switching the working area of the RAM 41 to 256B is that if the working areas of the general user mode and the user test mode are made the same, a program for program modification is stored. The illegally inserted ROM is inserted into the board 22, and the microcomputer is operated according to the program for the program modification for a limited time (for example, 60 seconds), and
An external ROM in which various constants and the like stored through the AM 41 are rewritten and a pass program is stored later.
Even if 10c is mounted on the board 22, the microcomputer may operate improperly because the constants and the like have already been rewritten, and in the case of the user test mode in order to prevent such inconvenience, This is for operating in a working area different from the general user mode.

Further, S1 to S5 or S1 shown in FIG.
The time required for the security checks in steps S3 and S6 is set to, for example, about 3 to 5 seconds. 3 ~
The reason why the configuration is made to be a relatively long time of about 5 seconds is that when a ROM storing an illegally modified program other than a passing program is mounted on the board 22, the above-mentioned 3 to 3 is applied every time the time limit elapses. Perform a security check for about 5 seconds to make the CPU inoperable during that time,
This is because the CPU is stopped for a long period of about 3 to 5 seconds and the gaming machine is intentionally not operated normally, so that an illegally remodeled program may interfere with the game.

In S8, the time limit (for example, 6
(0 seconds), the CPU may not be activated until the power is turned on next time. After repeating the process of resetting the system after the time limit elapses a predetermined number of times, the CPU 40 is stopped so that the operation in the user test mode is not performed again even if the power is turned on again depending on the inappropriate ROM. You may comprise.

The security check processing time of about 3 to 5 seconds and the time limit (for example, 60 seconds) become shorter when the oscillation frequency of the crystal oscillator 45 becomes higher, and become longer when the oscillation frequency becomes lower. . When the monitor device 60 is connected to the security check circuit 62 as shown in FIG. 2, it is possible to determine whether the current mode of the chip is the general user mode or the user test mode. In the figure, 66 and 68 are data buses.

The development chip 23b is all the same as the mass production chip 23a except that the security check circuit 62 shown in FIG. 2 does not exist. In addition,
The security check circuit 62 is also provided for the development chip 23b.
May be provided so that a program for performing a security check is not stored in the ROM 64.

The mass production chip 23a and the development chip 2
3b is a so-called ASIC (application specific inte
grated circuit), a dedicated chip for pachinko and slot machines. Further, a chip for limiting the gaming machine maker 4 may be used. In the above-described embodiment, various functions are integrated into one chip. However, each of these functions may be configured by a single component.

FIG. 6 is a block diagram showing a part of a microcomputer development system when a program is developed using a development chip in a development section of a gaming machine maker.

In the figure, reference numeral 80 denotes an ICE for CPU, which is a commercially available product. ICE (in-circuit emulator) means MDS (micr
It emulates the hardware of a microcomputer system under the ocomputer development system). The CPU ICE 80 is an ICE for a gaming machine control microcomputer before being made into a single chip, and develops a microcomputer program by effectively utilizing this commercially available conventional CPU ICE 80. For this purpose, the one-chip microcomputer ICE adapter board 59 is required. The one-chip microcomputer ICE adapter board 59 is sold by the chip distribution company 2 shown in FIG. CPU probe 8 of ICE80 for CPU
1 and the CPU socket 84 of the one-chip microcomputer ICE adapter board 59, and further the one-chip microcomputer probe board 82 of the one-chip microcomputer ICE adapter board 59.
A microcomputer program can be developed with the one-chip microcomputer socket 84 of the product development board 83 connected. Reference numeral 10 denotes a ROM connected to the development chip 23b.

[0054]

As described above, the present invention relates to a one-chip microcomputer for controlling a gaming machine carried into a game arcade, in which an unauthorized remodeling operation using a read-only memory storing an unauthorized program other than a passing program is performed. In this case, since the game is not executed because the suitability judging means judges that the game is not appropriate, the control of the gaming machine by the unauthorized program can be easily prevented.

[Brief description of the drawings]

FIG. 1 is a system block diagram schematically showing a security system using a gaming machine control microcomputer according to the present invention.

FIG. 2 is a block diagram showing a mounting chip constituting a gaming machine control microcomputer according to the present invention and circuits of peripheral devices connected thereto.

FIG. 3 is an explanatory diagram showing a memory map of the gaming machine control microcomputer according to the present invention.

FIG. 4 is an explanatory diagram for explaining a function corresponding to an I / O port mode.

FIG. 5 is a flowchart showing a program stored in a ROM provided in a security check circuit of the gaming machine control microcomputer.

FIG. 6 is a block diagram showing a part of a development system of the gaming machine control microcomputer.

[Explanation of symbols]

 21 Pachinko game machine as an example of a game machine 23 Mounting chip 10c Mounting ROM 4 Game machine maker as an example of a development / manufacturing company 11 Third-party testing organization 25 Competent supervisory organization 24 Amusement arcade

Claims (4)

(57) [Claims] 1. A control program for controlling a game machine.
Read-only memory (hereinafter referred to as ROM)
To store security information in the regular ROM.
Storage means (hereinafter referred to as security information storage means)
Security program stored in the ROM
Security information converted to security information.
And the correct information already stored in the security information storage means.
To check compliance with security information
A microcomputer for controlling a gaming machine, comprising a function of operating the gaming machine in accordance with the control program only when the determination result is proper. 2. A control program for controlling a gaming machine.
Read-only memory (hereinafter referred to as ROM)
To store security information in the regular ROM.
Storage means (hereinafter referred to as security information storage means)
Security program stored in the ROM
Security information converted to security information.
And the correct information already stored in the security information storage means.
To check compliance with security information
Means for operating the gaming machine according to the control program of the ROM when the determination result is appropriate,
A gaming machine control microcomputer having a function of operating the gaming machine in accordance with the control program only for a predetermined time when the determination result is not appropriate. 3. A control program stored in a ROM.
Already stored in the security information storage means
If the result of judging the suitability of the
If it is not correct, the microcomputer
Note that the system is configured to be reset.
2. A micro computer for controlling a gaming machine according to claim 1.
Data. 4. In a user test mode, a user
Operating in a different working area than the user mode
The method according to any one of claims 1 to 3, wherein
A microcomputer for controlling game machines.