JP3263101B2 - Microcomputer for controlling game machines - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for controlling a game machine represented by a pachinko game machine, an arrangement type pachinko game machine, a slot machine, or the like.

[0002]

2. Description of the Related Art Conventionally, a program for a microcomputer for controlling a gaming machine for controlling a gaming machine is developed by a development / manufacturing company and stored in a read-only memory (ROM) of the microcomputer. Take a third-party test to determine if you pass certain criteria. Only a microcomputer having a read-only memory in which a passing program that has passed the examination of a third-party organization is stored in the gaming machine and loaded into the game arcade, where a sound game that passes a certain standard is passed. Only gaming machines that can perform the game will be installed.

[0003]

However, even if the only gaming machines that are shipped to the amusement arcade are those that can play sound games that pass a certain standard, the present invention relates to a gaming machine carried into the amusement arcade. In some cases, an unauthorized program other than a passing program was created, and the central processing unit could be operated by the unauthorized program.If such unauthorized modification was performed, a third-party organization performed a test. However, there is a disadvantage in that a gaming machine that operates in a manner that does not conform to a certain standard is available in an actual game arcade.

An object of the present invention is to provide a gaming machine control microcomputer capable of minimizing the control of a gaming machine by an illegally modified program other than a passing program.

[0005]

A microcomputer for controlling a gaming machine according to the present invention stores predetermined program data for a game control operation and a predetermined security code converted according to a predetermined format based on the data. External storage means (10
c) and a microcomputer having a built-in security check circuit having storage means for storing a predetermined security code stored in the external storage means (10c) and storage means for storing a predetermined conversion format program. , The connected external storage means (10
c) the security code and storage means (10
If the security code is converted according to a predetermined conversion format based on the program data stored in c), it is checked whether or not the security code has already been written in the storage means of the security check circuit, and the write is performed. If not, the CPU is activated after writing, and if a security code is written in the storage means of the security check circuit, it is determined whether or not both security codes match. The configuration is such that the CPU is activated in such a case.

[0006]

According to the present invention, when the external storage means storing information for controlling the gaming machine is first connected to the gaming machine control microcomputer, the security code stored in the external storage means is stored. Are stored in the storage means of the security check circuit. This security check information is retained as it is thereafter. The suitability determination means of the gaming machine control microcomputer, when a predetermined determination condition is satisfied, uses the security check information stored in the storage means of the security check circuit as a clue, and controls the game control operation stored in the connected external storage means. It is determined whether the information for is appropriate.

[0007]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an overall system block diagram showing a security system using a game one-chip microcomputer according to the present invention.

A microcomputer chip according to the present invention is manufactured by a semiconductor chip maker 1. The semiconductor chip maker 1 is an MPU in a microcomputer.
(Micro Processing Unit), RA
A semiconductor chip in which M (Random Access Memory) and input / output ports (I / O ports) are integrated into one chip is manufactured. The chips manufactured by the semiconductor chip maker 1 include a mass-production chip 23a and a development chip 23b, which will be described in detail later. The mass production chip 23a is the RO connected to the mass production chip 23a.
The program has a determination function of determining whether or not the program stored in M is an appropriate program that has passed a test by a third-party testing institution 11 described later. Development chip 2
3b is a chip having no judgment function described above, and is the same as the chip for mass production 23a except that it does not have a judgment function.

[0010] Of the chips received from the semiconductor chip maker 1 to the chip distribution company 2, the mass production chips 23a are distributed by the mass production chip distribution section 2a and carried into the chip distribution management organization 3. On the other hand, the development chip 23 b is distributed by the development chip distribution section 2 b of the chip distribution company 2 and is carried into the chip distribution management organization 3. Note that the chip distribution company 2 may be a completely private company, or may be a public company formed by the government. The chip distribution management institution 3 is an organization for managing whether or not chips are properly distributed and mediating distribution of chips to a predetermined game machine maker or the like. The chip distribution management organization 3 may be omitted and chips may be directly carried in from the chip distribution company 2 to the game machine maker.

The mass production chip 23a and the development chip 23b carried into the chip distribution management organization 3 are carried into the mass production section 6 and the development section 5 of the gaming machine maker 4, respectively.
The development section 5 of the gaming machine maker 4 develops a program using the development chip 23b carried in as shown in FIG. Then, the development section 5 stores an application master ROM 10a in which the developed development program is stored.
As shown in FIG. 1A, a security code is requested to the security management section 2c of the chip distribution company 2. The security management section 2c writes a predetermined security code into the ROM 10a,
As shown in (B), development department 5 of gaming machine maker 4
To return. Development department 5 returns the returned application master RO
The M10a is mounted on the mass-production chip 23a, and further, these are mounted to create an application gaming machine, and an application document is created, and a plurality of application gaming machines / production machines on which the application master ROM 10a is mounted. The applicant submits an application submission 8 composed of documents 9 and the like, and applies for a test to a third-party testing institution 11 as shown in FIG.

The third-party testing institution 11 is composed of, for example, a commissioned agency of a public supervisory institution such as the police. The third-party testing institution 11 includes a test service section 12 and an appraisal service section 13. The test submission 8 is carried into the test service section 12, and the test application is accepted as shown in FIG. The test service section 12 tests the received test submission 8 as shown in FIG. 15 and determines whether or not the test result is acceptable as shown in FIG.
The gaming machine is returned to the gaming machine maker 4 as shown in (D). However, one of them is stored as it is in the third party testing institution 11, and the application master ROM 10a is removed from the gaming machine and delivered to the chip distribution management institution 3 as shown in FIG. If it is determined to be unsuccessful, the test service department 12 requests the chip distribution management organization 3 to discard the delivered ROM 10a as shown in FIG. The chip distribution management organization 3 disposes of the ROM 10a so as not to flow out. If the pass is determined to be acceptable, the request is made to the chip distribution management organization 3 to submit the application for granting a copy of the gaming machine maker 4 and return the delivered ROM 10a to the gaming machine maker 4, as shown in FIG. I do. In response, the chip distribution management organization 3
As shown in (F), the ROM 10a is returned to the gaming machine maker 4, and the fact that a request for submission of a certified copy application has been received is sent to the gaming machine maker. The gaming machine maker 4 having received the notification submits the certified copy application form and the ROM 10a to the third-party testing institution 11 as shown in FIG. Then, as shown in FIG. 1 (H), a certified copy is issued to the gaming machine maker 4 from the third party testing organization 11. The application master ROM 10a of the gaming machine stored in the third-party testing institution 11
Is used for appraisal work as a master ROM 10b for mass production.

On the other hand, the competent supervising organization 25 composed of polices in each prefecture also conducts an examination on the application gaming machine, and is judged to be passed by the third-party testing institution 11 and judged to be appropriate by the competent supervising organization 25. In the event that a game machine is installed in the amusement arcade. The read-only memory (R)
A third party organization is configured to test whether the development program stored in the OM passes certain criteria. The security code is an R code mounted on a game machine that has been determined to be accepted by a third party and is on the market.
The security information is used to determine whether or not the program stored in the OM is an appropriate program that has passed the test of the third party.

As the security code, for example, a method in which program data converted according to a predetermined conversion format is used as a security code can be considered.
In this case, all of the program data may be used as a reference for creating a security code, or a particularly important portion of the program data (for example, a data portion such as a jackpot probability or an opening time of a variable winning ball device) may be used as a reference for creating a security code. It may be.

Some of the returned application master ROMs 10a are carried into the mass production section 6 of the gaming machine maker 4 as mass production master ROMs 10b. The mass production section 6 copies the storage information stored in the mass production master ROM 10b as shown in FIG. Master ROM 1 for mass production
ROM 10c on which the storage information of the
Implemented in Further, the chips for mass production carried in from the chip distribution management organization 3 are transferred to the substrate 2 as shown in FIG.
2 Mounting chip 2 mounted on this substrate 22
The microcomputer 3 controls the gaming machine by the ROM 3c and the mounting ROM 10c.

After the chip 23 and the ROM 10c are mounted on the board 22, the power is turned on for the first time.
The security code included in the storage information of M10c is stored in the mounting chip 23 as described later. The mounting chip 23 composed of the mass production chip 23a
And has a function of storing only the security code stored in the ROM 10c which is attached first and is connected first. Then, based on the stored security code, it is determined whether or not the program stored in the mounting ROM 10c is an appropriate one that has passed the test of the third party organization. Once the ROM is mounted, the program stored in the ROM is altered,
In the case where 0c is replaced with a ROM storing a program created illegally, the security code stored in the mounting chip 23 and the security code stored in the ROM are inconsistent with each other, and the consistency is lost. lose. Therefore, it is possible to determine that the program has been tampered with.

Instead of having the game machine maker 4 copy the program and security code to the ROM and mount it on the board, the master ROM 1 for mass production is used.
0b may be carried into the chip distribution company 2, the chip distribution company 2 may copy the ROM and mount the ROM on the board, and then carry the board into the gaming machine maker 4. The gaming machine maker 4 constitutes a development / manufacturing company which develops a program for operating a central processing unit of a microcomputer for controlling the gaming machine and stores the development program in a read-only memory of the microcomputer. ing. The development and manufacturing company is not limited to the game machine maker, but may be a program development and manufacture company subcontracted to the game machine maker.

As described above, the mass-production chip 23a
If the program stored in the connected ROM is modified to make it different from the first program, it is determined that the program has been illegally modified so that the microcomputer does not operate in a normal state. Has the function of Therefore, when the development is performed by the development section 5 using the mass production chip 23a,
Every time the program stored in the ROM is debugged or the like and the program is changed, it is determined that the program is improper and the microcomputer does not operate normally. However, as described above, the development chip 23b does not have the security check function. Therefore, if the debugging or the like is performed using the development chip 23b, the microcomputer operates in a normal state, which is convenient for program development. In addition, the chip for mass production 23
The package a is made of, for example, plastic, and the package of the development chip 23b is made of, for example, ceramic so that the chip 23a for mass production and the chip 23b for development can be distinguished from the appearance of the chip.

The gaming machine 21 on which the board on which the chip and the ROM are mounted is mounted is carried into a game hall 24. In the amusement arcade 24, a plurality of carried-in gaming machines 21 are installed so that a player can play a game.

The jurisdiction supervising organization 25 performs a random inspection of the gaming machine 21 installed in the game arcade 24, and performs a collation process of the ROM of the gaming machine which seems to be malfunctioning as shown in FIG. Third-party testing institutes 1 whose ROMs have been verified but whose suitability is difficult to determine
A request for appraisal is made to the appraisal business unit 13 of the first section. For example,
If both the mounting chip 23 and the mounting ROM 10c are replaced with other illegally manufactured ones, the gaming machine will operate according to the remodeling program without performing the security check described above. In such a case, an appraisal request is made to the appraisal business unit 13.

In the appraisal business section 13, the board 2 on which the mounting chip 23 and the mounting ROM 10c requested for the appraisal are mounted is mounted.
Inspection and verification of the game machine are performed as shown in FIG. This gaming machine verification / collation 33 removes the ROM 10c mounted on the board 22 and mounts the mass production master ROM 10b storing an appropriate program in place of the ROM 10c to determine whether the mounting chip 23 operates normally. It is performed by verifying and collating. As a result, as shown in FIG. 28, an appraisal work / document is prepared, and the appraisal result is reported to the competent supervisory authority 25. Application master RO mentioned above
M10a, master ROM 10b for mass production, mounting ROM 10
c is formed of, for example, an EPROM.

FIG. 2 is a block diagram showing a mounting chip in a state where a chip for mass production is mounted on a substrate and various devices and circuits connected to the mounting chip.

The mounting chip 23 has a central processing unit (CP) capable of executing a control operation in a predetermined procedure.
U (Central Processing Unit)
40 and R which can write and call necessary data
The AM 41 and an I / O port 44 that receives input signals and provides input data to the CPU 40 and receives output data from the CPU 40 and outputs the data to the outside are integrated into one chip. A crystal oscillation signal from an externally provided crystal oscillator 45 is input to a clock generation circuit 46 provided on the mounting chip 23. The crystal oscillation signal from the crystal oscillator 45 has a frequency twice as high as the operation clock. Note that a vibration signal from a ceramic oscillator using ceramic as an oscillator instead of the crystal oscillator 45 may be input to the clock generation circuit 46.

The programmable clock dividing circuit 47 to which the clock signal from the clock generating circuit 46 is inputted,
The input clock signal is frequency-divided and a predetermined clock signal is output to the sound generator 48 and the variable display device display driving IC 49. The sound generator 48 outputs a control signal for generating sound to a speaker 97 (see FIG. 7) provided in the gaming machine. The variable display device display drive IC 49 is for controlling the variable display device 90 (see FIG. 7) provided in the gaming machine.
The U, RAM, ROM, and I / O ports are configured as one chip. The variable display device display driving IC 49 may be provided in a state of being connected to the programmable interrupt request timers 50 and 51 as shown by a dashed line in the drawing, or may be provided without the variable display device display driving IC 49. Display device 90 is directly connected to I / O port 4
4 may be controlled by an output signal.

The programmable interrupt request timer 0 (5
Reference numerals 0) and 1 (51) each comprise a 16-bit programmable counter timer, and include a free running counter and a compare register (two sets).
The programmable interrupt request timers 0 (50) and 1 (5
1) The main functions are interval timer function,
Event count function, one-shot output function, PW
Not only has an M (pulse width modulation) output function, but also a pulse width measurement function and a time difference measurement function.

The pulse width measuring function is, for example, a start winning switch 101a, 101b, 10 provided in a game machine.
This is a function for measuring the waveform length of the detection signal of the 1c or 10 count detection switch 102 (see FIG. 8). The time difference measurement function is a function of measuring the time from when there is a detection signal from the above-described various switches to when there is a next detection signal. The pulse width measurement function and the time difference measurement function
Programmable interrupt request timer 0 (50), 1 (51)
This can be achieved when the clock source of the counter is selected as an external input.

As the clock source of the counter, a clock can be selected and used as a refresh counter, and the output from the other programmable interrupt request timer can be selected as a clock source and used as a 32-bit counter. Can also. As a method of selecting these clock sources, a method of selecting them inside a program is adopted. In other words, there is a register at a certain address, a predetermined number is written in this register, and a clock source is selected according to the type of the written number.

This programmable interrupt request timer 0 (5
For 0) and 1 (51), an interrupt can be set by a counter output and a compare output, and the interrupt can be set to be routed to any one of exception processing of a user reset, a maskable interrupt, and a non-maskable interrupt. Further, by the function of the prescaler, the clock unit time of the timer can be arbitrarily set, and the values of the compare registers (two sets) can be arbitrarily set. Output signals from the programmable interrupt request timers 0 (50) and 1 (51) are input to the reset / interrupt controller 52.

This reset / interrupt controller 52
Has a system reset function and a user reset function. The system reset refers to initializing the entire mounting chip 23 including the I / O port 44 and restarting from the power-on state. On the other hand, the user reset is to perform a warm restart of the mounted chip 23 by resetting only the CPU 40. This user reset is performed, for example, once every 2 msec to enable interrupt processing. The reset / interrupt controller 52 receives a system reset signal, a user reset signal for performing a warm restart, a non-maskable interrupt request signal, and a maskable interrupt request signal from an interrupt request signal generating circuit 54. A system reset output signal is output from the reset / interrupt controller 52 to the interrupt request signal generation circuit 54.

The system reset signal input to the reset / interrupt controller 52 has a low active level input. That is, it is reset when the input signal switches from the high level to the low level. Similarly, the user reset signal input to the reset / interrupt controller 52 is low active and level input. The interrupt request signal generating circuit 54 may not be provided.

The mounting chip 23 is provided with an address decode circuit 57 and a data output time adjustment circuit 58. The address decode circuit 57 has an external I / O 67
And the external ROM 10c are connected. A microcomputer is formed by the mounting chip 23 and the external ROM 10c. This microcomputer may be implemented as a single chip including the mounting chip 23, the external ROM 10c, and the sound generator 48. The address decode circuit 57 has an address decode (chip select signal generation) function for setting an external input / output map area and an external ROM area to a space on a memory (physical address).

The external input / output map area can be set to an external input / output map area size of 256 B to 2 KB, and a chip select signal (6
Book). The external ROM area generates a chip select signal for the external ROM 10c.

The data output time adjusting circuit 58 provides a wait function for extending a machine cycle in order to interface with a low-speed input / output device. By setting, a wait state for a maximum of four machine cycles is possible. The output signal from the address decode circuit 57 is also input to the I / O port 44, and the input / output port is specified by specifying the bit of the I / O port 44 according to the output address. I have.

The I / O port 44 has 8 bits (port A
And a 4-bit (for port B) peripheral device interface port (PIP). These port terminals serve as a chip select terminal for external input / output and a handshake terminal (for one port) in addition to a general-purpose input / output port function. As shown in FIG.
There are three modes, a, b, and c, and a selection command for selecting one of the three modes is given from the external ROM 10 c to the I / O port 44 via the CPU 40. When the mode c is selected, an 8-bit general-purpose input / output port for setting input / output in units of bits and 6b
It provides a chip select function for it. To have a handshake function, the mode a or b is selected. Then, 8b that I / O setting can be done in Byte unit
It provides a general purpose input / output port. However, two terminals (P8, P9) are set as handshake terminals for port A, and timing signals and read / write signals are input / output to / from these handshake terminals P8, P9. This handshake terminal can be set to interrupt. In addition, routing of the handshake terminal interrupt can be set for maskable interrupt exception processing. Mode a
Is selected, the terminals P10 to P13 become chip select signal ports, and when mode b is selected, the terminals P10 to P13 become PIPs for port B without the handshake function.

Various drive circuits 55 and various switch circuits 56 of the gaming machine are connected to the I / O port 44. Then, signals from the various switch circuits 56 are given to the CPU 40 via the I / O port 44, and control signals from the CPU 40 are given to the various drive circuits 55 via the I / O port 44.

The watchdog timer 60 provided in the mounting chip 23 provides a function of detecting a malfunction (runaway) due to a cause such as noise or a drop in power supply voltage, and returning to a normal state. The signal from watchdog timer 60 is applied to system check circuit 61 and reset / interrupt controller 52. The watchdog timer 60 is configured to output a watchdog timer signal when the reset timing of the timer is equal to or longer than the maximum allowable reset interval time. The maximum allowable reset interval time can be set by the gaming machine maker 4 to a desired time. Furthermore, this watchdog timer 60 has an 8-bit
The clock unit time of the timer can be set by the function of the prescaler. The output of the watchdog timer signal can be set to be routed to any one of the exception processing of user reset, maskable interrupt, and non-maskable interrupt. The system check circuit 61 may not be provided.

An address bus terminal (16 terminals) and a data bus terminal (8 terminals) are connected to the external bus interface 43 provided on the mounting chip 23, and an address bus signal and a data bus signal are respectively output. You.
From the external bus interface 43, a signal indicating that the data bus is in a read cycle, a signal indicating that the data bus is in a write cycle, a signal indicating that access to the memory space is being performed, and an operation code fetch cycle is being executed. A signal indicating the presence is output. These output signals are output to the one-chip microcomputer ICE adapter board 59 (see FIG. 5) during program development. All the input / output terminals of the mounting chip 23 except the output terminal from the security check circuit 62 to the monitor device 60 are connected to the one-chip microcomputer ICE adapter board 59. Further, the address bus signal from the address bus terminal and the data bus signal from the data bus terminal are connected to the external I / O, respectively.
It is also output to port 67 and external ROM 10c. Also,
A data bus signal from the data bus terminal may be input to the I / O port of the variable display device display driving IC 49 and the data bus to operate the variable display device display driving IC. In this case, as the content of the signal input to the variable display device display driving IC, for example, a command signal for making the gaming machine a big hit can be considered. On the other hand, as the command signal input to the variable display device display drive IC 49, an output signal from the I / O port 44 may be input as a command signal.

In the figure, reference numeral 69 denotes a large-capacity capacitor;
This is for backing up the power supply of AM41.
In some cases, the capacitor 69 is not provided. This R
The AM 41 is configured to be able to perform bank switching by a bank switching signal from the security check circuit 62. This will be described with reference to FIG.

FIG. 3 is an explanatory diagram showing a memory map. As shown in FIG. 3, addresses 0000 to 7FFF
Are the addresses allocated to the external ROM 10c,
8000 to 81FF are addresses allocated to the RAM 41, and F000 to F7FF are external I / O.
Address assigned to 67, from FF00 to FFF
Addresses up to F are addresses allocated to the internal I / O 44.
Then, the RAM 41 stores the address from 8000 to 81FF.
Up to 256 / 512B (capacitor 6
9 is possible) and 256B. However, the capacity of the RAM 41 is 256B
At the time, the address is from 8000 to 80FF. Then, in the case of a general user mode described later, 25
A working area of 6 / 512B is used, and in the case of a user test mode described later, bank switching is performed and a working area of 256B is used. Of the 256 / 512B, 256 is for a pachinko game machine and 512 is for a slot machine.

The external ROM 10c is assigned addresses 0000 to 7FFF as described above.
An appropriate program is created to fit within this address. If a program is created to execute an instruction outside this address, it is determined that this program has been tampered with. In such a case,
The CPU 40 is configured to stop automatically and not execute an instruction.

The RAM 41 is backed up by a capacitor 69. However, if the power supply is momentarily interrupted for any reason, the CPU operation becomes unstable, and R
An abnormal access to the AM 41 may destroy data in the RAM 41. Therefore, the RAM 41 is provided with an access control function for prohibiting access to the RAM 41 in response to the output from the backup power supply at the moment of a power interruption.

That is, the RAM 41 is provided with an access control register, which controls whether or not access to the RAM 41 is possible according to the value of a predetermined bit. The rewriting of this bit is performed while the operation of the CPU 40 is still stable in response to a non-maskable interrupt generated by the backup power supply at the moment of a power interruption. When this bit is a value indicating that access is not allowed, neither data reading nor writing from the RAM 41 can be performed, so that an abnormal operation of the gaming machine can be prevented.

The security check circuit 62 provided on the mounting chip 23 includes a CPU 63, a ROM 64, an R
It has an AM 65, and the ROM 64 stores a program shown in FIG.

The program will be described with reference to FIG. The power is turned on, the system is reset, and in step S (hereinafter simply referred to as S) 1, the external ROM 1
Security code written in 0c and external RO
A process of checking the consistency with the program data of M10c is performed. The security code written in the external ROM 10c is, as described with reference to FIG.
This is a security code added to the development program, for example, a code obtained by converting program data of the external ROM 10c according to a certain conversion format.
Then, the conversion format is already stored in the ROM 64 of the security check circuit 62, and the consistency between the security code written in the external ROM 10c and the program data is checked in accordance with the stored conversion format.

Next, the flow proceeds to S2, where it is determined whether or not the result of the check is proper. If the result is proper, the flow proceeds to S3 to determine whether or not the security code is written in the security check circuit 62. A decision is made. The RO is mounted on the same substrate as the substrate 22 on which the mounting chip 23 is mounted.
When the power is turned on for the first time after the M10c is mounted, the process proceeds to S6 because the security code has not been written in the security check circuit 62 yet. In S6, after the process of writing the security code in the RAM 65 of the security check circuit 62 is performed, the process proceeds to S7. In this case, the program data in the ROM 11c may be directly written into the security check circuit 62 as security data. In S7, a process is performed in which the CPU 40 is activated without a time limit to enter a general user mode in which normal gaming machine control is performed. Also in this case, if there is a system runaway or the like, the system is reset and the processes after S1 are performed again.

On the other hand, R of the security check circuit 62
If the security code has already been written in the AM 65 , a determination of YES is made in S3 and the control proceeds to S4, in which the security code of the ROM 10c and the security code already written in the RAM 65 of the security check circuit 62 are compared. Check consistency. Next, the control proceeds to S5, where it is determined whether or not the check is appropriate. If the check is appropriate, the control proceeds to S7. If not, the control proceeds to S8, where C
The process shifts to a process of activating the PU 40 only for a predetermined time (for example, 60 seconds), that is, a user test mode. Then, if a certain time has elapsed or if there is a system runaway or the like, the system is reset again, and the processing after S1 is performed. S1, S2 and S4, S5
This constitutes an adequacy determining means for determining whether or not the control program stored in the read-only memory has passed the test by the third party. On the other hand, if it is determined that the result of the check in S2 and S5 is appropriate, the ROM 41 uses the working area of 256 / 512B as described above, while the result of the check in S2 and S5 When it is determined that the data is improper, a bank switching signal is output from the security check circuit 62 to the RAM 41 as shown in FIG. 2, and the RAM 41 is switched to the working area of 256B. If the CPU is activated only within the time limit (for example, 60 seconds) by S8, the operation of the microcomputer within the time limit is performed in the working area of 256B of the RAM 41.

One of the reasons for activating the CPU 40 only for a predetermined period of time (for example, 60 seconds) even if the result of this check is inappropriate is, for example, a game machine 24 shown in FIG. Before shipment to the board, the board may be checked or the control of the variable display device or the like provided on the game board may be checked again. In such a case, the mounting ROM 10c already mounted on the board 22 is pulled out once and other checks are performed. The purpose of this is to insert a ROM in which a program for use is stored and perform a check. Even if a ROM in which a program different from the passing program is stored is mounted, the microcomputer operates for a predetermined time (for example, 60 seconds). This is so that the above-described check can be performed. Another reason is that a program development company for controlling a gaming machine creates a program, passes the test of the third-party testing institution 11 and passes the test, and then stores the ROM 10c storing the passed program and the chip 23 on the substrate 22. This is because a board check may be performed before mounting and shipping to the gaming machine maker 4. In this case, the board check is performed by replacing the test ROM with a test ROM in which a test program in which the control time is shortened, for example, by shortening the opening period of the variable prize ball device at the time of the big hit, is replaced with the pass ROM Short time limit (for example, 60 seconds) after mounting on the substrate 22
I / O tests can be performed quickly within the system. In the case of such a user test mode, the reason for switching the working area of the RAM 41 to 256B is that if the working areas of the general user mode and the user test mode are made the same, a program for program modification is stored. The illegally inserted ROM is inserted into the board 22, and the microcomputer is operated according to the program for the program modification for a limited time (for example, 60 seconds), and
An external ROM in which various constants and the like stored through the AM 41 are rewritten and a pass program is stored later.
Even if 10c is mounted on the board 22, the microcomputer may operate improperly because the constants and the like have already been rewritten, and in the case of the user test mode in order to prevent such inconvenience, This is for operating in a working area different from the general user mode.

Further, S1 to S5 or S1 shown in FIG.
The time required for the security checks in steps S3 and S6 is set to, for example, about 3 to 5 seconds. 3 ~
The reason why the configuration is made to be a relatively long time of about 5 seconds is that when a ROM storing an illegally modified program other than a passing program is mounted on the board 22, the above-mentioned 3 to 3 is applied every time the time limit elapses. Perform a security check for about 5 seconds to make the CPU inoperable during that time,
This is because the CPU is stopped for a long period of about 3 to 5 seconds and the gaming machine is intentionally not operated normally, so that an illegally remodeled program may interfere with the game.

In S8, the time limit (for example, 6
(0 seconds), the CPU may not be activated until the power is turned on next time. After repeating the process of resetting the system after the time limit elapses a predetermined number of times, the CPU 40 is stopped so that the operation in the user test mode is not performed again even if the power is turned on again depending on the inappropriate ROM. You may comprise.

The security check processing time of about 3 to 5 seconds and the time limit (for example, 60 seconds) become shorter when the oscillation frequency of the crystal oscillator 45 becomes higher, and become longer when the oscillation frequency becomes lower. . When the monitor device 60 is connected to the security check circuit 62 as shown in FIG. 2, it is possible to determine whether the current mode of the chip is the general user mode or the user test mode. In the figure, 66 and 68 are data buses.

The development chip 23b is the same as the mass production chip 23a except that the security check circuit 62 shown in FIG. 2 does not exist. In addition,
The security check circuit 62 is also provided for the development chip 23b.
May be provided so that a program for performing a security check is not stored in the ROM 64.

The mass production chip 23a and the development chip 2
3b is a so-called ASIC (application)
specific integrated circuit
t), which is a chip dedicated to pachinko gaming machines and slot machines. Further, a chip for limiting the gaming machine maker 4 may be used. In the above-described embodiment, various functions are integrated into one chip. However, each of these functions may be configured by a single component.

FIG. 6 is a block diagram showing a part of a microcomputer development system when a program is developed using a development chip in a development section of a gaming machine maker.

In the figure, reference numeral 80 denotes a CPU ICE, which is a commercially available product. ICE (in-circuit emulato
r) is MDS (microcomputerdev)
The emulation of the hardware of the microcomputer system is performed under an employment system. The CPU ICE 80 is an ICE for a gaming machine control microcomputer before being made into a single chip, and develops a microcomputer program by effectively utilizing this commercially available conventional CPU ICE 80. For this purpose, the one-chip microcomputer ICE adapter board 59 is required. This one-chip microcomputer ICE adapter board 59 is a chip distribution company 2 shown in FIG.
Has been released. The CPU probe 81 of the CPU ICE 80 and the CPU socket 84 of the one-chip microcomputer ICE adapter board 59 are connected, and the one-chip microcomputer probe 8 of the one-chip microcomputer ICE adapter board 59 is further connected.
2 and the one-chip microcomputer socket 84 of the product development board 83 are connected, and microcomputer program development becomes possible. Reference numeral 10 denotes a ROM connected to the development chip 23b.

FIG. 7 is an overall front view showing a pachinko gaming machine 21 as an example of a gaming machine in which a microcomputer for controlling a gaming machine is incorporated.

When the player operates a hitting ball operation handle 92 provided at the lower right corner of the pachinko gaming machine 21, the hitting ball firing device 93 (see FIG. 8) is operated, and the pachinko balls are placed one by one in the game area 94. Is driven into. Gaming area 94
The pachinko balls that are driven into the inside are the starting winning prizes 96a, 96
If any one of b and 96c is won, the variable display device 90 capable of variably displaying a plurality of types of identification information variably starts.
This variable display device is provided with a plurality of (three in the drawing) drums. Variable display is performed by rotating this drum with, for example, a stepping motor, and the variable display is performed by stopping the stepping motor. The display can be stopped. The variable display device 9
0 means liquid crystal display or segment L instead of using a drum.
It may be constituted by a digital display using an ED, a dot matrix LED, electroluminescence, or the like.

When the display result when the variable display device is stopped is a combination of predetermined identification information (for example, 777), the variable winning ball device 95 is opened and the pachinko ball is likely to win. The first state is advantageous to the player, and the big hit state occurs. Whether or not to generate the big hit state is determined by picking up the value of the random number counter which is counted up by using the reset waiting time of the microcomputer at the time of winning the start, and based on the picked up value.

In this embodiment, a pachinko game machine in which a pachinko ball is inserted to play a game is shown. However, a card processor including a card reader / writer or the like is provided to record information capable of specifying a predetermined value. A card-type gaming machine in which a recording medium such as a card or the like is inserted into the card processor and a game can be played within a value range specified by the recording medium may be used. In this case, the card processor may be provided so as to be separable from the pachinko gaming machine 21, or may be incorporated in the pachinko gaming machine 21. In the case of this card-type gaming machine, the acquired score obtained by the game is displayed, and at the end of the game, a premium recording medium on which a valuable value corresponding to the score is recorded is paid out to the player. This premium recording medium may be constituted by a recording medium different from the storage medium inserted into the card processor at the start of the game, or the recording area of the storage medium inserted at the start of the game is divided into two parts. The value required at the start of the game may be recorded in the recording area, and the value corresponding to the acquired score at the end of the game may be recorded in the other recording area and paid out to the player. In the figure, reference numeral 97 denotes a speaker that generates a sound effect or the like at the time of a big hit based on a signal from the sound generator 48 (see FIG. 2).

FIG. 8 is an overall rear view showing the internal structure of the pachinko gaming machine 21.

The starting winning ports 96a, 96b, 96c
(See FIG. 7) is a winning ball detection switch 1
01a, 101b, and 101c, and the detection signals are supplied to various switch circuits 56 of the game control main board 22.
(See FIG. 2). In addition, the variable winning ball device 95
Is detected by the 10-count detection switch 102, and the detection signal is transmitted to the game control main board 22.
Are input to the various switch circuits 56. The game control main board 22 has a connector 103 mounted thereon with the chip 23 and the external ROM 10c, and the detection signal is input via this connector. In the figure, reference numeral 180 denotes a solenoid for opening and closing the variable winning ball apparatus 95, which is controlled based on a drive control signal from each drive circuit 55 of the game control main board 22. Game control main board 22
Is provided on the mechanism plate side of the gaming machine 21 in a state housed in the board case 104. In the figure, reference numeral 108 denotes a game control sub-board, which is a variable display device display driving IC 49 described above.
Has been implemented. The game control sub-board 108 is provided with a connector 107, and the connector 107 is connected to the connector 103 of the game control main board 22 via the connection wiring 105. Further, the pachinko gaming machine 21 is provided with a relay terminal board 111, and the connector 110 of the relay terminal board 111 and the connector 103 of the game control main board 22 are connected via the connection wiring 105. Further, the connector 103 of the game control main board 22 and the locking device 113 are connected via the ground wire 112, and the game control main board 22 is in a grounded state.

FIG. 9 is an exploded perspective view showing the structure of a board case for accommodating the game control main board 22.

The external ROM 10c is mounted on the game control main board 22 on which the mounting chip 23 is mounted (see arrow in the figure), and then the connector 1 of the game control main board 22 is mounted.
The game control main board 22 is mounted and fixed in the board storage box main body 120 while the connection wiring 105 and the ground wire 112 are connected to 03. Then, the transparent cover 12
1 covers the substrate storage box main body 120. An engagement hole 124 is provided in the substrate storage box body 120, and the claw 1 provided on the transparent cover body 121 side is provided.
25 is inserted into the engagement hole 124, and the transparent cover 121 is
Fixed to. Next, the opening / closing cover body 122 is attached to the substrate storage box main body 120 so as to be freely opened and closed. The opening / closing cover body 122 is provided with a support shaft 128, and an insertion hole 127 provided on the substrate storage box main body 120 side.
The opening / closing cover body 122 is supported on the substrate storage box main body 120 side so as to be freely opened / closed by passing the support shaft 128 through. On the other hand, an engagement claw portion 123 is formed in the substrate storage box main body 120, and an engagement hole 129 that engages with the engagement claw portion 123 is formed on the opening / closing cover body 122 side. The opening / closing cover body 122 is fixed to the board storage box main body 120 by externally fitting the engagement claws 129 to the engagement claws 123 and engaging them. And the opening and closing cover body 12
When it is desired to open 2, the engagement can be easily opened by releasing the engagement between the engagement claw 123 and the engagement hole 129.

In the drawing, reference numeral 132 denotes a sealing seal, which is attached to the transparent cover 121 and the substrate storage box main body 120 with the transparent cover 121 attached to the substrate storage box 120. In this case, for example, the transparent cover 121 is replaced with the board storage box body 1 in order to replace the external ROM 10c with another external ROM.
If the transparent cover 121 is detached from the seal cover 132, the seal 132 is broken. Therefore, it is possible to determine whether the transparent cover body 121 has been detached by looking at the seal 132. Reference numeral 130 denotes a notch for guiding the connection wiring 105 and the ground wire 112 to the outside of the board case 104.

Transparent cover body 121 and openable cover body 122
Are provided with a large number of heat radiation holes 131 so that heat from the game control main board 22 housed in the board case 104 can be released to the outside.
The board storage box body 120 and the opening / closing cover body 12
Numeral 2 is formed of, for example, a synthetic resin obtained by mixing carbon with polypropylene in order to enhance conductivity. The color of this resin is black. The transparent cover body 121 is made of a transparent material such as polycarbonate.
The game control main board 22 can be viewed from outside the transparent cover body 121 by opening the game control board 2, and the game control board 22 can be removed without detaching the transparent cover body 121 from the board storage box main body 120. It is configured so that it is possible to confirm to a certain extent whether there is any abnormality when viewed. Further, carbon may be mixed into polycarbonate or the like constituting the transparent cover body 121.
The transparent cover body 121 does not need to be completely transparent, and may be of such a degree that the inside can be seen through. In addition,
The substrate storage box main body 120 and the opening / closing cover body 122 may be formed of a metal plate.

[0065]

The present invention relates to a one-chip microcomputer for controlling a gaming machine carried into a game arcade. When a proper storage means is first mounted, security check information corresponding to the security code is provided. Is automatically stored. Then, in the case where an unauthorized remodeling operation is performed by the storage unit storing the unauthorized information other than the appropriate game control operation information, the inappropriateness is determined by the appropriateness determination unit, and the game is not executed. In addition, it is easy to prevent the gaming machine from being controlled by the illegal gaming control information. Further, since the security check information is automatically stored, there is no input error or omission.

[Brief description of the drawings]

FIG. 1 is a system block diagram schematically showing a security system using a gaming machine control microcomputer according to the present invention.

FIG. 2 is a block diagram showing a mounting chip constituting a gaming machine control microcomputer according to the present invention and circuits of peripheral devices connected thereto.

FIG. 3 is an explanatory diagram showing a memory map of the gaming machine control microcomputer according to the present invention.

FIG. 4 is an explanatory diagram for explaining a function corresponding to an I / O port mode.

FIG. 5 is a flowchart showing a program stored in a ROM provided in a security check circuit of the gaming machine control microcomputer.

FIG. 6 is a block diagram showing a part of a development system of the gaming machine control microcomputer.

FIG. 7 is an overall front view showing a pachinko gaming machine as an example of the gaming machine.

FIG. 8 is an overall rear view showing the internal structure of the pachinko gaming machine.

FIG. 9 is an exploded perspective view for explaining the structure of the board case.

[Explanation of symbols]

 4 Example of a gaming machine maker 10a Application ROM 10b Mass production ROM 10c Mounting ROM 11 Third-party testing institution 21 Pachinko gaming machine as an example of gaming machine 23 Mounting chip 24 Amusement arcade 25 Jurisdiction overseeing agency

Claims (1)

(57) [Claims] An external storage means (10c), which is detachably connected and stores predetermined program data for a game control operation and a predetermined security code converted according to a predetermined format based on the data; A microcomputer incorporating a security check circuit having storage means for storing a predetermined security code stored in the external storage means (10c) and storage means for storing a predetermined conversion format program; If the security code stored in the external storage means (10c) matches the security code converted according to a predetermined conversion format based on the program data stored in the storage means (10c), the storage means of the security check circuit Already have a security code It performed whether collation is incorporated can, if not written C after writing in the storage means
The PU is activated, and if a security code has been written in the storage means of the security check circuit, it is determined whether or not both security codes match, and if so, the CPU is activated. A microcomputer for controlling a gaming machine, comprising: