JP2852853B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film insulated gate field effect transistor (thin film transistor or TF).
The present invention relates to a method for obtaining a crystalline semiconductor used for a thin film device such as T).

[0002]

2. Description of the Related Art Conventionally, a crystalline silicon semiconductor thin film used for a thin film device such as a thin film insulated gate field effect transistor (TFT) is manufactured by a plasma CVD method or a thermal CV method.
The amorphous silicon film formed by the method D was crystallized in a device such as an electric furnace at a temperature of 600 ° C. or more for a long time of 24 hours or more. In particular, a longer heat treatment has been required to obtain sufficient characteristics (high field effect mobility and high reliability).

[0003]

However, such a conventional method has many problems. One is lower throughput and therefore higher cost. For example, assuming that the crystallization step requires 24 hours, if the processing time per substrate is 2 minutes, 720 substrates must be processed simultaneously. However, for example, in a commonly used tubular furnace, at most 50 substrates can be processed at a time, and when only one apparatus (reaction tube) is used, it takes 30 minutes per substrate. I have. That is, 1
In order to set the processing time per sheet to 2 minutes, as many as 15 reaction tubes had to be used. This meant that the size of the investment would increase, and that the investment would be significantly depreciated, which would return to the cost of the product.

[0004] Another problem was the temperature of the heat treatment. In general, substrates used for manufacturing TFTs are roughly classified into those made of pure silicon oxide such as quartz glass and non-alkali borosilicate glass such as Corning No. 7059 (hereinafter referred to as Corning 7059). Among them, the former has excellent heat resistance and can be handled in the same manner as a wafer process of a normal semiconductor integrated circuit, so that there is no problem regarding the temperature. However, its cost is high, and it increases exponentially rapidly as the substrate area increases. Therefore, at present, a relatively small area T
Used only for FT integrated circuits.

On the other hand, alkali-free glass has a sufficiently low cost as compared with quartz, but has a problem in terms of heat resistance, and generally has a strain point of about 550 to 650 ° C. Therefore, the heat treatment at 600 ° C. caused a problem of irreversible shrinkage and warpage of the substrate. In particular, it was remarkable for a large substrate having a diagonal exceeding 10 inches. For the above reasons, regarding crystallization of a silicon semiconductor film, a heat treatment condition of 550 ° C. or lower and within 4 hours has been indispensable for cost reduction. An object of the present invention is to provide a method for manufacturing a semiconductor which satisfies such a condition and a method for manufacturing a semiconductor device using such a semiconductor.

[0006]

SUMMARY OF THE INVENTION The present invention relates to an amorphous state or a disordered crystalline state that can be said to be substantially amorphous (for example, a state in which a portion having good crystallinity and an amorphous portion are mixed). ) Islands containing nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, silver above or below the silicon film Film, dots, particles, clusters, lines, etc. are formed, and this is crystallized silicon film by annealing at a temperature lower than the crystallization temperature of ordinary amorphous silicon by simple heat treatment and for a shorter time. It is characterized by obtaining.

With respect to the conventional crystallization of a silicon film, a method of solid-phase epitaxial growth using a crystalline island-like film as a nucleus and using this as a seed crystal (for example, Japanese Patent Laid-Open No. 1-21)
4110). However, in such a method, crystal growth hardly proceeded at a temperature of 600 ° C. or less. In a silicon system, generally, in order to transition from an amorphous state to a crystalline state, a molecular chain in an amorphous state is divided, and furthermore, the divided molecule is brought into a state where it does not bind to another molecule again. It goes through the process of recombining a molecule into a part of the crystal in accordance with some crystalline molecule. However, during this process, the energy required to break the initial molecular chain and keep it unbound to other molecules is large,
This is a barrier in the crystallization reaction. In order to provide this energy, at a temperature of about 1000 ° C. for several minutes,
Alternatively, at a temperature of about 600 ° C., several tens of hours are required, and since the time depends exponentially on the temperature (= energy), at 600 ° C. or less, for example, at 550 ° C., the crystallization reaction hardly progresses. It could not be observed. The conventional idea of solid phase epitaxial crystallization did not provide a solution to this problem.

The present inventor has considered, apart from the conventional idea of solid-phase crystallization, to reduce the barrier energy of the above-mentioned process by some catalytic action. The present inventor has proposed nickel (element symbol Ni), iron (Fe), cobalt (C
o), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (I
r), platinum (Pt), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), copper (Cu), zinc (Zn), gold (Au),
Silver (Ag) is easily bonded to silicon.

[0009] For example, in the case of nickel, easily nickel silicide (Formula _{NiSi x, 0.4 ≦ x ≦ 2.5} ) , and the and the lattice constant of the nickel silicide is noticed that close to that of silicon crystal. Therefore, as a result of simulating the energy of a ternary system such as crystalline silicon-nickel silicide-amorphous silicon, amorphous silicon easily reacts at the interface with nickel silicide, and amorphous silicon (silicon A) + nickel silicide (silicon B) → It became clear that the reaction of nickel silicide (silicon A) + crystalline silicon (silicon B) (silicon A and B indicate the position of silicon) occurs. The potential barrier for this reaction is sufficiently low and the temperature of the reaction is low. This reaction equation shows that nickel proceeds while transforming amorphous silicon into crystalline silicon. Actually, the reaction starts below 580 ° C.
It became clear that the reaction was observed even at 0 ° C. Naturally, the higher the temperature, the faster the reaction proceeds. Similar effects were also observed with the other metal elements shown above.

In the present invention, island-like, stripe-like, linear,
Ni, Fe, Co, Ru, Rh, etc.
Pd, Os, Ir, Pt, Sc, Ti, V, Cr, M
Starting from a film, a particle, a cluster, or the like containing at least one of n, Cu, Zn, Au, and Ag, these metal elements are developed from here to the surroundings with the above-described reaction, thereby forming a crystal. Expand the area of silicon. Note that an oxide is not preferable as a material containing these metal elements. This is because oxides are stable compounds and cannot initiate the above reaction.

Although the crystalline silicon expanded from a specific place is different from the conventional solid phase epitaxial growth, it has a good crystal continuity and a structure close to a single crystal. It is convenient for use in an element. However, when a material containing the above-mentioned metal that promotes crystallization of nickel or the like is uniformly provided on the substrate, there are countless starting points of crystallization, and therefore, it is difficult to obtain a film having good crystallinity. was difficult.

The amorphous silicon film as a starting material for this crystallization had better results as the hydrogen concentration was lower. However, since hydrogen is released as the crystallization progresses, the hydrogen concentration in the obtained silicon film did not show a clear correlation with the hydrogen concentration in the amorphous silicon film as the starting material. The hydrogen concentration in crystalline silicon according to the invention is typically 0.01 atomic%.
Not less than 5 atomic%.

In the present invention, Ni, Fe, Co, Ru, R
h, Pd, Os, Ir, Pt, Sc, Ti, V, Cr,
Mn, Cu, Zn, Au, and Ag are used, but generally, these materials are not preferable for silicon as a semiconductor material. Therefore, it is necessary to remove the nickel. However, as for nickel, nickel silicide that has reached the end of crystallization as a result of the above reaction is easily dissolved in hydrofluoric acid or hydrochloric acid or a diluent thereof, so Nickel can be reduced from the substrate by treating with acid. In addition, to actively reduce these metal elements,
After completion of the crystallization step, hydrogen chloride, various methane chlorides (CH ₃ Cl, CH ₂ Cl ₂ , CHCl ₃ ), various ethane chlorides (C ₂ H ₅ Cl, C ₂ H ₄ Cl ₂ , C ₂ H ₃ Cl)
₃ , C ₂ H ₂ Cl ₄ , C ₂ HCl ₅ ) or various types of ethylene chloride (C ₂ H ₃ Cl, C ₂ H ₂ Cl ₂ , C ₂ HCl)
_The treatment may be performed at 400 to 600 ° C. in an atmosphere containing chlorine such as ₃ ). In particular, trichlorethylene (C ₂ HCl
₃ ) is an easy-to-use material. Ni, Fe, Co, Ru, Rh, Pd, Os, I in the silicon film according to the present invention
r, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn,
The concentration of Au or Ag is typically 0.0005 atomic%.
It was at least 1 atomic%.

In utilizing the crystalline silicon film produced according to the present invention for a semiconductor device such as a TFT, as is apparent from the above description, the termination of crystallization (here, the crystallization started from a plurality of starting points) Is where it hits)
There are large grain boundaries (crystal discontinuities),
It is not preferable to provide a semiconductor element because the concentration of nickel or another metal element that promotes crystallization is high. Therefore, in forming a semiconductor device using the present invention, it is necessary to optimize the pattern of the coating film of the metal element containing nickel and other elements that promote crystallization, which is the starting point of crystallization, and the pattern of the semiconductor device. .

In the present invention, there are roughly two methods for patterning a metal element for promoting crystallization. The first method is to selectively form these metal films and the like before forming the amorphous silicon film. Second
Is a method of selectively forming these metal films and the like after forming an amorphous silicon film.

In the first method, ordinary photolithography means or lift-off means may be used. The second method is somewhat complicated. In this case, when a metal film or the like for promoting crystallization is formed in close contact with the amorphous silicon film, a part of the metal and the amorphous silicon react during the film formation, and silicide is formed. Therefore,
When patterning is performed after forming a metal film or the like, it is necessary to sufficiently etch such a silicide layer as well.

In the second method, a lift-off method is relatively easy. In this case, an organic material such as a photoresist or an inorganic material such as silicon oxide or silicon nitride may be used as the mask material. The process temperature must be considered when selecting the mask material. Care must be taken because the masking action varies depending on the material. In particular, a film of silicon oxide, silicon nitride, or the like formed by various CVD methods has many pinholes, and if the film thickness is not sufficient, crystallization may proceed from an unintended portion. In general, after a film is formed using these mask materials, patterning is performed to selectively expose the surface of amorphous silicon. Then, a metal film or the like for promoting crystallization is formed.

In the present invention, what should be noted is the concentration of the metal element in the silicon film. It is important to keep the volume constant, but it is also important to keep the volume constant. That is, if the amount of the metal element fluctuates greatly, the degree of crystallization varies greatly from lot to lot at the manufacturing site. In particular, when the amount of the metal element is required to be small, it is increasingly difficult to reduce the fluctuation of the amount.

In the first method, since the selectively formed metal film or the like is covered with the amorphous silicon film, it cannot be taken out later to adjust the amount. In particular, when converted from the amount of the metal element required in the present invention, the thickness of the metal film or the like is as small as several to several tens of degrees, and it is difficult to form a film with good reproducibility.

The same applies to the second method. However, in the second method, a metal film or the like which promotes crystallization is present on the surface, so that there is still room for improvement as compared with the first method. That is, a sufficiently thick metal film is formed,
By performing heat treatment (pre-annealing) at a temperature lower than the annealing temperature before annealing, a part of the amorphous silicon film reacts with the metal film to form silicide. Thereafter, the unreacted metal film is etched.
Depending on the type of metal used, particularly Ni, Fe, Co, T
For i and Cr, there is no problem because there is an etchant in which the etching rates of the metal film and the silicide are sufficiently large.

In this case, the thickness of the obtained silicide layer is determined by the temperature and time of the heat treatment (pre-annealing). The thickness of the metal film is almost irrelevant. Therefore, the amount of a very small amount of metal element introduced into the amorphous silicon film can be controlled. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0022]

【Example】

[Example 1] In this example, a plurality of island-shaped nickel films were formed on a Corning 7059 glass substrate, and an amorphous silicon film was crystallized using these as starting points, and the obtained crystalline silicon film was used. A method for manufacturing a TFT will be described. There are two methods for forming an island-like nickel film in terms of whether to provide it above or below an amorphous silicon film. FIG.
(A-1) is a method provided below, and FIG. 2 (A-2) is a method provided above. In particular, the latter must be noted because nickel is formed on the entire surface of the amorphous silicon film and then this is selectively etched, so that nickel and amorphous silicon react in a small amount to form silicide. Nickel is formed. If this is left as it is, a silicon film having good crystallinity as intended by the present invention cannot be obtained. Therefore, it is required to sufficiently remove the nickel silicide with hydrochloric acid, hydrofluoric acid, or the like. . Therefore, the amorphous silicon becomes thinner than the initial state.

On the other hand, in the former case, such a problem does not occur, but also in this case, the island-shaped portion 2 is formed by etching.
It is desired that other nickel films be completely removed.
Further, in order to suppress the influence of the remaining nickel, the substrate may be treated with oxygen plasma, ozone, or the like to oxidize nickel in regions other than the island region.

In each case, the substrate (Corning 705)
9) On top of 1A, underlying silicon oxide film 1B having a thickness of 2000
Was formed by a plasma CVD method. The amorphous silicon film 1 has a thickness of 200 to 3000 °, preferably 500 to 1500 °, and is manufactured by a plasma CVD method or a low pressure CVD method. The amorphous silicon film is dehydrogenated by annealing at 350 to 450 ° C. for 0.1 to 2 hours to reduce the hydrogen concentration in the film to 5%.
Crystallization was easy when the content was less than atomic%. FIG. 2 (A
In the case of -1), a nickel film having a thickness of 50 to 100 is formed by a sputtering method before the formation of the amorphous silicon film 1.
0 °, preferably 100 to 500 °, was deposited and then patterned to form island-shaped nickel regions 2.

On the other hand, in the case of FIG. 2A-2, after the amorphous silicon film 1 is formed, the nickel film is formed by sputtering to a thickness of 50 to 1000 Å, preferably 100 to 1000 Å.
An island-shaped nickel region 2 was formed by depositing 500 ° and patterning it. Figure 1 shows this situation viewed from above.
It is shown in (A).

The island nickel is a square having a side of 2 μm, and the interval is 5 to 50 μm, for example, 20 μm. Similar effects can be obtained by using nickel silicide instead of nickel. When depositing nickel, the substrate should be 100 to 5 mm.
Good results were obtained by heating to 00 ° C, preferably 180-250 ° C. This is because the adhesion between the underlying silicon oxide film and the nickel film is improved, and the silicon oxide reacts with the nickel to produce nickel silicide. Similar effects can be obtained by using silicon nitride, silicon carbide, or silicon instead of silicon oxide.

Next, this is heated at 450 to 580 ° C., for example, at 5 ° C.
Annealing was performed at 50 ° C. for 8 hours in a nitrogen atmosphere. FIG.
FIG. 2B shows the intermediate state. In FIG. 2A, nickel proceeds from the island-like nickel film at the end to the central portion as nickel silicide 3A, and the portion 3 through which nickel has passed is crystal. It is silicon. Eventually, FIG.
As shown in (C), the crystallization starting from the two island-shaped nickel films hits, leaving nickel silicide 3A in the middle, and the crystallization ends. At this time, the area where the object is
Crystallization is grown laterally from the region to a width of 20 to 200 μm.
Close.

FIG. 1B shows a state of the substrate in this state as viewed from above. The nickel silicide 3 shown in FIG.
A is the grain boundary 4. If the annealing is further continued, nickel moves along the grain boundaries 4 and gathers in the intermediate region 5 of these island-like nickel regions (although the original shape is not retained at this stage).

Crystalline silicon can be obtained by the above steps, but it is not preferable that nickel diffuses into the semiconductor film from the nickel silicide 3A generated at this time. Therefore, it is desired to etch away high concentration regions where nickel is concentrated with hydrofluoric acid or hydrochloric acid. In the etching with hydrofluoric acid and hydrochloric acid, the etching rates of nickel and nickel silicide are sufficiently large, so that the silicon film is not affected. At the same time, the region where the nickel growth point was located was also removed. FIG. 2D shows the state after the etching. The part with the grain boundary is groove 4.
A. It is not preferable to form a semiconductor region (such as an active layer) of the TFT so as to sandwich this groove. FIG. 1C shows an example of the arrangement of the TFTs. The semiconductor region 6 is arranged so as not to cross the grain boundaries 4. That is, a TFT is formed in a region of crystal growth in a lateral direction not in the thickness direction of the film but in a direction parallel to the substrate, depending on the right and left sides of the nickel. Then, the crystal growth direction is also uniform,
Further, the residual nickel can be extremely reduced. As a result, high TFT characteristics can be obtained. On the other hand, the gate wiring 7 may cross the grain boundary 4.

FIGS. 3 and 4 show an example in which a TFT is manufactured using the crystalline silicon obtained in the above steps. FIG.
In (A), the X at the center means the location where the groove 4A in FIG. 2 was located. As shown in the drawing, the semiconductor region of the TFT is arranged so as not to cross the X portion. That is, the crystalline silicon film 3 obtained in the step shown in FIG. 2 was patterned to form the island-shaped semiconductor regions 11a and 11b. Then, a silicon oxide film 12 functioning as a gate insulating film was formed by a method such as an RF plasma CVD method, an ECR plasma CVD method, or a sputtering method.

Further, phosphorus is reduced to 1 × by a low pressure CVD method.
10 ²⁰ -5 × 10 ²⁰ cm ^-3 doped thickness 3000-
A 6000 ° polycrystalline silicon film was formed, and this was patterned to form gate electrodes 13a and 13b.
(FIG. 3 (A))

Next, impurity doping was performed by a plasma doping method. As the doping gas, for example, phosphine (PH ₃ ) was used for the N-type, and diborane (B ₂ H ₆ ) was used for the P-type. The figure shows an N-type TFT.
The accelerating voltage is 80 keV for phosphine and 6 for diborane.
5 keV. Further, the impurity was activated by annealing at 550 ° C. for 4 hours to form impurity regions 14 a to 14 d. For the activation, a method using light energy such as laser annealing or flash lamp annealing can also be used. (FIG. 3
(B))

Finally, a 5000-nm-thick silicon oxide film is deposited as an interlayer insulator 15 in the same manner as a normal TFT fabrication, and contact holes are formed in the silicon oxide film to form wiring / electrodes 16a to 16d in the source and drain regions. Was formed.
(FIG. 3 (C)) A TFT (N-channel type in the figure) was manufactured through the above steps. Field-effect mobility of the obtained TFT was 30 to 50 cm ² / Vs at 40~60cm ² / Vs, P-channel type N-channel type.

FIG. 4 shows a case where an aluminum gate TFT is manufactured. In FIG. 4A, the X in the center means the location where the groove 4A in FIG. 2 was located. As shown in the drawing, the semiconductor region of the TFT is arranged so as not to cross the X portion. That is, the crystalline silicon film 3 obtained in the step shown in FIG. 2 was patterned to form the island-shaped semiconductor regions 21a and 21b. And RF
A silicon oxide film 22 functioning as a gate insulating film was formed by a method such as a plasma CVD method, an ECR plasma CVD method, and a sputtering method. When the plasma CVD method is adopted, the source gas is TEOS (tetra ethoxy
Preferred results were obtained using silane) and oxygen. Then, an aluminum film containing 1% silicon (thickness 50
00Å) was deposited by a sputtering method, and this was patterned to form gate wiring / electrodes 23a and 23b.

Next, the substrate was immersed in a 3% solution of tartaric acid in ethylene glycol, anodized by passing a current through the aluminum wiring as an anode and platinum as a cathode. The current was initially applied so as to increase the voltage at 2 V / min. When the voltage reached 220 V, the voltage was kept constant. When the current became 10 μA / m ² or less, the current was stopped. As a result, the anodic oxides 24a, 2
4b was formed. (FIG. 4 (A))

Next, impurity doping was performed by a plasma doping method. As doping gas, phosphine (PH ₃ ) is used for N-type, and diborane (B) is used for P-type.
₂ H ₆ ). The figure shows an N-channel TFT.
The accelerating voltage is 80 keV for phosphine and 6 for diborane.
5 keV. Further, this is laser-annealed to activate the impurity, and the impurity region 2 is activated.
5a to 25d were formed. The laser used was KrF
250-300mJ / with laser (wavelength 248nm)
Five shots of laser light having an energy density of cm ² were irradiated. (FIG. 4 (B))

Finally, a 5000-nm-thick silicon oxide film is deposited as an interlayer insulator 26 in the same manner as in the normal TFT fabrication, and contact holes are formed in the silicon oxide film to form wiring / electrodes 27a to 27d in the source and drain regions. Was formed.
(FIG. 4C) The field effect mobility of the obtained TFT is 60 for the N-channel type.
~120cm ² / Vs, 50~90cm in P-channel type
² / Vs. A shift register manufactured using this TFT has a drain voltage of 17 V, 6 MHz,
Operation at 11 MHz at 20 V was confirmed.

Embodiment 2 FIG. 5 shows a case in which an aluminum gate TFT is manufactured in the same manner as in FIG. However, here, amorphous silicon was used as the active layer. As shown in FIG. 5A, a base silicon oxide film 32 is deposited on a substrate 31 and further has a thickness of 2000 to 30.
An amorphous silicon film 33 of 00 ° was deposited. An appropriate amount of P-type or N-type impurities may be mixed in the amorphous silicon film. Then, as shown above, the island-shaped nickel or nickel silicide coating 34 is formed.
A and 34B were formed, and in this state, the amorphous silicon film was crystallized by lateral growth by annealing at 550 ° C. for 8 hours or at 600 ° C. for 4 hours.

Next, the crystalline silicon film thus obtained was patterned as shown in FIG. At this time, since the silicon film in the center of the figure (the middle part between the nickel or nickel silicide coatings 34A and 34B) contains a large amount of nickel, patterning is performed so as to remove this, and the island-like silicon regions 35A, 35B was formed.
Further, a substantially intrinsic amorphous silicon film 3 is formed thereon.
6 was deposited. Thereafter, as shown in FIG. 5C, a film is formed of a material such as silicon nitride or silicon oxide as a gate insulating film 37, a gate electrode 38 is formed of aluminum, and anodic oxidation is performed as in the case of FIG. The impurity is diffused by an ion doping method to form an impurity region 39.
A and 39B are formed. Further, an interlayer insulator 40 is deposited, a contact hole is formed, and the metal electrodes 41A and 41A are formed.
B is formed on the source and the drain to complete the TFT. This TFT is characterized in that the semiconductor film in the source and drain portions is thicker and the resistivity is smaller than the thickness of the active layer. As a result, the resistance of the source and drain regions is reduced, and the characteristics of the TFT are reduced. Is improved. Also, the formation of the contact is easy.

Third Embodiment FIG. 6 shows a CMOS type T
The case where FT fabrication was performed is shown. As shown in FIG. 6A, a base silicon oxide film 52 was deposited on a substrate 51, and an amorphous silicon film 53 having a thickness of 1000 to 1500 ° was further deposited. Then, an island-shaped nickel or nickel silicide film 54 is formed as described above, and annealed at 550 ° C. in this state. By this step, the silicon silicide region 55 moves not in the thickness direction of the film but in the plane direction, and crystallization proceeds. By annealing for 4 hours, the amorphous silicon film changes to crystalline silicon as shown in FIG. Further, the silicon silicide 59A and 59B are driven to the end by the progress of crystallization.

Next, the crystalline silicon film thus obtained was patterned as shown in FIG. 6B to form an island-like silicon region 56. At this time, it should be noted that the nickel concentration is high at both ends of the island region. After forming the island-shaped silicon region, a gate insulating film 57 and gate electrodes 58A and 58B were formed.

Thereafter, as shown in FIG. 5C, an impurity is diffused by an ion doping method to form an N-type impurity region 60A and a P-type impurity region 60B. At this time, for example, phosphorus is used as an N-type impurity (doping gas is phosphine PH ₃ ), the entire surface is doped with an acceleration voltage of 60 to 110 kV, and then the region of the N-channel TFT is covered with a photoresist. And a P-type impurity such as boron (doping gas is diborane B
₂ H ₆ ) and doping at an acceleration voltage of 40 to 80 kV.

After the end of the doping, the source and the drain are activated by irradiating a laser beam in the same manner as in FIG. 4, and further, an interlayer insulator 61 is deposited, contact holes are formed, and the metal electrodes 62A and 62B are formed. , 62C are formed on the source and the drain to complete the TFT.

Embodiment 4 FIG. 7 shows this embodiment. In this embodiment, a nickel film and a part of an amorphous silicon film are reacted by a first heat treatment (pre-annealing) to obtain a silicide, and further, an unreacted nickel film is removed, and then annealing is performed to perform crystallization. It is about the method of making it.

On a substrate (Corning No. 7059) 701, an underlying silicon oxide film (thickness: 2000 °) was formed by a sputtering method. Then, a silicon film 703 having a thickness of 300 to 800 °, for example, 500 ° was formed by a plasma CVD method. Further, a silicon oxide film 704 was formed by a plasma CVD method. This silicon oxide film 704
Is a mask material. The thickness was preferably 500 to 2000 mm. If it is too thin, crystallization proceeds from an unintended portion due to a pinhole, and if it is too thick, it takes a long time to form a film, which is not suitable for mass production. Here, it was set to 1000 °.

Thereafter, the silicon oxide film 704 was patterned by a known photolithography process. Then, a nickel film (thickness 500 °) 7 is formed by sputtering.
05 was formed. The thickness of the nickel film was preferably 100 mm or more. (FIG. 7 (A)) and 2
Annealing was performed at 50 to 450 ° C. for 10 to 60 minutes (pre-annealing step). For example, annealing was performed at 450 ° C. for 20 minutes.
As a result, the nickel silicide layer 7 in the amorphous silicon
06 was formed. The thickness of this layer was determined by the pre-annealing temperature and time, and the thickness of the nickel film 705 was hardly involved. (FIG. 7 (B))

Thereafter, the nickel film was etched. A nitric acid or hydrochloric acid solution was suitable for the etching. In these etchants, the nickel silicide layer was hardly etched during the etching of the nickel film. In this embodiment, an etchant obtained by adding acetic acid as a buffer to nitric acid was used. The ratio is nitric acid: acetic acid: water = 1: 1
0:10. After removing the nickel film, 550 ° C.
Annealing was performed for 4 to 8 hours (crystallization annealing step).

Several methods were tried in the crystallization annealing step. The first method is a method in which the mask material 704 is left as shown in FIG. Crystallization proceeds as shown by the arrow in FIG. The second method is to perform annealing by exposing the silicon film by removing all the mask material. Third, after removing the mask material as shown in FIG. 7D, a new film 7 of silicon oxide or silicon nitride is formed.
07 is formed on the surface of the silicon film as a protective film, and then annealing is performed.

The first method is a simple method, but the surface of the mask material 704 reacts with nickel in the pre-annealing step, which becomes a silicate in a higher temperature crystallization annealing step, making etching difficult. . That is, since the etching rates of the silicon film and the mask material 704 become substantially the same, when the mask material is removed later, the exposed portion of the silicon film is also largely etched, and a step is formed on the substrate.

The second method is extremely simple. Before the crystallization annealing step, the reaction between nickel and the mask material is gentle, so that etching is easy. However, since the silicon surface is entirely exposed during the crystallization annealing, the characteristics when a TFT or the like is manufactured later deteriorated.

In the third step, a high-quality crystalline silicon film can be surely obtained, but the number of steps is increased and the third step is complicated. Third
As a fourth improved method of the above method, the silicon surface is put into a furnace with the silicon surface exposed, and the silicon is first heated at 500 to 550 ° C. for 1 hour.
2 hours on the surface by heating in a stream of oxygen
A method of forming a thin silicon oxide film of 0 to 60 °, switching to a nitrogen gas stream as it is, and using it as crystallization annealing conditions was studied. According to this method, an oxide film is formed at an initial stage of crystallization, and in this oxidation stage, only a very close portion of the nickel silicide layer is crystallized. In), crystallization did not occur. Therefore, the surface of the silicon film was extremely flat particularly in a region far from the nickel silicide layer 706. The characteristics are
It was improved over the second method and was almost the same as the third method.

Thus, a crystalline silicon film was obtained. After that, the silicon film 703 was patterned. In this way, the high-concentration nickel portion (the region where the growth origin is present) and the growth point (the hatched portion at the tip of the arrow in the figure) were removed, leaving only the low-nickel-concentration region. Thus, the island-shaped silicon region 708 used for the active layer of the TFT is formed.
Was formed. Then, a gate insulating film 709 of silicon oxide having a thickness of 1200 ° was formed by plasma CVD to cover this. Furthermore, a phosphorus-doped silicon film (thickness 60
00Å), the gate electrode 710 and the first layer wiring 71
1 was formed, and impurities were implanted into the active layer 708 in a self-aligned manner using the gate electrode 710 as a mask to form source / drain regions 712. After that, it is effective to irradiate visible / near infrared strong light to further enhance the crystallinity. Further, a silicon oxide film (thickness: 6000 °) was formed by a plasma CVD method to form an interlayer insulator 713. Finally, a contact hole was formed in the interlayer insulator, and a second layer wiring 714 and a source / drain electrode / wiring 715 were formed by an aluminum film (thickness: 6000 °). Through the above steps, a TFT was completed. (FIG. 7E)

[0053]

As described above, the present invention is epoch-making in that it promotes lowering the temperature and shortening the time of crystallization of amorphous silicon.
Since the equipment and the method are very common and excellent in mass productivity, the profits brought to the industry are insignificant. In the embodiment, description has been made mainly on nickel. However, similar steps are performed for other crystallization promoting metal elements, that is, Fe, Co, Ru, Rh, Pd, Os, Ir, and P.
t, Sc, Ti, V, Cr, Mn, Cu, Zn, Au,
It can be applied to any of Ag.

For example, in the conventional solid-phase growth method, since annealing for at least 24 hours is required,
Assuming that the substrate processing time per substrate is 2 minutes, as many as 15 annealing furnaces were required.
Since the number of annealing furnaces can be reduced to less than 1/6, the number of annealing furnaces can be reduced to 1/6 or less. Improvement in productivity and reduction in capital investment due to this leads to a reduction in substrate processing cost, which in turn leads to a reduction in TFT price and thus a new demand. Thus, the present invention is industrially useful and deserves a patent.

[Brief description of the drawings]

FIG. 1 shows a top view of the steps of an embodiment. (Crystallization and TFT arrangement)

FIG. 2 shows a cross-sectional view of a process of the embodiment. (Step of selective crystallization)

FIG. 3 shows a cross-sectional view of a process of the embodiment. (Example 1
reference)

FIG. 4 shows a cross-sectional view of a process of the embodiment. (Example 1
reference)

FIG. 5 shows a cross-sectional view of the process of the embodiment. (Example 2
reference)

FIG. 6 shows a cross-sectional view of a process in the example. (Example 3
reference)

FIG. 7 shows a cross-sectional view of a step in the example. (Example 4
reference)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Amorphous silicon 2 ... Nickel-shaped nickel film 3 ... Crystal silicon 4 ... Grain boundary 5 ... A region where crystallization has not progressed 6 ... Semiconductor region 7 ... Gate wiring

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kenji Fukunaga 398 Hase, Atsugi-shi, Kanagawa Prefecture Semiconductor Energy Research Institute, Inc. (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi-shi, Kanagawa Semiconductor Energy Research Institute, Inc. (56) References JP-A-62-298151 (JP, A) JP-A-2-140915 (JP, A) JP-A-61-63017 (JP, A) JP-A-5-13442 (JP, A) −166528 (JP, U) JP44-15736 (JP, B1)

Claims (12)

(57) [Claims] A first step of forming a silicon film in a substantially amorphous state on a substrate; a second step of forming a mask film; and patterning the mask film to expose a surface of the silicon film. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver And a fifth step of laterally crystallizing a silicon film adjacent to the exposed portion of the silicon film by annealing the substrate after the fourth step. Manufacturing method of a semiconductor device. 2. A first step of forming a substantially amorphous silicon film on a substrate, a second step of forming a mask film, and patterning the mask film to expose a surface of the silicon film. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver And a fifth step of laterally crystallizing the silicon film adjacent to the exposed portion of the silicon film by annealing the substrate at a temperature of 600 ° C. or less after the fourth step. And a method for manufacturing a semiconductor device. 3. A first step of forming a substantially amorphous silicon film on a substrate, a second step of forming a mask film, and patterning the mask film to expose the silicon film surface. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver And a fifth step of laterally crystallizing a silicon film adjacent to the exposed portion of the silicon film by annealing the substrate after the fourth step. A method for manufacturing a semiconductor device, comprising using a silicon film crystallized in a lateral direction for a semiconductor device. 4. A first step of forming a substantially amorphous silicon film on a substrate, a second step of forming a mask film, and patterning the mask film to expose a surface of the silicon film. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver A fifth step of reacting the element with the silicon film after the fourth step; and a silicon film adjacent to the part of the silicon film reacted with the element by annealing the substrate. And a sixth step of crystallizing the semiconductor device in the lateral direction. 5. A first step of forming a silicon film in a substantially amorphous state on a substrate, a second step of forming a mask film, and patterning the mask film to expose the surface of the silicon film. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver A fourth step of forming a substrate, a fifth step of reacting the element with the silicon film by heat-treating the substrate after the fourth step, and annealing the substrate at a higher temperature than the fifth step. And a sixth step of laterally crystallizing a silicon film adjacent to the silicon film in a portion reacted with the element. The method of manufacturing a semiconductor device. 6. A first step of forming a substantially amorphous silicon film on a substrate, a second step of forming a mask film, and patterning the mask film to expose a surface of the silicon film. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver A fifth step of forming a silicide by reacting the element with the silicon film by heat-treating the substrate after the fourth step; and forming a higher temperature than the fifth step. And a sixth step of laterally crystallizing the silicon film adjacent to the silicide by annealing the substrate in step (c). Method of manufacturing location. 7. A first step of forming a silicon film in a substantially amorphous state on a substrate, a second step of forming a mask film, and patterning the mask film to expose a surface of the silicon film. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver A fifth step of reacting the element with the silicon film by heat-treating the substrate after the fourth step; and a step of heating the substrate at a temperature higher than the fifth step and equal to or lower than 600 ° C. Annealing the silicon film to laterally crystallize the silicon film adjacent to the portion of the silicon film reacted with the element.
And a method of manufacturing a semiconductor device. 8. A first step of forming a substantially amorphous silicon film on a substrate, a second step of forming a mask film, and patterning the mask film to expose a surface of the silicon film. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver A fifth step of reacting the element with the silicon film after the fourth step; and a silicon film adjacent to the part of the silicon film reacted with the element by annealing the substrate. A sixth step of laterally crystallizing the silicon film, wherein the laterally crystallized silicon film is used for a semiconductor device. Semiconductor device manufacturing method. 9. A first step of forming a substantially amorphous silicon film on a substrate, a second step of forming a mask film, and patterning the mask film to expose the silicon film surface. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver A fourth step of forming the following; a fifth step of reacting the element with the silicon film after the fourth step; a sixth step of removing a film containing the element; and annealing the substrate. And a seventh step of laterally crystallizing a portion of the silicon film adjacent to the silicon film that has reacted with the element. Manufacturing method of body device. 10. A first step of forming a substantially amorphous silicon film on a substrate, a second step of forming a mask film, and patterning the mask film to expose a surface of the silicon film. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver A fifth step of reacting the element with the silicon film by heat-treating the substrate after the fourth step, and a sixth step of removing a film containing the element. Annealing the substrate at a temperature higher than that of the fifth step so that the silicon film adjacent to the portion of the silicon film that has reacted with the element is laterally oriented; And a seventh step of crystallizing the semiconductor device. 11. A first step of forming a substantially amorphous silicon film on a substrate, a second step of forming a mask film, and patterning the mask film to expose the silicon film surface. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver A fourth step of forming a silicide by reacting the element with the silicon film by heat-treating the substrate after the fourth step; and removing a film containing the element. A sixth step of annealing the substrate at a higher temperature than the fifth step to laterally crystallize the silicon film adjacent to the silicide. And a seventh step of causing the semiconductor device to be manufactured. 12. A first step of forming a substantially amorphous silicon film on a substrate, a second step of forming a mask film, and patterning the mask film to expose a surface of the silicon film. A third step and a coating containing at least one element of nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver A fifth step of reacting the element with the silicon film by heat-treating the substrate after the fourth step, and a sixth step of removing a film containing the element. Annealing the substrate at a temperature higher than the fifth step and equal to or lower than 600 ° C. so that the silicon film adjacent to the portion of the silicon film that has reacted with the element is removed 7th to crystallize the film horizontally
And a method of manufacturing a semiconductor device.