JP3796097B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an integrated circuit. Specifically, it has a matrix structure, such as a liquid crystal display device or dynamic RAM (DRAM), and a MOS type or MIS (metal-insulator-semiconductor) type field effect element (the above is a MOS type) as a switching element. A matrix device (including an electro-optical display device and a semiconductor memory device), and a driving circuit therefor, or an integrated image sensor The present invention relates to a semiconductor circuit having a driver circuit. In particular, the present invention relates to an apparatus using a thin film semiconductor element such as a thin film semiconductor transistor formed on an insulating surface as a MOS type element, and to an apparatus having a thin film transistor in which an active layer of the thin film transistor is formed of crystalline silicon.
[0002]
[Prior art]
Conventionally, a crystalline silicon semiconductor thin film used for a thin film device such as a thin film insulated gate field effect transistor (TFT) is an amorphous silicon film formed by a plasma CVD method or a thermal CVD method in an apparatus such as an electric furnace. And crystallization at a temperature of 600 ° C. or higher for a long time of 24 hours or longer. In particular, in order to obtain sufficient characteristics (high field effect mobility and high reliability), a longer heat treatment has been required.
[0003]
However, such conventional methods have many problems. One is low throughput and therefore high cost. For example, if this crystallization process requires 24 hours, 720 substrates had to be processed at the same time if the processing time per substrate was 2 minutes. However, for example, in a normally used tubular furnace, the number of substrates that can be processed at one time is 50 at most, and when only one apparatus (reaction tube) is used, it takes 30 minutes per sheet. I have. That is, 15 reaction tubes had to be used in order to reduce the processing time per sheet to 2 minutes. This meant that the scale of the investment increased and that the depreciation of the investment was large and rebounded to the cost of the product.
[0004]
Another problem was the temperature of the heat treatment. In general, a substrate used for manufacturing a TFT is roughly classified into a substrate made of pure silicon oxide such as quartz glass and an alkali-free borosilicate glass such as Corning No. 7059 (hereinafter referred to as Corning 7059). Among these, the former has excellent heat resistance and can be handled in the same way as a normal wafer process of a semiconductor integrated circuit, and therefore has no problem with respect to temperature. However, its cost is high and increases exponentially with an increase in substrate area. Therefore, at present, it is used only for TFT integrated circuits having a relatively small area.
[0005]
On the other hand, the alkali-free glass has a sufficiently low cost compared to quartz, but has a problem in terms of heat resistance, and generally has a strain point of about 550 to 650 ° C., and particularly easily available material is 600 ° C. or less. The heat treatment at 600 ° C. caused problems such as irreversible shrinkage and warping of the substrate. This was particularly noticeable when the substrate was larger than 10 inches diagonal. For the reasons described above, heat treatment conditions of 550 ° C. or less and within 4 hours have been indispensable for cost reduction for crystallization of a silicon semiconductor film. An object of the present invention is to provide a method for manufacturing a semiconductor that satisfies such conditions, and a method for manufacturing a semiconductor device using such a semiconductor.
[0006]
Recently, research has been conducted on an insulating gate type semiconductor device having a thin-film active layer (also referred to as an active region) on an insulating substrate. In particular, thin-film insulated gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are formed on a transparent insulating substrate and used for controlling each pixel and driving the matrix in a display device such as a liquid crystal having a matrix structure, or are also formed on an insulating substrate. It is intended to be used for a drive circuit of an image sensor, and is distinguished as an amorphous silicon TFT or a crystalline silicon (also referred to as polycrystalline silicon) TFT depending on the material and crystal state of a semiconductor to be used.
[0007]
Recently, research has also been conducted on the use of a material that exhibits an intermediate state between crystalline silicon and amorphous. Although the intermediate state has been discussed, in this specification, any crystal can be obtained by some thermal process (for example, thermal annealing at a temperature of 450 ° C. or higher or irradiation with strong energy such as laser light). Everything that has reached the state is called crystalline silicon.
[0008]
Also in a single crystal silicon integrated circuit, a crystalline silicon TFT is used as a so-called SOI technology, and this is used as a load transistor in, for example, a highly integrated SRAM. However, in this case, the amorphous silicon TFT is hardly used.
[0009]
Furthermore, since a semiconductor circuit on an insulating substrate has no capacitive coupling between the substrate and the wiring, it can operate at a very high speed, and a technique for use as an ultra-high-speed microprocessor or an ultra-high-speed memory has been proposed.
[0010]
In general, the electric field mobility of an amorphous semiconductor is small, and therefore it cannot be used for a TFT that requires high-speed operation. In addition, since the P-type field mobility is extremely small in amorphous silicon, a P-channel TFT (PMOS TFT) cannot be manufactured. Therefore, in combination with an N-channel TFT (NMOS TFT), A complementary MOS circuit (CMOS) cannot be formed.
[0011]
However, a TFT formed of an amorphous semiconductor has a feature that the OFF current is small. Therefore, as in the active matrix transistor of a liquid crystal display with a small matrix scale, a high-speed operation is not required, a single conductivity type is sufficient, and a TFT having a high charge retention capability is required. Has been used. However, it has been difficult to use amorphous silicon TFTs for more advanced applications such as large-matrix liquid crystal displays. Of course, it cannot be used for a peripheral circuit of a display or a drive circuit of an image sensor, which requires high speed operation. In addition, although it has a matrix configuration, it is difficult to use it for a semiconductor memory device.
[0012]
On the other hand, a crystalline semiconductor has a higher electric field mobility than an amorphous semiconductor, and thus can operate at high speed. For example, in a TFT using a silicon film recrystallized by laser annealing, the electric field mobility is 300 cm. ² A value of / Vs is obtained. The electric field mobility of a MOS transistor formed on a normal single crystal silicon substrate is 500 cm. ² / Vs is an extremely large value, and the MOS circuit on the single crystal silicon is limited to the operation speed due to the parasitic capacitance between the substrate and the wiring. There are no such restrictions, and remarkable high-speed operation is expected.
[0013]
In addition, in the case of crystalline silicon, not only an NMOS TFT but also a PMOS TFT can be obtained in the same manner, so that a CMOS circuit can be formed. For example, in an active matrix liquid crystal display device, only an active matrix portion can be formed. In addition, those having a so-called monolithic structure in which peripheral circuits (drivers and the like) are also constituted by CMOS crystalline silicon TFTs are known. The TFT used in the above-described SRAM is also paying attention to this point, and the PMOS is constituted by a TFT, which is used as a load transistor.
[0014]
In addition, in a normal amorphous TFT, it is difficult to form a source / drain region by a self-alignment process such as that used in single crystal IC technology, which is due to a geometrical overlap between the gate electrode and the source / drain region. While the parasitic capacitance becomes a problem, the crystalline silicon TFT has a feature that the parasitic capacitance can be remarkably suppressed because a self-alignment process can be adopted.
[0015]
However, the crystalline silicon TFT has a larger leakage current when no voltage is applied to the gate (when it is not selected) than the amorphous silicon TFT, and in order to use it in a liquid crystal display, an auxiliary capacitor for compensating this leakage current. In addition, measures were taken to reduce leakage current by further arranging two TFTs in series.
[0016]
For example, if an amorphous silicon TFT is used to form a peripheral circuit of a polysilicon TFT having high mobility monolithically on the same substrate, amorphous silicon is formed and selective. A method has been proposed in which only a peripheral circuit is crystallized by irradiating a laser beam on the substrate.
[0017]
However, at present, the yield is low due to the reliability problem of the laser irradiation process (for example, the in-plane uniformity of the irradiation energy is poor). After all, the matrix is composed of amorphous silicon TFTs, and the drive circuit is simple. A method of connecting crystal integrated circuits by a TAB method or the like is employed. However, this method requires a pixel pitch of 0.1 mm or more due to physical limitations of connection, and is expensive.
[0018]
Although the present invention is intended to provide an answer to such a difficult problem, it is undesirable for the process to be complicated, resulting in a decrease in yield and an increase in cost. The gist of the present invention is that two types of TFTs, a TFT requiring high mobility and a TFT requiring low leakage current, can be easily manufactured by maintaining minimum productivity by changing the minimum process. There is to divide.
[0019]
Another object of the present invention is to reduce the difference in mobility between NMOS and PMOS in a CMOS circuit. By reducing the difference in mobility between NMOS and PMOS, the degree of freedom in circuit design can be increased.
[0020]
The semiconductor circuit to which the present invention is applied is not universal. In particular, the present invention utilizes materials whose light transmission and reflection properties change due to the effect of an electric field, such as a liquid crystal display device, and sandwiches these materials between opposing electrodes, and applies an electric field between the opposing electrodes. Next, an active matrix circuit for displaying an image, a memory device such as a DRAM that retains memory by accumulating charges in a capacitor, and a MOS structure of a MOS transistor as a capacitor or another capacitor Suitable for a circuit having a dynamic circuit such as a dynamic shift register for driving a stage circuit, and a circuit having a digital circuit such as an image sensor driving circuit and a circuit for controlling an analog signal output. . In particular, the invention is suitable for a circuit in which a dynamic circuit and a static circuit are mixedly mounted.
[0021]
[Means for Solving the Problems]
The present invention can be applied above or below a silicon film in an amorphous state or a messy crystalline state that can be said to be substantially amorphous (for example, a state in which a portion having good crystallinity and an amorphous portion are mixed). Insular films and dots, particles, clusters containing nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, silver, A crystalline silicon film is obtained by forming a line or the like, and annealing the wire at a temperature lower than the crystallization temperature by a simple heat treatment of ordinary amorphous silicon, and for a shorter time. This annealing can be performed in a hydrogen, oxygen or nitrogen atmosphere. In this annealing, (1) heating is performed in an atmosphere containing oxygen for A time, and then heating is performed in an atmosphere containing hydrogen for B time. (2) Heating is performed in an atmosphere containing oxygen for C hours, and then heating is performed in an atmosphere containing nitrogen for D hours. (3) Heating is performed in an atmosphere containing hydrogen for E hours, and then heating is performed in an atmosphere containing oxygen for F hours. (4) Heating is performed in an atmosphere containing hydrogen for G time, and then heating is performed in an atmosphere containing nitrogen for H time. (5) Heating is performed in an atmosphere containing nitrogen for I hours, and then heating is performed in an atmosphere containing oxygen for J hours. (6) Heat in an atmosphere containing nitrogen for K hours, and then heat in an atmosphere containing hydrogen for L hours. (7) Heat in an atmosphere containing oxygen for M hours, then heat in an atmosphere containing hydrogen for N hours, and then heat in an atmosphere containing nitrogen for P hours. (8) Heating is performed in an atmosphere containing oxygen for Q hours, followed by heating in an atmosphere containing nitrogen for R hours, and then heating in an atmosphere containing hydrogen for S hours. (9) Heating is performed in an atmosphere containing hydrogen for T time, then heating is performed in an atmosphere containing oxygen for U time, and then heating is performed in an atmosphere containing nitrogen for V time. (10) Heating is performed in an atmosphere containing hydrogen for W hours, followed by heating in an atmosphere containing nitrogen for X hours, and then heating in an atmosphere containing oxygen for Y hours. (11) Heating is performed in an atmosphere containing nitrogen for Z time, followed by heating in an atmosphere containing oxygen for A ′ time, and then heating in an atmosphere containing hydrogen for B ′ time. Alternatively, (12) heating is performed in an atmosphere containing nitrogen for C ′ time, and then heating is performed in an atmosphere containing hydrogen for D ′ time, and then heating is performed in an atmosphere containing oxygen for E ′ time.
After the annealing, the crystalline silicon film is patterned to form island-shaped crystalline silicon regions, and TFTs, diodes, or resistors can be formed using the island-shaped regions.
[0022]
As for the conventional crystallization of a silicon film, a method (for example, JP-A-1-214110) has been proposed in which a crystalline island-shaped film is used as a nucleus and this is used as a seed crystal for solid phase epitaxial growth. However, in such a method, crystal growth hardly progressed at a temperature of 600 ° C. or lower. In the silicon system, in general, in order to shift from the amorphous state to the crystalline state, the molecular chain in the amorphous state is broken, and the broken molecule is not bonded to other molecules again. It goes through a process of recombining the molecule into a part of the crystal to match some crystalline molecule. However, in this process, the energy for breaking the first molecular chain and maintaining it in a state not bonded to other molecules is large, and this is a barrier in the crystallization reaction. In order to give this energy, it takes several minutes at a temperature of about 1000 ° C., or several tens of hours at a temperature of about 600 ° C., and the time depends exponentially on the temperature (= energy). For example, at 550 ° C., it was hardly observed that the crystallization reaction proceeds. The conventional idea of solid phase epitaxial crystallization also did not give an answer to this problem.
[0023]
The present inventor has considered that the barrier energy of the above-described process is reduced by some kind of catalytic action, completely independent of the conventional idea of solid-phase crystallization. The present inventor is nickel (element symbol Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt). , Scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), copper (Cu), zinc (Zn), gold (Au), silver (Ag) are bonded to silicon. Cheap.
[0024]
For example, in the case of nickel, nickel silicide (chemical formula NiSi _x 0.4 ≦ x ≦ 2.5), and the lattice constant of nickel silicide is close to that of silicon crystal. Therefore, as a result of simulating ternary energy such as crystalline silicon-nickel silicide-amorphous silicon, amorphous silicon reacts easily at the interface with nickel silicide,
Amorphous silicon (silicon A) + nickel silicide (silicon B)
→ Nickel silicide (silicon A) + crystalline silicon (silicon B)
(Silicon A and B indicate the position of silicon)
It became clear that this reaction occurred. The potential barrier for this reaction is sufficiently low and the reaction temperature is low. This reaction equation shows that nickel progresses while transforming amorphous silicon into crystalline silicon. In practice, it was found that the reaction started at 580 ° C. or lower, and that the reaction was observed even at 450 ° C. As a matter of course, the higher the temperature, the faster the reaction proceeds. Similar effects were also observed with the other metal elements shown above.
[0025]
In the present invention, Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, etc., such as islands, stripes, lines, dots, and films, such as nickel, and their silicides are used. Starting from films, particles, clusters, etc. containing at least one of Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au, Ag, these metal elements are accompanied by the above reaction. Expanding the area of crystalline silicon by expanding to the surroundings. Note that oxides are not preferable as materials containing these metal elements. This is because an oxide is a stable compound and cannot start the above reaction.
[0026]
Crystalline silicon spread from a specific location in this way is different from conventional solid phase epitaxial growth, but has a structure similar to a single crystal with good continuity of crystallinity, so that TFT, diode, resistance, etc. This is convenient for use in semiconductor devices. However, when a material containing the above metal that promotes crystallization of nickel or the like uniformly is provided on the substrate, there are innumerable starting points for crystallization, and thus obtaining a film with good crystallinity was difficult.
[0027]
In addition, the amorphous silicon film as a starting material for the crystallization gave better results as the hydrogen concentration was lower. However, since hydrogen is released as the crystallization progresses, the hydrogen concentration in the obtained silicon film is not so clearly correlated with the hydrogen concentration in the amorphous silicon film as the starting material. The hydrogen concentration in the crystalline silicon according to the present invention was typically 0.01 atomic% or more and 5 atomic% or less.
[0028]
In the present invention, Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au, and Ag are used. Generally, these materials are used as semiconductor materials. This is not preferable for silicon. Therefore, it is necessary to remove this, but regarding nickel, nickel silicide that has reached the end of crystallization as a result of the above reaction is easily dissolved in hydrofluoric acid or hydrochloric acid or a diluted solution thereof. Nickel can be reduced from the substrate by treatment with acid. Furthermore, to actively reduce these metal elements, hydrogen chloride, various chloromethanes (CH _Three Cl, CH ₂ Cl ₂ , CHCl _Three ), Various ethane chlorides (C ₂ H _Five Cl, C ₂ H _Four Cl ₂ , C ₂ H _Three Cl _Three , C ₂ H ₂ Cl _Four , C ₂ HCl _Five ) Or various ethylene chloride (C ₂ H _Three Cl, C ₂ H ₂ Cl ₂ , C ₂ HCl _Three ) And the like in an atmosphere containing chlorine. In particular, trichlorethylene (C ₂ HCl _Three ) Is an easy-to-use material. The concentrations of Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au, Ag in the silicon film according to the present invention are typically It was 0.005 atomic% or more and 1 atomic% or less.
[0029]
When the crystalline silicon film produced according to the present invention is used for a semiconductor element such as a TFT, a diode, or a resistor, as is apparent from the above description, the termination of crystallization (this is a crystal started from a plurality of starting points). There is a large grain boundary (discontinuous part of crystallinity) and the concentration of metal elements that promote crystallization, such as nickel, is high. It is not preferable. Therefore, in forming a semiconductor element using the present invention, the pattern of the metal element-containing film that promotes crystallization of nickel or the like, which is the starting point of crystallization, and the pattern of the semiconductor element must be optimized. .
[0030]
In the present invention, there are roughly two methods for patterning a metal element that promotes crystallization. The first method is a method of selectively forming these metal films and the like before forming an amorphous silicon film. The second method is a method of selectively forming these metal films and the like after the amorphous silicon film is formed.
[0031]
In the first method, ordinary photolithography means or lift-off means may be used. The second method is somewhat complicated. In this case, if a metal film for promoting crystallization is formed in close contact with the amorphous silicon film, the metal and amorphous silicon partially react during the film formation to form silicide. Therefore, when patterning is performed after forming a metal film or the like, it is necessary to sufficiently etch such a silicide layer.
[0032]
In the second method, the lift-off method is relatively easy. In this case, an organic material such as a photoresist or an inorganic material such as silicon oxide or silicon nitride may be used as the mask material. The process temperature must be taken into account when selecting the mask material. In addition, since the masking action varies depending on the material, sufficient care must be taken. In particular, a film of silicon oxide, silicon nitride, or the like formed by various CVD methods has many pinholes, and if the film thickness is not sufficient, crystallization may proceed from an unintended portion. In general, after forming a film using these mask materials, patterning is performed to selectively expose the surface of amorphous silicon. Then, a metal film or the like that promotes crystallization is formed.
[0033]
In the present invention, what should be noted is the concentration of the metal element in the silicon film. There is no excuse for the small amount, but more than that, it is important that the amount is always kept constant. That is, if the amount of metal element varies greatly, the degree of crystallization varies greatly from lot to lot at the production site. In particular, when the amount of the metal element is required to be small, it becomes increasingly difficult to reduce the variation in the amount.
[0034]
In the first method, since the selectively formed metal film or the like is covered with the amorphous silicon film, it cannot be taken out later to increase or decrease the amount. In particular, when converted from the amount of metal element required in the present invention, the thickness of the metal film or the like is as small as several to several tens of inches, and it is difficult to form a film with good reproducibility.
[0035]
The same applies to the second method. However, in the second method, a metal film or the like that promotes crystallization is present on the surface, so there is still room for improvement as compared with the first method. That is, a sufficiently thick metal film is formed, and a heat treatment (pre-annealing) is performed at a temperature lower than the annealing temperature before annealing, thereby reacting a part of the amorphous silicon film with the metal film to form a silicide. Thereafter, the metal film that has not reacted is etched. Depending on the type of metal used, Ni, Fe, Co, Ti, and Cr are not problematic because there are etchants with sufficiently high etching rates for the metal film and silicide.
[0036]
In this case, the thickness of the silicide layer to be obtained is determined by the temperature and time of the heat treatment (pre-annealing). The thickness of the metal film is almost irrelevant. For this reason, the amount of a very small amount of metal element introduced into the amorphous silicon film can be controlled.
[0037]
Further, according to the present invention, when the crystalline silicon TFT is crystallized in an atmosphere containing oxygen, hydrogen or nitrogen at a temperature of 450 to 1000 ° C., preferably 500 to 800 ° C., the surface of the semiconductor is made of silicon oxide, silicon nitride or the like. The fact that there is a difference in the degree of crystallization between the case where it is covered and the case where it is not covered by a film (cover film) is used. The atmosphere is an atmosphere containing oxygen, an atmosphere containing hydrogen, an atmosphere containing nitrogen, an atmosphere containing oxygen and hydrogen, an atmosphere containing oxygen and nitrogen, an atmosphere containing hydrogen and nitrogen, or an atmosphere containing oxygen, hydrogen, and nitrogen. is there. In the crystallization, (1) heating is performed in an atmosphere containing oxygen for A time, and then heating is performed in an atmosphere containing hydrogen for B time. (2) Heating is performed in an atmosphere containing oxygen for C hours, and then heating is performed in an atmosphere containing nitrogen for D hours. (3) Heating is performed in an atmosphere containing hydrogen for E hours, and then heating is performed in an atmosphere containing oxygen for F hours. (4) Heating is performed in an atmosphere containing hydrogen for G time, and then heating is performed in an atmosphere containing nitrogen for H time. (5) Heating is performed in an atmosphere containing nitrogen for I hours, and then heating is performed in an atmosphere containing oxygen for J hours. (6) Heat in an atmosphere containing nitrogen for K hours, and then heat in an atmosphere containing hydrogen for L hours. (7) Heat in an atmosphere containing oxygen for M hours, then heat in an atmosphere containing hydrogen for N hours, and then heat in an atmosphere containing nitrogen for P hours. (8) Heating is performed in an atmosphere containing oxygen for Q hours, followed by heating in an atmosphere containing nitrogen for R hours, and then heating in an atmosphere containing hydrogen for S hours. (9) Heating is performed in an atmosphere containing hydrogen for T time, then heating is performed in an atmosphere containing oxygen for U time, and then heating is performed in an atmosphere containing nitrogen for V time. (10) Heating is performed in an atmosphere containing hydrogen for W hours, followed by heating in an atmosphere containing nitrogen for X hours, and then heating in an atmosphere containing oxygen for Y hours. (11) Heating is performed in an atmosphere containing nitrogen for Z time, followed by heating in an atmosphere containing oxygen for A ′ time, and then heating in an atmosphere containing hydrogen for B ′ time. Alternatively, (12) heating is performed in an atmosphere containing nitrogen for C ′ time, and then heating is performed in an atmosphere containing hydrogen for D ′ time, and then heating is performed in an atmosphere containing oxygen for E ′ time. In particular, (4) heating is performed in an atmosphere containing hydrogen for G time, and then heating is performed in an atmosphere containing nitrogen for H time. (5) Heating is performed in an atmosphere containing nitrogen for I time (for example, 4 hours), and then heating is performed in an atmosphere containing oxygen for J time (for example, 1 hour). Alternatively, (6) heating is performed in an atmosphere containing nitrogen for K hours (eg, 4 hours), and then heating is performed in an atmosphere containing hydrogen for L hours (eg, 1 hour). Is preferred. In general, when a cover film is present, the crystallinity is good, and as a natural consequence, a TFT with high mobility can be obtained. Instead, the leakage current generally increases. On the other hand, in the case where there is no cover film, the crystallinity is not good and the amorphous state is obtained depending on the temperature, so that the mobility is low but the leakage current is also low.
[0038]
This characteristic is considered to be governed by the presence or absence of hydrogen, oxygen, or nitrogen in the atmosphere during the thermal crystallization. This crystallization may be performed, for example, by crystallization in nitrogen and then in hydrogen or oxygen. In this way, TFTs having different characteristics can be simultaneously formed on the same substrate in the same process. For example, the former high mobility TFT is used as a matrix drive circuit, and the latter low leakage current TFT is used as a matrix portion TFT. it can.
[0039]
Alternatively, in a CMOS circuit, by not providing a cover film in the NMOS region and by providing a cover film in the PMOS region, the mobility of the NMOS is relatively reduced compared to the mobility of the PMOS. It is possible to almost eliminate the difference.
[0040]
In the present invention, the temperature of thermal crystallization is an important parameter, and the crystallinity of the TFT is determined by this temperature. In general, the temperature of thermal annealing is limited by the substrate and other materials. Regarding the restriction of the substrate material, when silicon or quartz is used as the substrate, thermal annealing at a maximum of 1100 ° C. is possible. However, in the case of Corning 7059 glass, which is a typical alkali-free glass, annealing at a temperature of 650 ° C. or lower is desirable. However, for the reasons described above, in the present invention, in addition to the substrate, the characteristics required for each TFT must be set in consideration. In general, if the annealing temperature is high, TFT crystal growth proceeds, the mobility increases, and the leakage current increases. Therefore, in order to obtain TFTs having different characteristics on the same substrate as in the present invention, the annealing temperature should be 450 to 1000 ° C., preferably 500 to 800 ° C.
[0041]
One example of the present invention uses a polysilicon TFT as a switching transistor in a display portion of an active matrix circuit of an electro-optical device such as a liquid crystal, and does not provide a cover film in the active matrix region when the active layer is crystallized. On the other hand, by providing a cover film in the peripheral circuit region, the former is a low leakage current TFT and the latter is a high mobility TFT.
[0042]
FIG. 8A shows a conceptual diagram of a device having the display circuit portion (active matrix) and its driving circuit (peripheral circuit) as described above. In the figure, a data driver 101 and a gate driver 102 are formed on an insulating substrate 107, and an active matrix 103 having a TFT in the center is formed. These driver and active matrix are connected to a gate line 105 and a data line 106. The display device connected by is shown. The active matrix 103 is an aggregate of pixel cells 104 having NMOS or PMOS TFTs (PMOS in the drawing).
[0043]
For the CMOS circuit in the driver section, the concentration of impurities such as oxygen, nitrogen, and carbon in the active layer is 10 in order to obtain high mobility. ¹⁸ cm ^-3 Or less, preferably 10 ¹⁷ cm ^-3 The following is desired. As a result, for example, the threshold voltage of the TFT is 0.5 to 2 V for NMOS, -0.5 to -3 V for PMOS, and the mobility is 30 to 150 cm for NMOS. ² / Vs, 20-100cm for PMOS ² / Vs.
[0044]
On the other hand, in the active matrix portion, the auxiliary capacitance can be reduced by using a single element having a leakage current of about 1 pA at a drain voltage of 1 V, or a plurality of elements in series, and further, it is not necessary at all. did it.
[0045]
The second example of the present invention relates to a semiconductor memory such as a DRAM. Semiconductor memory devices have already reached speed limits in single crystal ICs. In order to operate at higher speeds, it is necessary to increase the current capacity of the transistor, which not only causes a further increase in current consumption, but also stores memory by storing electric charge in the capacitor. As for the DRAM that performs the operation, there is no other way but to cope with it by increasing the drive voltage because the capacitance of the capacitor cannot be increased any more.
[0046]
The single crystal IC is said to have reached the speed limit because, in part, a large loss is caused by the capacitance of the substrate and the wiring. If an insulator is used for the substrate, it can be driven at a sufficiently high speed without increasing current consumption. For these reasons, an IC having an SOI (semiconductor on insulator) structure has been proposed.
[0047]
Also in the case of DRAM, in the case of the 1Tr / cell structure, the circuit configuration is almost the same as that of the previous liquid crystal display device, and in other DRAMs (for example, 3Tr / cell structure), the active layer is crystallized. In addition, the storage bit portion is not provided with a cover film, and on the other hand, since the drive circuit is required to operate at a sufficiently high speed, as in the liquid crystal display device, by providing a cover film in the region, The former is a low leakage current TFT, and the latter is a high leakage current TFT.
[0048]
Also in such a semiconductor memory device, the basic block configuration is the same as that of FIG. For example, in a DRAM, 101 is a column decoder, 102 is a row decoder, 103 is a storage element section, 104 is a unit storage bit, 105 is a bit line, 106 is a word line, and 107 is an (insulating) substrate.
[0049]
A third application example of the present invention is a drive circuit such as an image sensor. FIG. 8B shows an example of a 1-bit circuit of the image sensor, but the flip-flop circuit 108 and the buffer circuit 109 in the figure are usually configured by CMOS circuits and are applied to the scanning lines at high speed. A high-speed response that can follow the pulse is required. On the other hand, the TFT 110 in the signal output stage serves as a dam that discharges the charge accumulated in the capacitor by the photodiode to the data line by signals from the shift register units 108 and 109.
[0050]
Such a TFT 110 is required to have a low leakage current as well as a high-speed response. Therefore, in such a circuit, the TFT region of the circuits 108 and 109 is provided with a cover film and crystallized to obtain a high mobility TFT. In one TFT 110, the cover film is not provided in that region. By performing crystallization, a low leakage current TFT is obtained.
[0051]
In the present invention, as the cover film, silicon oxide, silicon nitride, or silicon oxynitride (SiN _x O _y ) Can be used. The thicker the cover film, the better the covering ability. However, since it takes time to form a thick film, the thickness must be determined in consideration of mass productivity and covering ability. Although the cover ability varies depending on the film quality, typically, the silicon oxide film needs to be 20 nm or more, and the silicon nitride film needs 10 nm or more. In consideration of mass productivity and reliability, 20 to 200 nm is appropriate for both.
[0052]
【Example】
[Example 1] In this example, a plurality of island-shaped nickel films on a Corning 7059 glass substrate are formed, and an amorphous silicon film is crystallized using these as starting points, and the obtained crystalline silicon film is used. A method for manufacturing a TFT will be described. There are two methods for forming an island-shaped nickel film in that it is provided on an amorphous silicon film or below. FIG. 2A-1 shows a method provided below, and FIG. 2A-2 shows a method provided above. In particular, it is necessary to pay attention to the latter, since nickel is formed on the entire surface of the amorphous silicon film and then selectively etched, so that nickel and amorphous silicon react with each other in a small amount. Nickel is formed. If this is left as it is, a good crystalline silicon film as intended by the present invention cannot be obtained. Therefore, it is required to sufficiently remove this nickel silicide with hydrochloric acid, hydrofluoric acid or the like. . For this reason, the amorphous silicon becomes thinner than the initial stage.
[0053]
On the other hand, such a problem does not occur in the former, but in this case as well, it is desirable that the nickel film other than the island-like portion 2 is completely removed by etching. Furthermore, in order to suppress the influence of residual nickel, the substrate may be treated with oxygen plasma, ozone, or the like to oxidize nickel other than the island regions.
[0054]
In either case, an underlying silicon oxide film 1B having a thickness of 2000 mm was formed on the substrate (Corning 7059) 1A by plasma CVD. The amorphous silicon film 1 has a thickness of 200 to 3000 mm, preferably 500 to 1500 mm, and was formed by plasma CVD or low pressure CVD. The amorphous silicon film was easy to be crystallized when hydrogen was extracted by annealing at 350 to 450 ° C. for 0.1 to 2 hours and the hydrogen concentration in the film was kept at 5 atomic% or less. In the case of FIG. 2A-1, a nickel film is deposited to a thickness of 50 to 1000 mm, preferably 100 to 500 mm, by sputtering before the amorphous silicon film 1 is formed, and is patterned to form island-shaped nickel regions. 2 was formed.
[0055]
On the other hand, in the case of FIG. 2 (A-2), after the amorphous silicon film 1 is formed, a nickel film is deposited by sputtering to a thickness of 50 to 1000 mm, preferably 100 to 500 mm, and this is patterned to form island-shaped nickel. Region 2 was formed. FIG. 1A shows a drawing of this state as viewed from above.
[0056]
The island-like nickel was a square with a side of 2 μm, and the interval was 5 to 50 μm, for example 20 μm. A similar effect can be obtained by using nickel silicide instead of nickel. In addition, when the nickel film was formed, good results were obtained by heating the substrate to 100 to 500 ° C., preferably 180 to 250 ° C. This is because the adhesion between the underlying silicon oxide film and the nickel film is improved, and the silicon oxide and nickel react to produce nickel silicide. Similar effects can be obtained by using silicon nitride, silicon carbide, or silicon instead of silicon oxide.
[0057]
Next, this was annealed in a nitrogen atmosphere at 450 to 580 ° C., for example, 550 ° C. for 8 hours. This annealing may be performed in a mixed atmosphere of nitrogen and hydrogen. In addition, this annealing is performed by X ₁ Perform in a hydrogen atmosphere for hours, then X ₂ You may carry out in nitrogen atmosphere for the time. FIG. 2B shows an intermediate state in which nickel proceeds from the island-like nickel film at the end in FIG. 2A to the central portion as nickel silicide 3A, and the portion 3 through which nickel has passed. Is crystalline silicon. Eventually, as shown in FIG. 2C, crystallization starting from two island-like nickel films collides, leaving nickel silicide 3A in the middle, and crystallization is completed.
[0058]
FIG. 1B shows a state in which the substrate in this state is viewed from above, and the nickel silicide 3 </ b> A in FIG. 2C is a grain boundary 4. If the annealing is further continued, the nickel moves along the grain boundaries 4 and collects in an intermediate region 5 of these island-like nickel regions (although the original shape is not retained at this stage).
[0059]
Crystalline silicon can be obtained by the above steps, but it is not preferable that nickel is diffused into the semiconductor film from the nickel silicide 3A generated at this time. Therefore, it is desired to etch away high concentration regions where nickel is concentrated with hydrofluoric acid or hydrochloric acid. Note that etching with hydrofluoric acid and hydrochloric acid does not affect the silicon film because the etching rates of nickel and nickel silicide are sufficiently high. At the same time, the region where the nickel growth point was present was also removed. The state after etching is shown in FIG. The portion where the grain boundary exists is the groove 4A. It is not preferable to form a semiconductor region (active layer or the like) of the TFT so as to sandwich this groove. An example of the TFT arrangement is shown in FIG. 1C. The semiconductor region 6 is arranged so as not to cross the grain boundary 4. That is, the right and left sides of the nickel are not formed in the thickness direction of the film, but are formed in the lateral crystal growth region in the direction parallel to the substrate. Then, the crystal growth direction is uniform, and the residual nickel can be extremely reduced. As a result, high TFT characteristics can be obtained. On the other hand, the gate wiring 7 may cross the grain boundary 4.
[0060]
An example of manufacturing a TFT using crystalline silicon obtained through the above steps is shown in FIGS. In FIG. 3A, X in the center means the place where the groove 4A in FIG. 2 was present. As shown in the drawing, the portion X is arranged so that the semiconductor region of the TFT does not cross. That is, the crystalline silicon film 3 obtained in the step shown in FIG. 2 was patterned to form island-like semiconductor regions 11a and 11b. Then, a silicon oxide film 12 functioning as a gate insulating film was formed by a method such as an RF plasma CVD method, an ECR plasma CVD method, or a sputtering method.
[0061]
Further, phosphorus is 1 × 10 5 by low pressure CVD. ²⁰ ~ 5x10 ²⁰ cm ^-3 A doped polycrystalline silicon film having a thickness of 3000 to 6000 mm was formed and patterned to form gate electrodes 13a and 13b. (Fig. 3 (A))
[0062]
Next, impurity doping was performed by a plasma doping method. As a doping gas, for example, phosphine (PH _Three ), Diborane (B ₂ H ₆ ) Was used. In the figure, an N-type TFT is shown. The acceleration voltage was 80 keV for phosphine and 65 keV for diborane. Further, annealing was performed at 550 ° C. for 4 hours to activate the impurities and form impurity regions 14a to 14d. For activation, a method using light energy such as laser annealing or flash lamp annealing can also be used. (Fig. 3 (B))
[0063]
Finally, a silicon oxide film having a thickness of 5000 mm is deposited as an interlayer insulator 15 in the same manner as in the normal TFT fabrication, and contact holes are formed in the silicon oxide film to form wiring / electrodes 16a to 16d in the source region and the drain region. . (Figure 3 (C))
A TFT (N-channel type in the figure) was manufactured through the above steps. The field effect mobility of the obtained TFT is 40-60 cm in the N channel type. ² / Vs, P channel type, 30-50cm ² / Vs.
[0064]
FIG. 4 shows a case where an aluminum gate TFT is manufactured. In FIG. 4A, X in the center means the place where the groove 4A in FIG. 2 was present. As shown in the drawing, the portion X is arranged so that the semiconductor region of the TFT does not cross. That is, the crystalline silicon film 3 obtained in the step shown in FIG. 2 was patterned to form island-like semiconductor regions 21a and 21b. Then, a silicon oxide film 22 functioning as a gate insulating film was formed by a method such as an RF plasma CVD method, an ECR plasma CVD method, or a sputtering method. When the plasma CVD method is employed, TEOS (tetra-ethoxy silane) and oxygen are preferably used as the source gas. Then, an aluminum film (thickness 5000 mm) containing 1% silicon was deposited by sputtering, and this was patterned to form gate wiring / electrodes 23a and 23b.
[0065]
Next, the substrate was immersed in an ethylene glycol solution of 3% tartaric acid, and platinum was used as a cathode, an aluminum wiring was used as an anode, and an electric current was passed through this to perform anodization. At first, the current is applied so that the voltage increases at 2 V / min. When the voltage reaches 220 V, the voltage is constant, and the current is 10 μA / m. ² The current was stopped when: As a result, anodic oxides 24a and 24b having a thickness of 2000 mm were formed. (Fig. 4 (A))
[0066]
Next, impurity doping was performed by a plasma doping method. As a doping gas, N-type phosphine (PH _Three ), Diborane (B ₂ H ₆ ) Was used. The figure shows an N-channel TFT. The acceleration voltage was 80 keV for phosphine and 65 keV for diborane. Furthermore, this was laser-annealed to activate the impurities and form impurity regions 25a to 25d. The laser used was a KrF laser (wavelength 248 nm), 250 to 300 mJ / cm. ² A laser beam having an energy density of 5 shots was irradiated. (Fig. 4 (B))
[0067]
Finally, a silicon oxide film having a thickness of 5000 mm is deposited as an interlayer insulator 26 in the same manner as in the normal TFT fabrication, and contact holes are formed in the silicon oxide film to form wiring / electrodes 27a to 27d in the source region and the drain region. . (Fig. 4 (C))
The field effect mobility of the obtained TFT is N-channel type and 60 to 120 cm. ² / Vs, P-channel type, 50-90cm ² / Vs. In addition, it was confirmed that a shift register manufactured using this TFT operates at 6 MHz at a drain voltage of 17 V and at 11 MHz at 20 V.
[0068]
Example 2 FIG. 5 shows a case where an aluminum gate TFT is manufactured as in FIG. Here, however, amorphous silicon was used as the active layer. As shown in FIG. 5A, a base silicon oxide film 32 was deposited on a substrate 31, and an amorphous silicon film 33 having a thickness of 2000 to 3000 mm was further deposited. An appropriate amount of P-type or N-type impurities may be mixed in the amorphous silicon film. Then, as shown above, island-like nickel or nickel silicide coatings 34A and 34B are formed, and in this state, the amorphous silicon film is crystallized by lateral growth by annealing at 550 ° C. for 8 hours or 600 ° C. for 4 hours. I let you.
[0069]
Next, the crystalline silicon film thus obtained was patterned as shown in FIG. At this time, since the silicon film in the central part (intermediate part of the nickel or nickel silicide coatings 34A, 34B) contains a large amount of nickel, patterning is performed so as to remove the silicon film 35A, 35B was formed. Further, a substantially intrinsic amorphous silicon film 36 was deposited thereon.
Thereafter, as shown in FIG. 5C, a film is formed of a material such as silicon nitride or silicon oxide as the gate insulating film 37, the gate electrode 38 is formed of aluminum, and anodic oxidation is performed as in FIG. Impurity regions 39A and 39B are formed by diffusing impurities by ion doping. Further, an interlayer insulator 40 is deposited, contact holes are formed, and metal electrodes 41A and 41B are formed on the source and drain to complete the TFT. This TFT is characterized in that the semiconductor film in the source and drain portions is thicker and the resistivity is lower than the thickness of the active layer. As a result, the resistance in the source and drain regions is reduced, and the TFT characteristics are reduced. Will improve. Further, the contact can be easily formed.
[0070]
Example 3 FIG. 6 shows a case where a CMOS type TFT is manufactured. As shown in FIG. 6A, a base silicon oxide film 52 was deposited on a substrate 51, and an amorphous silicon film 53 having a thickness of 1000 to 1500 mm was further deposited. Then, an island-like nickel or nickel silicide coating 54 is formed as described above, and annealing is performed at 550 ° C. in this state. By this step, the silicon silicide region 55 moves in the plane direction, not in the thickness direction of the film, and crystallization proceeds. By annealing for 4 hours, the amorphous silicon film is changed to crystalline silicon as shown in FIG. Further, the silicon silicide 59A and 59B are driven to the end by the progress of crystallization.
[0071]
Next, the crystalline silicon film thus obtained was patterned as shown in FIG. 6B to form island-like silicon regions 56. At this time, it should be noted that the nickel concentration is high at both ends of the island region. After forming the island-like silicon region, a gate insulating film 57 and gate electrodes 58A and 58B were formed.
[0072]
Thereafter, as shown in FIG. 5C, impurities are diffused by ion doping to form an N-type impurity region 60A and a P-type impurity region 60B. In this case, for example, phosphorus as an N-type impurity (doping gas is phosphine PH). _Three Then, the entire surface is doped with an acceleration voltage of 60 to 110 kV, and then the region of the N-channel TFT is covered with a photoresist to form a P-type impurity such as boron (the doping gas is diborane B). ₂ H ₆ ) And doping at an acceleration voltage of 40 to 80 kV.
[0073]
After the doping is completed, the source and drain are activated by laser light irradiation as in the case of FIG. 4, and further, the interlayer insulator 61 is deposited, contact holes are formed, and the metal electrodes 62A, 62B, and 62C are formed. A TFT is completed by forming the source and drain.
[0074]
Example 4 FIG. 7 shows this example. In this example, a part of the nickel film and the amorphous silicon film are reacted by an initial heat treatment (pre-annealing) to obtain a silicide, and after further removing the unreacted nickel film, annealing is performed for crystallization. It is about the method to make it.
[0075]
A base silicon oxide film (thickness: 2000 mm) was formed on a substrate (Corning 7059) 701 by sputtering. Then, a silicon film 703 having a thickness of 300 to 800 mm, for example, 500 mm was formed by plasma CVD. Further, a silicon oxide film 704 was formed by a plasma CVD method. This silicon oxide film 704 serves as a mask material. The thickness was preferably 500 to 2000 mm. If it is too thin, crystallization proceeds from an unintended location by a pinhole, and if it is too thick, it takes time to form a film and is not suitable for mass production. Here, it was 1000 mm.
[0076]
Thereafter, the silicon oxide film 704 was patterned by a known photolithography process. A nickel film (thickness 500 mm) 705 was formed by sputtering. The thickness of the nickel film was preferably 100 mm or more. (Fig. 7 (A))
And it annealed for 10 to 60 minutes at 250-450 degreeC in nitrogen atmosphere (pre-annealing process). For example, annealing was performed at 450 ° C. for 20 minutes. As a result, a nickel silicide layer 706 was formed in the amorphous silicon. The thickness of this layer was determined by the pre-annealing temperature and time, and the thickness of the nickel film 705 was hardly involved. (Fig. 7 (B))
[0077]
Thereafter, the nickel film was etched. A nitric acid or hydrochloric acid solution was suitable for etching. In these etchants, the nickel silicide layer was hardly etched during the etching of the nickel film. In this example, an etchant obtained by adding acetic acid as a buffer to nitric acid was used. The ratio was nitric acid: acetic acid: water = 1: 10: 10. After removing the nickel film, annealing was performed at 550 ° C. for 4 to 8 hours (crystallization annealing step).
[0078]
Several methods were tried in the crystallization annealing process. The first method is a method in which the mask material 704 is left as shown in FIG. Crystallization proceeds as shown by the arrow in FIG. The second is a method of removing the mask material and exposing the silicon film to perform annealing. The third method is a method in which after the mask material is removed as shown in FIG. 7D, a new silicon oxide or silicon nitride film 707 is formed on the silicon film surface as a protective film, and then annealing is performed.
[0079]
The first method is a simple method, but the surface of the mask material 704 reacts with nickel in the pre-annealing stage, and this becomes silicate in a higher temperature crystallization annealing process, which makes etching difficult. That is, since the etching rates of the silicon film and the mask material 704 are approximately the same, when the mask material is removed later, the exposed portion of the silicon film is greatly etched, and a step is generated on the substrate.
[0080]
The second method is very simple, and before the crystallization annealing step, the reaction between nickel and the mask material is gentle, so that etching is easy. However, since the silicon surface is completely exposed during the crystallization annealing, the characteristics when a TFT or the like is manufactured later deteriorated.
[0081]
In the third step, a high-quality crystalline silicon film can be obtained with certainty, but the number of steps is complicated and complicated. As a fourth method improved from the third method, the surface of silicon is exposed to a furnace, and first heated at 500 to 550 ° C. for about 1 hour in an oxygen stream to reach a surface of 20 to 60 mm. A method of forming a thin silicon oxide film and switching to a nitrogen stream as it is to obtain crystallization annealing conditions was studied. In this method, an oxide film is formed at the initial stage of crystallization, and only the very vicinity of the nickel silicide layer is crystallized at this oxidation stage. ) Did not cause crystallization. For this reason, the surface of the silicon film was very flat especially in a region far from the nickel silicide layer 706. The characteristics were improved over those of the second method and were almost the same as those of the third method.
[0082]
A crystalline silicon film was thus obtained. Thereafter, the silicon film 703 was patterned. Thus, the high concentration value portion of nickel (region with the growth source) and the growth point (shaded portion at the tip of the arrow in the figure) were removed, leaving only the low concentration region of nickel. Thus, an island-shaped silicon region 708 used for the active layer of the TFT was formed. Then, a silicon oxide gate insulating film 709 having a thickness of 1200 mm was formed by plasma CVD. Further, a gate electrode 710 and a first layer wiring 711 are formed by using a phosphorus-doped silicon film (thickness: 6000 mm), and impurities are implanted into the active layer 708 in a self-aligning manner using the gate electrode 710 as a mask. Formed. Thereafter, it is effective to irradiate strong visible / near infrared light to further enhance crystallinity. Further, a silicon oxide film (thickness: 6000 mm) was formed by a plasma CVD method to form an interlayer insulator 713. Finally, a contact hole was formed in the interlayer insulator, and a second layer wiring 714 and source / drain electrodes / wiring 715 were formed by an aluminum film (thickness: 6000 mm). The TFT was completed through the above steps. (Fig. 7 (E))
[0083]
Embodiment 5 FIG. 9 shows this embodiment. In this embodiment, polysilicon TFTs are formed in the peripheral circuit and active matrix region of the TFT type liquid crystal electro-optical display device.
[0084]
First, a base oxide film 121 with a thickness of 20 to 200 nm was deposited on a heat-resistant glass substrate 120 such as a quartz substrate by a sputtering method. Further, an amorphous silicon film having a thickness of 30 to 50 nm was deposited thereon by plasma CVD or low pressure CVD using monosilane or disilane as a raw material. At this time, the concentration of oxygen and nitrogen in the amorphous silicon film is 10 ¹⁸ cm ^-2 Or less, preferably 10 ¹⁷ cm ^-2 The following. The low pressure CVD method is suitable for this purpose. In this embodiment, the oxygen concentration is 10 ¹⁷ cm ^-2 It was as follows. A silicon oxide film (thickness 100 to 150 nm) or a silicon nitride film (30 to 100 nm) as a cover film is again formed on the amorphous silicon film by sputtering, and this is patterned to cover only the peripheral circuit region. The membrane 122 was left behind. Then, it was allowed to crystallize for 4 to 100 hours in an argon or nitrogen atmosphere (600 ° C.) containing 20 to 100% by volume of oxygen or hydrogen. As a result, the silicon film 123A in the peripheral circuit region has good crystallinity, and the silicon film 123B in the pixel region has poor crystallinity. This is shown in FIG.
[0085]
Thereafter, as shown in FIG. 9B, the silicon film was patterned into an island shape to form a peripheral circuit TFT region 124A and a pixel TFT region 124B. Then, a gate oxide film 125 was formed by means such as sputtering. Instead of sputtering, TEOS (tetra ethoxy silane) or the like may be used to form a film by plasma CVD. For film formation using TEOS, it is desirable to anneal at a temperature of 650 ° C. or higher for 0.5 to 3 hours at the time of film formation or after film formation.
[0086]
Thereafter, an N-type silicon film having a thickness of 200 nm to 2 μm was formed by LPCVD and patterned to form gate electrodes 126A to 126C in each island region. Instead of the N-type silicon film, a metal material having relatively good heat resistance such as tantalum, chromium, titanium, tungsten, molybdenum, etc. may be used.
[0087]
Thereafter, by ion doping, impurities were implanted into the island-like silicon film of each TFT in a self-aligned manner using the gate electrode portion as a mask. At this time, the phosphine (PH _Three ) Is doped as a doping gas, and then the right side of the island-like region 124A and the matrix region are covered with a photoresist, and diborane (B ₂ H ₆ ) As a doping gas, boron was implanted into the left side of the island region 124A. Dose amount is 2-8x10 for phosphorus ¹⁵ cm ^-2 Boron is 4-10 × 10 ¹⁵ cm ^-2 The boron dose was set to exceed that of phosphorus. In this way, P-type region 127A and N-type regions 127B and 127C were formed.
[0088]
Furthermore, activation was performed by annealing at 550 to 750 ° C. for 2 to 24 hours. In this example, thermal annealing was performed at 600 ° C. for 24 hours. By this annealing step, the ion implanted region could be activated.
[0089]
This step can also be performed by laser annealing. In particular, when laser annealing is performed, thermal damage to the substrate is small, so that it is possible to use a normal alkali-free glass such as Corning 7059. In this case, a material having poor heat resistance such as aluminum can be used as the gate electrode material. Through the above steps, a P-type region 127A and N-type regions 127B and 127C are formed. The sheet resistance in these regions was 200 to 800 Ω / □.
[0090]
After that, as shown in FIG. 9C, a silicon oxide film having a thickness of 300 to 1000 nm was formed as an interlayer insulator 128 over the entire surface by sputtering. This may be a silicon oxide film formed by plasma CVD. In particular, a silicon oxide film with good step coverage can be obtained by the plasma CVD method using TEOS as a raw material.
[0091]
Thereafter, as the pixel electrode 129, an ITO film was formed by sputtering and patterned. Then, contact holes were formed in the source / drain (impurity region) of the TFT, and wirings 130A to 130E of chromium or titanium nitride were formed. FIG. 9C shows that an inverter circuit is formed of the left NTFT and PTFT. The wirings 130A to 130E may be multilayer wirings with aluminum having chromium or titanium nitride as a base for lowering sheet resistance. Finally, annealing was performed in hydrogen at 200 to 350 ° C. for 0.5 to 2 hours to reduce dangling bonds in the silicon active layer. Through the above steps, the peripheral circuit and the active matrix circuit can be integrally formed. In this embodiment, the typical mobility is 80 cm for the NMOS in the peripheral circuit section. ² / Vs, PMOS 50cm ² / Vs, pixel TFT (NMOS) 5-30cm ² / Vs.
[0092]
[Embodiment 6] FIG. 10 shows this embodiment. This embodiment uses the present invention in a CMOS circuit to reduce the difference in mobility between NMOS and PMOS. First, a base oxide film 132 having a thickness of 20 to 200 nm was deposited on a Corning 7059 substrate 131 by sputtering. Further, an amorphous silicon film having a thickness of 50 to 250 nm was deposited thereon by plasma CVD or low pressure CVD using monosilane or disilane as a raw material. At this time, the concentration of oxygen and nitrogen in the amorphous silicon film is 10 ¹⁸ cm ^-2 Or less, preferably 10 ¹⁷ cm ^-2 The following. The low pressure CVD method is suitable for this purpose. In this embodiment, the oxygen concentration is 10 ¹⁷ cm ^-2 It was as follows.
[0093]
A cover film 133 (silicon oxide film, thickness 50 to 150 nm) was provided only in the PMOS region. Then, annealing was performed at 600 ° C. for 4 to 100 hours in an atmosphere of argon or nitrogen containing 50% or more of oxygen or hydrogen for crystallization. As a result, the region 134A under the cover film had good crystallinity, but the region 134B without the cover film had poor crystallinity. This state is shown in FIG.
[0094]
Thereafter, these Si films were patterned into island shapes to form a PMOS region 135A and an NMOS region 135B as shown in FIG. Further, a silicon oxide film (thickness 50 to 150 nm) was formed by sputtering to cover these island regions, and this was used as a gate insulating film 136. Thereafter, an aluminum film having a thickness of 200 nm to 2 μm was formed by a sputtering method, patterned, and further energized in an electrolytic solution to form an anodic oxide film on the upper and side surfaces of the film. Gate electrode portions 137A and 137B were formed in each island-like region by the above process.
[0095]
Thereafter, by ion doping, impurities were implanted into the island-like silicon film of each TFT in a self-aligned manner using the gate electrode portion as a mask. At this time, the phosphine (PH _Three ) As a doping gas, and then only the island-shaped region 135B in the figure is covered with a photoresist, and diborane (B ₂ H ₆ ) As a doping gas, boron was implanted into the island-shaped region 135A. Dose amount is 2-8x10 for phosphorus ¹⁵ cm ^-2 Boron is 4-10 × 10 ¹⁵ cm ^-2 The boron dose was set to exceed that of phosphorus.
[0096]
Although the crystallinity of the silicon film is destroyed by the doping process, the sheet resistance can be about 1 kΩ / □. However, if this level of sheet resistance is too large, the sheet resistance can be further reduced by annealing at 600 ° C. for 2 to 24 hours. The same effect can be obtained by irradiating intense light such as laser light.
[0097]
Through the above steps, a P-type region 138A and an N-type region 138B were formed. The sheet resistance in these regions was 200 to 800 Ω / □. Thereafter, a silicon oxide film having a thickness of 300 to 1000 nm was formed as an interlayer insulator 139 over the entire surface by sputtering. This may be a silicon oxide film formed by plasma CVD. In particular, a silicon oxide film with good step coverage can be obtained by the plasma CVD method using TEOS as a raw material.
[0098]
Thereafter, contact holes were formed in the source / drain (impurity region) of the TFT, and aluminum wirings 140A to 140D were formed. Finally, annealing was performed in hydrogen at 250 to 350 ° C. for 2 hours to reduce dangling bonds in the silicon film. Typical mobility of TFT obtained by the above process is 60cm for both PMOS and NMOS. ² / Vs. Further, when a shift register was manufactured using the steps of this example, an operation of 10 MHz or more was confirmed at a drain voltage of 20V.
[0099]
In Example 6, only the PMOS was covered with the cover film, and the NMOS was not covered with the cover film, and heat crystallization was performed in a hydrogen, oxygen or nitrogen atmosphere. On the contrary, only the NMOS may be covered with a cover film, and heat crystallization may be performed in a hydrogen, oxygen or nitrogen atmosphere without covering the PMOS with a cover film. As a result, an NMOS capable of operating at a higher speed and a PMOS having a lower leakage current can be obtained.
[0100]
Example 7 FIG. 11 shows this example. The present embodiment relates to a circuit combining a transistor and a silicon resistor. Impurity-doped silicon can be used as a transistor protection circuit. First, a base oxide film 141 was deposited to a thickness of 20 to 200 nm on a Corning 7059 substrate 140 by sputtering. Furthermore, an amorphous silicon film 142 was deposited to a thickness of 100 to 250 nm by plasma CVD or low pressure CVD using monosilane or disilane as a raw material. At this time, the concentration of oxygen and nitrogen in the amorphous silicon film is 10 ¹⁸ cm ^-2 Or less, preferably 10 ¹⁷ cm ^-2 The following.
[0101]
Further, a protective film 143 (thickness 20 to 200 nm) made of silicon oxide was deposited and annealed at 600 ° C. for 4 to 100 hours in an atmosphere of argon or nitrogen to be crystallized. This is shown in FIG.
[0102]
After that, these Si films were patterned in an island shape to form a transistor region 144A and a resistance region 144B as shown in FIG. Further, a silicon oxide film (thickness 50 to 150 nm) was formed by sputtering to cover these island regions, and this was used as a gate insulating film 145. Thereafter, an aluminum film having a thickness of 200 nm to 2 μm was formed by a sputtering method, patterned, and further energized in an electrolytic solution to form an anodic oxide film on the upper and side surfaces of the film. Through the above steps, the gate electrode portion 146 was formed in each island region.
[0103]
Thereafter, an impurity such as phosphorus was implanted into the island-like silicon film of each TFT in a self-aligned manner using the gate electrode portion as a mask by ion doping. Dose amount is 2-8x10 for phosphorus ¹⁵ cm ^-2 It was.
[0104]
Impurity regions 147A and 147B were formed by the above doping process. Since these two impurity regions are implanted with the same amount of impurities, they exhibit the same resistivity when subjected to thermal annealing. However, for example, the former always requires a low resistance, while the latter sometimes requires a high resistance. Therefore, as shown in FIG. 11C, a cover film 148 (silicon oxide film, thickness of 50 to 150 nm) is formed only in the transistor region. And it annealed at 550-650 degreeC for 4 to 20 hours in argon or nitrogen atmosphere containing 50 volume% or more of oxygen or hydrogen. Phosphine (PH) instead of oxygen and hydrogen _Three ) May be used. However, in this case, if the annealing temperature is too high, the phosphine is thermally decomposed and diffused into the semiconductor, which lowers the resistivity. Therefore, it is desirable that the annealing temperature be 800 ° C. or lower. Further, when the impurity region of the resistor is P-type, diborane (B ₂ H ₆ ) May be used.
[0105]
Through the above steps, the sheet resistance of the impurity region 147A of the transistor was 200 to 800 Ω / □, while the impurity region 147B of the resistor was 2 k to 100 kΩ / □. Thereafter, a silicon oxide film having a thickness of 300 to 1000 nm was formed as an interlayer insulator 149 over the entire surface by sputtering. This may be a silicon oxide film formed by plasma CVD. In particular, a silicon oxide film with good step coverage can be obtained by the plasma CVD method using TEOS as a raw material.
[0106]
Thereafter, contact holes were formed in the source / drain (impurity region) of the TFT, and aluminum wirings 150A to 150C were formed. Finally, annealing was performed in hydrogen at 250 to 350 ° C. for 0.5 to 2 hours to reduce dangling bonds in the silicon film. Through the above steps, the sheet resistance of the region where the same impurity is implanted with the same thickness can be made different.
[0107]
【The invention's effect】
As described above, the present invention is epoch-making in the sense of promoting the low temperature and short time of crystallization of amorphous silicon, and the equipment, apparatus, and technique for that purpose are very general, And because it is excellent in mass productivity, the benefits to the industry are immense. In the examples, description has been made centering on nickel. However, the same process can be applied to other crystallization promoting metal elements, that is, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, It can be applied to any of Cr, Mn, Cu, Zn, Au, and Ag.
[0108]
For example, in the conventional solid phase growth method, since annealing for at least 24 hours is required, if the substrate processing time per one is 2 minutes, 15 annealing furnaces are required. According to the present invention, the number of annealing furnaces can be reduced to 1/6 or less because it can be shortened within 4 hours. The improvement in productivity and the reduction in capital investment due to this result in a decrease in substrate processing cost, and in turn, a decrease in TFT price and arousing new demand. Thus, the present invention is industrially beneficial and is worthy of being patented.
In addition, the present invention solves the problem in the conventional process for manufacturing a crystalline silicon TFT by minimizing the crystallization condition of the active layer of the TFT, with or without a cover film.
[0109]
The invention has made it possible to increase the reliability and performance of particularly dynamic circuits and devices having such circuits. Conventionally, crystalline silicon TFTs have a low ON / OFF ratio for various purposes such as an active matrix of a liquid crystal display device, and there have been various difficulties in practical use. It seems that it was solved. Although not shown in the embodiments, it will be apparent that the present invention can be effectively applied to a TFT used as a means for three-dimensionalization of a single crystal semiconductor integrated circuit.
[0110]
For example, the peripheral logic circuit may be formed of a semiconductor circuit over a single crystal semiconductor, and a TFT may be provided thereon via an interlayer insulator, thereby forming a memory element portion. In this case, the memory element portion is a DRAM circuit using the TFT of the present invention, and its drive circuit is configured as a single crystal semiconductor circuit in CMOS. In addition, when such a circuit is used for a microprocessor, the memory section is raised to the second floor, so that the area can be saved. Thus, the present invention is considered to be an extremely useful invention in industry.
[Brief description of the drawings]
FIG. 1 shows a top view of steps of an embodiment. (Crystallization and TFT arrangement)
FIG. 2 shows a cross-sectional view of the steps of the example. (Selective crystallization process)
FIG. 3 shows a cross-sectional view of the steps of the example. (See Example 1)
FIG. 4 shows a cross-sectional view of the steps of the example. (See Example 1)
FIG. 5 shows a cross-sectional view of the steps of the example. (See Example 2)
FIG. 6 shows a cross-sectional view of the steps of the example. (See Example 3)
FIG. 7 shows a cross-sectional view of the steps of the example. (See Example 4)
FIG. 8A is a block diagram when the present invention is applied to an active matrix device. (B) A circuit example when the present invention is applied to a drive circuit of an image sensor is shown.
FIG. 9 shows a process of the example.
FIG. 10 shows a process of the example.
FIG. 11 shows a process of the example.
[Explanation of symbols]

Claims (9)

Forming a non-single-crystal semiconductor film containing silicon on the substrate;
Selectively forming a region having a metal element that promotes crystallization on the non-single-crystal semiconductor film;
By forming a metal silicide with a metal element that promotes crystallization and performing a heat treatment, the metal silicide moves in the non-single-crystal semiconductor film in a direction parallel to the surface of the substrate. After crystallizing the non-single crystal semiconductor film and forming the crystalline semiconductor film,
A method for manufacturing a semiconductor device, wherein the metal silicide after the movement is removed. Forming a non-single-crystal semiconductor film containing silicon on the substrate;
Selectively forming a region having a metal element that promotes crystallization on the non-single-crystal semiconductor film;
By forming a metal silicide with a metal element that promotes crystallization and performing a heat treatment, the metal silicide moves in the non-single-crystal semiconductor film in a direction parallel to the surface of the substrate. After crystallizing the non-single crystal semiconductor film and forming the crystalline semiconductor film,
A method for manufacturing a semiconductor device, comprising: removing the metal silicide after movement and the crystalline semiconductor film under a region having a metal element that promotes crystallization. Forming a non-single-crystal semiconductor film containing silicon on the substrate;
Selectively forming a region having a metal element that promotes crystallization on the non-single-crystal semiconductor film;
By forming a metal silicide with a metal element that promotes crystallization and performing a heat treatment, the metal silicide moves in the non-single-crystal semiconductor film in a direction parallel to the surface of the substrate. After crystallizing the non-single crystal semiconductor film and forming the crystalline semiconductor film,
Removing the crystalline semiconductor film under the metal silicide after movement and the region having a metal element that promotes crystallization;
Forming a gate insulating film on the crystalline semiconductor film;
A method for manufacturing a semiconductor device, wherein an impurity is introduced into a selected portion of the crystalline semiconductor film by an ion doping method. Selectively forming a region having a metal element that promotes crystallization on the substrate;
Forming a non-single-crystal semiconductor film containing silicon on the region having the metal element that promotes crystallization and on the substrate;
By forming a metal silicide with a metal element that promotes crystallization and performing a heat treatment, the metal silicide moves in the non-single-crystal semiconductor film in a direction parallel to the surface of the substrate. After crystallizing the non-single crystal semiconductor film to form a crystalline semiconductor film,
A method for manufacturing a semiconductor device, wherein the metal silicide after the movement is removed. Selectively forming a region having a metal element that promotes crystallization on the substrate;
Forming a non-single-crystal semiconductor film containing silicon on the region having the metal element that promotes crystallization and on the substrate;
By forming a metal silicide with a metal element that promotes crystallization and performing a heat treatment, the metal silicide moves in the non-single-crystal semiconductor film in a direction parallel to the surface of the substrate. After crystallizing the non-single crystal semiconductor film to form a crystalline semiconductor film,
A method for manufacturing a semiconductor device, comprising removing the metal silicide after movement and the crystalline semiconductor film over a region having a metal element that promotes crystallization. Selectively forming a region having a metal element that promotes crystallization on the substrate;
Forming a non-single-crystal semiconductor film containing silicon on the region having the metal element that promotes crystallization and on the substrate;
By forming a metal silicide with a metal element that promotes crystallization and performing a heat treatment, the metal silicide moves in the non-single-crystal semiconductor film in a direction parallel to the surface of the substrate. After crystallizing the non-single crystal semiconductor film to form a crystalline semiconductor film,
Removing the metal silicide after movement, and the crystalline semiconductor film on the region having a metal element that promotes crystallization;
Forming a gate insulating film on the crystalline semiconductor film;
A method for manufacturing a semiconductor device, wherein an impurity is introduced into a selected portion of the crystalline semiconductor film by an ion doping method.   The method for manufacturing a semiconductor device according to claim 1, wherein the non-single-crystal semiconductor film is formed by a CVD method.   The metal element that promotes crystallization is at least selected from nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver. The method for manufacturing a semiconductor device according to claim 1, wherein the element is one element.   The method for manufacturing a semiconductor device according to claim 1, wherein a hydrogen concentration of the non-single-crystal semiconductor film is 5 atomic% or less.

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