CN100521119C - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN100521119C
CN100521119C CN 200610099734 CN200610099734A CN100521119C CN 100521119 C CN100521119 C CN 100521119C CN 200610099734 CN200610099734 CN 200610099734 CN 200610099734 A CN200610099734 A CN 200610099734A CN 100521119 C CN100521119 C CN 100521119C
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film
method
crystallization
silicon film
semiconductor device
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CN1877800A (en )
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张宏勇
福永健司
竹村保彦
高山彻
鱼地秀贵
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株式会社半导体能源研究所
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一种制造半导体器件,例如薄膜晶体管的方法。 For example, one kind of thin film transistor of the semiconductor device. 在非晶硅膜之上或之下,选择形成岛状、线状、条状、点状或膜状的镍、铁、钴、钌、铑、钯、锇、铱、铂、钪、钛、钒、铬、锰、铜、锌、金、银及其硅化物,得到结晶硅膜,再以它们作起始点,在低于普通非晶硅的结晶温度下退火使其结晶化。 Above or below the amorphous silicon film is selectively formed island-like, linear, strip-like, point-like or film-like nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, silver, and silicide, to obtain a crystalline silicon film, then the starting point for them, at a temperature lower than the normal crystallization of amorphous silicon is annealed to cause crystallization. 通过在将变成晶体管有源区的半导体层之上选择形成覆盖膜,然后再使其热结晶化,构成具有薄膜晶体管的动态电路的同时,得到漏电小和迁移率高的晶体管。 By selecting the above semiconductor layer of the transistor into an active region of a transistor formed coating film, and then thermally crystallized, while constituting a dynamic circuit having a thin film transistor, and a small leakage obtain high mobility.

Description

半导体器件及其制造方法 Semiconductor device and manufacturing method thereof

本申请是申请日为1993年12月4日、申请号为200410069654.6 并且发明名称为"半导体器件及其制造方法"的申请的分案申请。 This application was filed on December 4, 1993, and Application No. 200410069654.6 entitled invention is a divisional application of application "semiconductor device and its manufacturing method," the. 技术领域 FIELD

本发明涉及一种制造集成电路的方法,或者更具体地涉及包括具有矩阵结构的矩阵器件(包括电一光显示器和半导体存储器)和作为开关元件的MOS或MIS (金属-绝缘体-半导体)型场效应元件(下文一般称之为MOS型元件)的半导体电路,其特征在于它的动态工作,诸如液晶显示和动态RAM (DRAM)及其驱动电路或类似图像传感器的集成驱动电路。 The present invention relates to a method of manufacturing an integrated circuit, or more specifically, to a device comprising a matrix having a matrix structure (including electro-optic displays and a semiconductor memory) and the switching element as a MOS or MIS (metal - insulator - Semiconductor) type field effect of the semiconductor circuit element (hereinafter generally referred to as MOS type element), characterized in that its dynamic operation, such as a liquid crystal display and a dynamic RAM (DRAM) or the like and a drive circuit driving integrated circuit image sensor. 本发明特别涉及一种采用薄膜半导体元件, 诸如形成于绝缘表面的薄膜半导体晶体管或类似物,如MOS型元件的器件,还涉及具有薄膜晶体管的、其有源层是用晶体硅形成的器件。 The present invention particularly relates to a thin film semiconductor device using such a semiconductor thin film transistor formed on an insulating surface, or the like, such as device-type MOS element, but also relates to devices which are formed in the active layer having a crystalline silicon thin film transistor.

背景技术 Background technique

通常,用于薄膜器件,如薄膜绝缘栅型场效应晶体管(TFT)结晶硅半导体薄膜是用等离子CVD或热CVD方法形成的非晶硅膜在一种设备,如电炉中,在温度高于600。 Typically for thin film devices, such as thin-film insulated gate field effect transistor (TFT) is a crystalline silicon semiconductor thin film is an amorphous silicon thermal CVD or plasma CVD method or the like in an apparatus such as electric furnace at a temperature above 600 . C经24小时以上进行结晶化的方法制备的。 C prepared by the method of crystallization over 24 hours. 为了得到良好的特征,如高场迁移率和高可靠性,需要进行很多小时的热处理。 In order to obtain the good characteristics, such as high-field mobility and high reliability, the heat treatment is required for many hours.

然而,通常的方法存在许多问题。 However, there are many problems the usual way. 问题之一是其生产率低,随之而来的是产品的成本变得高。 One of the problems is its low productivity, followed by the cost of the product becomes high. 例如,若花24小时作晶体化处理时, For example, if the crystallization took 24 hours for processing,

6而若每片衬底花费2分钟时间处理,相同的时间内,必须处理720片衬底。 6 and if the sheet substrate per process takes two minutes, the same time, the substrate 720 must be processed. 然而一个常用的管式炉一次最多能处理50片衬底,当仅用一个设备(反应管)时,每片花30分钟。 However, a conventional tube furnace up to a processing substrate 50, when only one apparatus (reaction tube), each sheet over 30 minutes. 即,为在2分钟处理1片, 就必须用15个反应管。 That is, as a treatment for 2 minutes, 15 must be reaction tubes. 这意味着必须增加投资賴^莫,那是因为投资被大幅度折旧,但不能在产品成本中反映出来。 This means that the need for increased investment Lai ^ Mo, it is because investments are substantial depreciation, but not reflected in the product cost.

另一个问题在于热处理的温度。 Another problem is that the temperature of heat treatment. 一般,用于制造TFT的衬底大致分为由纯氧化硅组成的玻璃,如石英玻璃、非碱硼硅酸玻璃,诸如Coning No. 7059 (下文称之为Coning 7059 )。 In general, for manufacturing the TFT substrate of glass into a substantially pure silicon oxide, like quartz glass, non-alkali borosilicate glass, such as Coning No. 7059 (hereinafter referred to as Coning 7059). 在这些衬底中,前者就温度而言不成问题,因为它的耐热性好,因而能按与正常半导体集成电路的片子加工工艺相同的方式来操作,然而,它的成本高,并随衬底面积的增大而指数增加。 In these substrates, the temperature is not a problem in terms of the former, because of its good heat resistance, which can press the semiconductor integrated circuit of the normal film processing operation to the same manner as the process, however, its high cost, and with the liner increased exponentially increase bottom area. 所以,它仅被用作面积比较小的TFT集成电路。 So, it is used only as a relatively small area TFT integrated circuit.

另一方面,与石英玻璃相比,非碱玻璃的成本虽然十分低,但在耐热方面还存在问题。 On the other hand, compared with quartz glass, non-alkali glass, although the cost is low, but there are problems in terms of heat resistance. 因为它的应变点一般在550~650°C,对某些易于应用的材料,或低于600°C。 Strain point as it is generally 550 ~ 650 ° C, some materials easily applied, or less than 600 ° C. 当用600。 When using 600. C做热处理时,就会导致衬底出现不可逆的收缩或翘曲之类的问题。 When doing C heat treatment, it will cause problems such shrinkage or warpage of the substrate appears irreversible. 当衬底的对角线距离超过10cm时尤为显著。 When the diagonal distance of more than 10cm substrate is particularly significant. 基于上述原因,人们认为必须保持热处理条件低于550。 For these reasons, it is considered heat treatment conditions must be maintained below 550. C,时间不超过4小时,以便降低硅半导体膜结晶化的成本。 C, time is not more than 4 hours, so as to reduce the silicon semiconductor film is crystallized cost. 因而,本发明的一个目的是提供一种半导体的制造方法,其排除这些条件,以及采用这种半导体来制造半导体器件的方法。 Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor, which excludes these conditions, and the use of this method of manufacturing a semiconductor device of a semiconductor.

近来,已进行有关具有薄膜有源层(或称为有源区)的绝缘栅型半导体器件的研究。 Recently, studies on insulated gate type semiconductor device having a thin film active layer (or active area) has been conducted. 特别是对薄膜绝缘栅晶体管或所谓的薄膜晶体管 Especially for so-called thin-film insulated gate transistor or a thin film transistor

(TFT)做了热烈的研究。 (TFT) made a lively research. 它们形成在透明的绝缘衬底上,用来控制每个图象和驱动它的在显示器件,如一个具有矩阵结构的液晶显示器中的矩阵,或用作一个同样形成于绝缘衬底上的图象传感器的驱动电 It is formed on a transparent insulating substrate, for controlling and driving it each picture in the display device, such as a liquid crystal matrix display having a matrix structure, or as a similarly formed on the insulating substrate in FIG. driving the sensor as

路。 road. 根据所用的半导体的材料的晶体状态,它们被分成非晶硅TFT或结晶硅(或称多晶硅)TFT。 The crystal state of the semiconductor material used, and they are divided into amorphous silicon TFT or crystalline silicon (or polysilicon) TFT.

最近,正开展利用介于多晶和非晶硅之间的中间态的材料的研究。 Recently, the use of the intermediate state between the polycrystalline and amorphous materials being carried out. 虽然中间态尚处于讨论中,但所有那些用任何热处理(如用强能量,象激光辐照,在450。C以上的温度的退火)获得的某些晶体状态, 在本说明书中被称为结晶硅。 Although the discussion is still in an intermediate state, some of the crystalline state but all those with any heat treatment (e.g., with a strong energy, such as laser irradiation, annealing at a temperature above the 450.C) obtained in the present specification is referred crystallized silicon.

结晶硅TFT作为一个所谓的SOI技术远^L用于单晶硅集成电路中,在高集成的SRAM中它被用作一个负载晶体管。 Crystalline silicon TFT as a so-called SOI technique for the single crystal silicon integrated circuit is far ^ L, the high integration of the SRAM which is used as a load transistor. 然而,在这种情况下,很少用非晶硅TFT。 However, in this case, rarely used amorphous silicon TFT.

还有绝缘衬底上的半导体电路的工作速度可以很高,因为在衬底和布线之间没有电容耦合,因而提出一种技术,用它作很高速度的微处理机或很高速度的存储器。 There operating speed of the semiconductor circuit on the insulating substrate can be very high, because there is no capacitive coupling between the substrate and the wiring, thus proposes a technique to use it as a high speed microprocessor or a high speed memory .

一般, 一个处于非晶态的半导体的迁移率是低的,因而不能用于工作速度要求很高的TFT。 In general, a mobility of the semiconductor in the amorphous state is low, and therefore can not be used in demanding operating speed TFT. 还有,因为P型非晶硅的场迁移率显著的小,不能制成P-型TFT (PMOS的TFT),因而,不能与N沟型TFT (画OS的TFT)结合形成一个互补MOS电路(CMOS)。 Also, since the P-type amorphous silicon field mobility is significantly small, not made of P- type TFT (of the PMOS TFT), thus forming a complementary MOS circuit can not be combined with the N-channel type TFT (the OS Videos TFT) (CMOS).

然而,用非晶半导体形成的TFT有一个优点,OFF(关断)电流小。 However, TFT formed using an amorphous semiconductor has an advantage, OFF (OFF) a small current. 因而它可被用于:工作速度要求不是很高、仅一种导电类型即可、 以及要求一个电荷保持能力高的TFT,如具有小矩阵规模的液晶显示的有源矩阵电路的晶体管。 So that it can be used: the operation speed is not very high, only one conductivity type can be, and requires a high charge retention capability of the TFT, such as a transistor active matrix circuit having a matrix of small-scale liquid crystal display. 然而,将非晶硅TFT用于尖端应用,如具有大规模矩阵的液晶显示器中,是困难的。 A liquid crystal display, however, the tip of the amorphous silicon TFT is used for applications, such as a large-scale matrix, it is difficult. 还有它自然不能用于显示的外围电路和要求工作速度高的图象传感器的驱动电路。 It is also not natural for driving circuit and the peripheral circuit requires a high operating speed of the displayed image sensor.

8另一方面,结晶半导体的场迁移率大于非晶体半导体的迁移率, 8 On the other hand, the field mobility greater than the mobility of the crystalline semiconductor is an amorphous semiconductor,

可以高速工作。 High-speed work. 例如,在由激光退火利用再结晶的硅膜制得的TFT中, 得到地场迁移率有300cm2/V . s之大。 For example, by using a laser annealing recrystallized silicon film obtained in the TFT, to give the field mobilities 300cm2 / V. The large s. 由在正常单晶硅衬底上形成的MOS晶体管的场迁移率大约是500cm々V 's来看,上面的迁移率则是一个极大的数值。 Field of the mobility of the MOS transistor formed on a single crystal silicon substrate about normal 500cm々V 's point of view, the above mobility is a great value. 但是,单晶硅上的MOS电路的工作速度受衬底与布线间的寄生电容所限,对用结晶化的硅膜制成的TFT来说,则没有这种限制,因为它是形成于绝缘衬底上的。 However, the operating speed of MOS circuits on a silicon single crystal by the parasitic capacitance between the wiring substrate limited, the TFT using the crystalline silicon film is formed, there is no such limitation, since it is formed in the insulating on the substrate. 所以在这种TFT中,可达到预期显著高的工作速度。 Therefore, this TFT, can be expected to achieve significantly higher operating speed.

另外,因为不仅能得到NMOS TFT,而且同样还能得到PMOS TFT,所以可以用结晶硅形成CMOS电路。 Further, since not only get NMOS TFT, but also to give the same PMOS TFT, a crystalline silicon can be formed using a CMOS circuit. 例如,在有源矩阵系统的液晶显示器中,已知用CMO S结晶硅TFT可构成一个不仅具有有源矩阵部分,而且还有外围电路(如驱动器)的所谓的单片结构的系统。 For example, an active matrix liquid crystal display system, it is known with CMO S can form a crystalline silicon TFT active matrix portion having not only a so-called monolithic structure of the system but also a peripheral circuit (e.g., driver). 用于前述的S RAM的T FT正是所提示的这一点,其中的PM OS作为负栽晶体管是由TFT构成的。 T FT is used for the above-described S RAM suggested by this, wherein the plant is a negative PM OS transistor constituted by the TFT.

再有,用于单晶IC技术的自对准工艺,在正常非晶TFT中不易形成源/漏区,并且由栅极与源/漏区的几何重叠引起的寄生电容带来一个问题。 Further, a single crystal self-alignment process IC technology, difficult to form source / drain regions in an amorphous TFT normal, and the parasitic capacitance caused by the geometric overlapping gate and the source / drain regions poses a problem. 但结晶硅TFT有显著压低这种寄生电容的优点,因为它可采用自对准工艺。 However, the crystalline silicon TFT significant advantage of this parasitic capacitance is lowered, since it can be self-alignment process.

然而,当没有电压施加于栅极(非选时期)时,结晶硅TFT的漏电流,与非晶硅TFT的漏电流相比,是大的。 However, when no voltage is applied to the gate (non-selected period), the crystalline silicon TFT leakage current, the leakage current as compared with the amorphous silicon TFT, is large. 但采取这样一种对策,提供一个辅助电容去补偿漏电流,并将两个TFT串联连接,减少它用于液晶显示时的漏电流。 However, to take such a countermeasure, there is provided an auxiliary capacitor to compensate a leakage current, and two TFT connected in series, which is used to reduce leakage current of the liquid crystal display.

例如,已经提出:先形成一非晶硅,再在其上选择地辐照激光, 仅仅使外围电路结晶化的方法,以便在同一衬底上形成具有高迁移率 For example, it has been proposed: forming a first amorphous silicon, and then in the method which is selectively irradiated on the laser, so that only crystallization of the peripheral circuit, so as to form with high mobility on the same substrate,

9的单片多晶硅TFT的外围电路,同时利用非晶硅TFT的高截止(OFF)阻抗。 9 monolithic polysilicon TFT of the peripheral circuit, while using an amorphous silicon TFT of the high cut-off (OFF) impedance.

然而,目前其产量还是低的,那是因为激光辐照工艺的可靠性尚有问题(如在辐照表面内辐照能量的均匀度不好),因而终于采用一种用非晶硅TFT构成一个矩阵,再按TAB或类似方法连接单晶集成电路构成驱动电路的方法。 However, the yield is still low, it is because there are reliability problems laser irradiation process (e.g., a uniform irradiance is not within the energy irradiated surface), thus finally adopt a configuration using an amorphous silicon TFT a matrix, then TAB integrated circuits, or single-crystal driving circuit connected to a similar method. 然而,从连接的结构限制考虑,本方法要宽于0.1mm的象素间距,并且其成本也变得很高。 However, limiting the structural connection from consideration, the present method wider than the pixel pitch of 0.1mm, and its cost becomes high.

发明内容 SUMMARY

本发明想要解决这些难题,但不希望使工艺复杂化,最后降低成本率,提高成本。 The present invention is intended to solve these problems, but do not want to complicate the process, the final cost rate and increase costs. 本发明想要容易地、区别对待地制造两种类型的TFT ,即一种要求迁移率高的TFF和一种要求漏电流低的TFT,同时保持批量生产,并尽量减少工艺的改动。 The present invention is intended to be easily, manufactured discriminate two types of TFT, that is, a high mobility requirements of low leakage current TFF TFT and a requirement while maintaining production, and minimize process changes.

另夕卜,本发明的另一个目的在于减小CMO S电路中NMO S和PMO S迁移率的差值。 Another Bu Xi, another object of the present invention is to reduce the difference circuit NMO S CMO S PMO S and mobility. NMO S和PMO S间差值的减小可增加电路设计的自由度。 PMO S between NMO S and reduce the difference in the degree of freedom in circuit design can be increased.

采用本发明的半导体电路不是万能的。 The semiconductor circuit of the present invention is not a panacea. 即,本发明适合于利用电场作用改变透光率或反光率的那种材料,将材料夹在面对面的两电极间,并在电极间施加电场来显示图象的有源矩阵电路,如液晶显示器; 在电容内存贮电荷用于保持记忆的存储器件,如DRAM:具有动态电路的电路,如动态移位寄存器,它用MO S晶体管的MO S结构部位的电容或其它电容驱动下一个电路;以及具有数字电路和控制才莫拟信号输出的电路,如图象传感器的驱动电路。 That is, the present invention is suitable for a material using an electric field that changes transmittance or reflectance of the material is sandwiched between the two electrodes face and applying an electric field between the electrodes to display an image of the active matrix circuit, such as a liquid crystal display ; memory for holding the stored charge storage device, such as a capacitor in the DRAM: dynamic circuit having a circuit, such as a dynamic shift register, MO S structural part which with MO S transistor capacitance or a further capacitor circuit driven; and a control circuit having a digital circuit and the analog signal output from Mo only, such as the image sensor driving circuit. 本发明特别适合于动态电路和静态电路混合设置的一种电路。 A circuit of the present invention is particularly suited to dynamic circuits and static mixing circuit provided.

本发明的特征在于:先在硅膜之上或之下形成含有由下列材料所组成的组中选出的一种材料的岛状膜、圓点、颗粒、团块或线条,再使其在低于仅仅一般非晶硅热处理过程中的结晶化温度做较短时间的退火,即可得到结晶硅膜,这些材料如下:镍、铁、钴、钌、铑、 4巴、锇、铱、柏、钪、钬、钒、4各、锰、铜、锌、金和银,以及它们的组合物,而硅膜处于非晶态或无序晶态(例如, 一种结晶好的部分和非晶部分相混的状态),可以说基本上是处于非晶态。 The present invention is characterized in that: the first formed of a material from the group consisting of the following materials contained in the selected island-shaped film, dot, granules, lumps or lines above or below the silicon film, and then allowed to Usually just below the amorphous silicon during heat treatment to make the crystallization temperature of the annealing time is short, to obtain a crystalline silicon film, these materials are as follows: nickel, iron, cobalt, ruthenium, rhodium, 4 bar, osmium, iridium, Bo , scandium, holmium, vanadium, 4 each, manganese, copper, zinc, gold and silver, and combinations thereof, and the silicon film is an amorphous or disordered crystalline state (e.g., a crystalline portion and an amorphous good partially mixed state), it can be said to be substantially in the amorphous state. 退火可以在 Annealing can

氢、氧或氮气氛下进行。 Hydrogen, carried out in an oxygen or nitrogen atmosphere. 退火可以按下列条件进行:(l)在含氧的气氛中加热A小时,然后在含氢的气氛中加热B小时;(2)在含氧的气氛中加热C小时,再在含氮的气氛中加热D小时;(3)在含氢的气氛中加热E小时,再在含氧的气氛中加热F小时;(4)在含氢的气氛中加热G小时,再在含氮的气氛中加热H小时;(5)在含氮的气氛中加热I小时,再在含氧的气氛中加热J小时;(6)在含氮的气氛中加热K小时,再在含氢的气氛中加热L小时;(7)在含氧的气氛中加热M小时,在含氢的气氛中加热N小时,然后在含氮的气氛中加热P小时;(8)在含氧的气氛中加热Q小时、在含氮的气氛中加热R小时,再在含氢的气氛中加热S小时;(9)在含氩的气氛中加热T小时,在氧气氛中加热U小时,再在含氮的气氛中加热V小时;(IO)在含氢的气氛中加热W小时,在含氮的气氛中加热X小时, 再在含氧的气氛中加热Y小 Annealing can be carried out under the following conditions: (l) is heated in an oxygen containing atmosphere A hours, and then heated in an atmosphere containing hydrogen hours B; (2) heating an oxygen-containing atmosphere at hours C, in an atmosphere containing nitrogen and then D heated hours; (3) E h was heated atmosphere containing hydrogen, and then heated in an oxygen containing atmosphere F h; (4) heating in a hydrogen containing atmosphere G h, and then heated in a nitrogen atmosphere H hours; (5) was heated in a nitrogen atmosphere I hour and then heated in an atmosphere containing oxygen and J h; (6) was heated in a nitrogen atmosphere K h, and then heated in a hydrogen-containing atmosphere h L ; (7) is heated in an oxygen containing atmosphere M h, is heated in an atmosphere containing hydrogen of N h, and then heated in an atmosphere containing nitrogen P h; (8) was heated in an oxygen containing atmosphere Q h, containing R nitrogen atmosphere heated hours and then heated in an atmosphere containing hydrogen hr S; (9) was heated in an argon atmosphere containing T h, is heated in an oxygen atmosphere U hours and then heated in an atmosphere containing nitrogen V h ; (the IO) W is heated in the atmosphere containing hydrogen hours, heated at an atmosphere containing nitrogen X h, Y then heated in an oxygen-containing atmosphere, a small 时;(11)在含氮的气氛中加热Z小时, 在含氧的气氛中加热A'小时,再在含氢的气氛中加热B'小时;或(12 )在含氮的气氛中加热C'小时,在含氢的气氛中加热D '小时, 再在含氧的气氛中加热E '小时。 When; (11) was heated in a nitrogen atmosphere Z hours, heated in an oxygen containing atmosphere A 'hours and then heated in an atmosphere containing hydrogen B' h; or (12) was heated in an atmosphere containing nitrogen C 'h D was heated in the atmosphere containing hydrogen' hours and then heated in an oxygen containing atmosphere E 'hours.

关于硅膜的结晶化,过去已经提出一种先形成作为晶核或籽晶的结晶的岛状膜,再使它固相外延生长(例如日本特开平1-214110)的方法。 About crystallized silicon film, it has been proposed in the past to form island-shaped film as a nucleation or crystal seed crystal, and then making it a solid phase epitaxial growth (for example, Japanese Patent Laid-Open 1-214110) method. 然而,在60(TC的温度下,用此方法,可勉强生长晶体。 一般, 当硅从非晶态转变为结晶态时,它经受一个工艺过程,非晶态分子链被分开,并在把分开的分子置于不与其它分子耦连的状态之后,分子与某些结晶化的分子相结合,而再结合成为晶体的一部分。然而分离原始分子链并保持它们不与其它分子耦合的状态的能量,在此工艺过程中是大的,它阻止了结晶化反应。为提供此能量,用100(TC的温度, 需用数分钟,或用60(TC的温度,需用数十小时。因为,时间与温度(=能量)有指数关系,例如,在低于600。C或在550。C,几乎一点看不到结晶化反应的进展。固相外延结晶化的概念对此问题也不能给予任何解答。 However, in (the temperature TC at 60, with this method, the crystal growth can be forced. In general, when the amorphous silicon when the transition from the crystalline state, it is subjected to a process, the amorphous molecular chains are separated, and the after separation of molecules into a state not coupled with other molecules, molecules with certain crystallized binding molecules, and then incorporated as part of the crystal. However, separation of the original molecule chains and maintaining the state where they are not coupled with other molecules energy in this process is large, which prevents the crystallization reaction. to provide this energy, with 100 (TC temperature required for several minutes, or a 60 (TC temperature of several tens of hours required because , time and temperature (= energy) have exponential relationship, e.g., at or below 600.C 550.C, almost point of view of progress of the reaction not crystallization. concept of solid phase epitaxial crystal can not be given to this problem any answers.

本发明的发明者考虑到,用某些催化作用来降低前述工艺过程中的阻止能量,它完全不同于常规的固相结晶化概念。 The inventors of the present invention contemplates the use of some catalytic action to prevent decrease the energy process, which is completely different from the conventional solid phase crystallization idea. 本发明者提到: 镍(Ni)、铁(Fe)、钴(Co)、钌(Ru)、铑(Rh)、 4巴(Pd)、锇(Os)、铱(Ir)、 4白(Pt)、钪(Sc)、钛(Ti)、钒(V)、铬(Cr)、猛(Mn)、铜(Cu)、锌(Zn)、金(Au)以及银(Ag),易于与硅耦连。 The present inventors have noted: a nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), 4 bar (Pd), osmium (Os), iridium (Ir), 4 White ( pt), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), Meng (Mn), copper (Cu), zinc (Zn), gold (Au), and silver (Ag), readily and silicon coupled.

例如,本发明者指出,就镍来说,它易于制成硅化镍(NiSix,0.4 《X<2.5)其晶格常数接近硅晶体的晶格常数。 For example, the present inventors have noted that, on the nickel, it is easy to be made of nickel silicide (NiSix, 0.4 "X <2.5) which is close to the lattice constant of the lattice constant of the silicon crystal. 那么,当模拟三元系-晶体硅•硅化镍.非晶硅中的能量和其它条件时,可以观察到,在与硅化镍的边界上,非晶硅易于反应,并大约发生下列反应: Then, when the analog ternary - • nickel silicide crystalline silicon amorphous silicon in energy and other conditions, can be observed at the boundary with nickel silicide, amorphous silicon readily reacts, and approximately the following reaction:

非晶硅(硅A) +硅化镍(硅B) Si (silicon A) + Nickel Silicide (silicon B)

—硅化镍(硅A) +晶体硅(硅B ) (硅A和硅B指示硅的位置) - nickel silicide (silicon A) + Crystalline silicon (silicon B) (A and silicone B indicates the position of the silicon of silicon)

阻止此反应的势能是非常低的,反应温度也是低的。 Prevent this reaction potential energy is very low, the reaction temperature is low. 此反应式指明,在非晶硅被镍转变为晶体硅时,进行该反应。 This reaction formula indicates, when the amorphous silicon is converted into nickel-crystalline silicon, the reaction is carried. 可以发现,此反应实际上起始于58(TC以下,即使在45(TC也能观察到此反应。当然,温度越高,反应进展的速度越快。用上述的其它金属元素,也能看到相同的作用。 Can be found, in fact, starting from this reaction is 58 (TC hereinafter, even in the 45 (TC this reaction can also be observed, of course, the higher the temperature, the faster the rate of progress of the reaction. The above-mentioned other metal elements, can also be seen to the same effect.

根据本发明,先形成一个至少含有Ni、 Fe、 Co、 Ru、 Rh、 Pd、Os、 Ir、 Pt、 Sc、 Ti、 V、 Cr、 Mn、 Cu、 Zn、 Au以及Ag之中的一种元素的膜、颗粒或团块,如岛状、条状、线状、点状或膜状的镍或上述其它单纯金属衬底或它们的硅化物,用作起始点,再按上述反应,把那些金属元素从点扩展到四周,使晶体硅区域延展。 According to the present invention, a first formed containing at least one element from among Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag a film, particles or agglomerates, such as island-shaped, strip-like, linear, dot-shaped or film of pure nickel or other metal substrate, or the aforementioned silicide thereof, as a starting point, then the above reaction, those metal element to extend from the point around which the crystalline silicon region extending. 另外,氧化物不适于作含有那些金属元素的材料,因为氧化物是一种稳定化合物,不能启动前述反应。 The oxide-containing material is not suitable for those metal elements, since the oxide is a stable compound, the reaction can not start.

从一特定点延展的晶体硅的结构,虽然不同于常规固相外延生长,但它接近于单晶硅,结晶的连续性好,因而适宜用作半导体器件,如TFT。 Extending from a particular point of the structure of crystalline silicon, although different from the conventional solid phase epitaxial growth, but which is close to single-crystalline silicon, crystalline good continuity, and thus suitable for use as a semiconductor device, such as a TFT. 然而,当包括加速结晶化的前述金属如镍等材料被均匀设置于衬底上时,会出现无数个结晶化的起始点,因此难以得到结晶性良好的膜。 However, when the crystallization accelerator include metals such as nickel and other materials are uniformly disposed on the substrate, there will be numerous crystallization starting point, it is difficult to obtain a film with good crystallinity.

当氢在作为结晶化起始材料的非晶硅中的浓度更低些,所得到的结果更好些。 When a lower concentration of hydrogen in the amorphous silicon crystallization starting material in some, the better the results obtained. 然而,因为当结晶进展时,会释放出氢,故没有看出在所得到的硅膜内的氢浓度和作为起始材料的非晶硅中的氢浓度之间的清楚的相互关系。 However, since the progress of crystallization, when, releases hydrogen, it is seen that there is no clear correlation between the hydrogen concentration in the hydrogen concentration of the resulting silicon film and amorphous silicon as a starting material in the. 本发明的晶体硅中的氢浓度一般高于0.001at%,低于5at%。 The hydrogen concentration in the silicon crystal according to the present invention is generally higher than 0.001at%, less than 5at%.

虽然Ni、 Fe、 Co、 Ru、 Rh、 Pd、 Os、 Ir、 Pt、 Sc、 Ti、 V、 Cr、 Although Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr,

Mn、 Cu、 Zn、 Au以及Ag被用于本发明,但这些材料一般不适合作为半导体材料的硅,因而必须除去这些材料。 Mn, Cu, Zn, Au and Ag is used in the present invention, but these materials are generally unsuitable for silicon as a semiconductor material, and thus these materials must be removed. 关于镍,因为达到作为前述反应结果的结晶化的终止的硅化镍容易溶于氢氟酸或氢氯酸或 On nickel, nickel silicide to achieve because of the termination of crystallization as a result of the reaction is easily dissolved in hydrofluoric acid or hydrochloric acid, or

13它们的稀释液中,用那些酸处理,可使镍从衬底中减少。 13 dilutions thereof, those using an acid treatment, can reduce the nickel from the substrate. 再有,在结 Further, the junction

晶化工艺终了之后,在含氯的气氛中,经400-600。 After completion of the crystallization process, a chlorine-containing atmosphere, by 400-600. C的处理,确实可减少那些金属元素,含氯物,如氯化氢、变化的氯化甲烷(CH3C1、 CH2C12、 CHC13)、变化的氯化乙烷(C2HsCl、 C2H4C12、 C2H3C13、 C2H2C14、 C2HCls)或变化的氯化乙烯(C2H3Cl、 C2H2C12、 C2HC13)。 Process C, indeed reduce those metal elements, containing substance, such as hydrogen chloride, methane chloride variation (CH3C1, CH2C12, CHC13), chlorinated ethane change (C2HsCl, C2H4C12, C2H3C13, C2H2C14, C2HCls) or variations ethylene chloride (C2H3Cl, C2H2C12, C2HC13). 特别是三氯乙烯是一种容易使用的材料。 In particular TCE is a material easy to use. Ni、 Fe、 Co、 Ru、 Rh、 Pd、 Os、 Ir、 Pt、 Sc、 Ti、 V、 Cr、 Mn、 Cu、 Zn、 Au以及Ag在本发明的硅膜中的浓度一般高于0.005at%,低于lat%。 Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag concentration in the silicon film of the present invention is generally higher than 0.005at% , less than lat%.

在根据本发明为半导体元件,例如TFT,制造的晶体硅膜的使用中,最好不在结晶的终端(也是从多个起始点开始的结晶化相互衔接的部位)制备半导体元件,从上面的说明可以明了,即是因为存在大的晶粒边界(晶性不连续的部位)并因为加速结晶化的金属元素,如镍的浓度高。 In the present invention, described is a semiconductor element such as the TFT, a crystalline silicon film is manufactured, preferably not in crystalline terminal (also from the starting point of a plurality of interrelated crystallized portions) preparing a semiconductor device, from the above can be appreciated, that is because there is a large grain boundaries (discontinuous crystalline portion) and the crystallization accelerator as a metal element, such as a high concentration of nickel. 所以,在利用本发明形成半导体元件时,必须选择最佳的包含将成为结晶化起始点并加速结晶的金属元素,如镍的被覆膜的图形和半导体元件的图形。 Therefore, when the present invention is formed using a semiconductor element, comprising the best must be chosen to become a starting point and a crystallization accelerator crystallized metal elements, such as graphics pattern and the semiconductor element is a nickel coating.

在本发明中,大致有两种方法将加速结晶化的金属元素制成图形。 In the present invention, there are two methods generally accelerate the crystallization of a metal element formed pattern. 第一种方法是在形成非晶硅膜之前,将即些金属有选择地形成膜和类似物,第二种方法是在形成非晶硅膜之后,有选择地使那些金属形成膜和类似物。 The first way is in an amorphous silicon film, i.e. after these metals are selectively formed film and the like, in the second method is an amorphous silicon film, selectively forming a metal film and the like that .

第一种方法可用常规光刻法或剥离法来实现。 The first method used to implement conventional photolithography or lift-off method. 第二种方法或多或少有些复杂。 The second method is more or less complicated. 即,若所形成的加速结晶化的金属膜或类似物依附于非晶硅膜,当膜形成时,金属和非晶硅局部发生相互反应,产生硅化物。 That is, when the acceleration of crystallization of the formed metal film or the like is attached to the amorphous silicon film, when the film is formed of metal and amorphous silicon occurs locally react with each other to produce a silicide. 因而,当形成金属膜或类似物之后制成图形时,必须全面腐蚀硅化物层。 Thus, when the pattern formed after a metal film or the like, must be fully etching the silicide layer.

14按第二种方法,剥离方法比较容易实施。 14 according to the second method, a method relatively easy to peel. 在此情况下,有机材料, 如光刻胶,或无机材料,如氧化硅或氮化硅可用作掩才莫材料。 In this case, an organic material, such as photoresist, or an inorganic material, such as silicon oxide or silicon nitride was used as a masking material mo. 在选择掩模材料时,必须考虑处理温度。 When choosing the masking material, the processing temperature must be considered. 另外,掩模的作用也因材料而异, 必须全心关注它。 In addition, the role of the mask is also depending on the material, we must devote attention to it. 特别是,如果膜不是充分的厚,用各种CVD方法形成的氧化硅或氮化硅膜会有许多针孔,因而结晶化可能是从不希望的部位展开。 In particular, if the film is not sufficiently thick, a silicon oxide or silicon nitride film formed by various CVD methods have many pinholes, and thus crystallization may be desired site never expanded.

一般地是在用这些掩模材料形成被覆膜之后,实施刻图,以便有选择地露出非晶硅的表面。 Generally the coating film is formed after these mask material patterned embodiment, in order to selectively expose the surface of the amorphous silicon. 然后,形成加速结晶化的金属膜或类似物。 Then, a metal film to accelerate crystallization, or the like.

本发明中必须注意在硅膜中金属元素的浓度。 It must be noted in the present invention, the concentration of the metal element in the silicon film. 再好莫过于金属含量小,但使含量总保持恒定也是至关重要的。 Better than the small metal content, but the content always remains constant is also essential. 那是因为,如果金属元素的含量有明显的起伏,将导致所制造的各批格点的结晶度的显著起伏。 That is because, if the content of the metal element is a significant fluctuation, leading to significant degree of crystallization undulation lattice points each batch produced. 特别当要求金属元素的含量更小些时,就变得更难的减小含量的起伏。 Particularly when the content of the metal elements required is much smaller, it becomes more difficult undulating reduced content.

在第一方法中,因为选择形成的金属膜或类似物是^C非晶硅膜覆盖的,则不能去掉后者去调节它的含量。 In the first method, since the metal film or the like is selectively formed in the amorphous silicon film covering ^ C, the latter can not be removed to adjust its content. 依照本发明所要求金属元素 According to the present invention, a metal element as claimed

的含量,金属膜或类似物的厚度薄到只有数A至数十A之薄,因而很难以良好的再现性来形成该膜。 The content of the thickness of the metal thin film or the like to only a few tens of A to A of thin, it is difficult to be formed with good reproducibility of the film.

这同样适用于第二方法。 The same applies to the second method. 不过,与第一种方法相比,第二种方法尚有改进的余地,因为在本方法中,加速结晶化的金属膜或类似物存在于表面。 However, compared with the first method, the second method still room for improvement, because in the present method, to accelerate the crystallization of the metal film or the like present on the surface. 即,先形成一个足够厚的金属膜,在退火使非晶硅膜与金属膜局部发生反应,产生硅化物之前,在低于退火温度的温度下,实施一次热处理(预退火)。 I.e., to form a sufficiently thick metal film, the amorphous silicon film during the annealing the metal film local reaction, before generating the silicide at a temperature lower than the annealing temperature, one embodiment of a heat treatment (pre-annealing). 然后,腐蚀掉未经反应的金属膜。 Then, the metal film is etched away unreacted. 这虽然 Although this

与所用的金属有关,特别是对Ni、 Fe、 Co、 Ti和Cr没问题,因为, 有一种对金属膜和硅化物的腐蚀速率都十分大的腐蚀剂。 For the metal used, particularly for Ni, Fe, Co, Ti, and Cr is no problem, because there is a metal silicide film and the etching rate of the etchant is very large.

15在此情况下,所得到的硅化物的厚度是由热处理(预退火)的温度和时间所决定的,而金属层的厚度几乎与它无关。 15 In this case, the thickness of the resulting silicide is determined by the heat treatment (pre-annealing) temperature and time, and the thickness of the metal layer is almost independent of it. 因此,在非晶硅膜中所引入的金属元素的微小含量是可控制。 Accordingly, the content of fine metal element introduced in the amorphous silicon film is controllable.

本发明还应用,当半导体表面被氧化硅或氮化硅覆盖膜(保护膜) The present invention also applies, when the semiconductor surface is covered with silicon oxide or silicon nitride film (protective film)

盖住时和使结晶硅TFT在450-100(TC最好在500-80(TC在含氧、氢或氮的气氛中结晶化时表面未被覆盖时,结晶度存在差异的情况。该气氛可以是含氧的气氛,含氬的气氛,含氮的气氛、含氧和氢的气氛、 含氧和氮的气氛、含氢和氮的气氛以及含氧、氢及氮的气氛。前述结晶化可按下列条件进行:(1 )在含氧的气氛中加热A小时,然后在含氢的气氛中加热B小时;(2)在含氧的气氛中加热C小时,再在含氮的气氛中加热D小时;(3)在含氢的气氛中加热E小时,再在含氧的气氛中加热F小时,(4)在含氢的气氛中加热G小时,再在含氮的气氛中加热H小时;(5)在含氮的气氛中加热I小时,现在含氧的气氛中加热J小时;(6)在含氮的气氛中加热K小时,再在含氢的气氛中加热L小时;(7)在含氧的气氛中加热M小时,在含氢的气氛中加热N小时,然后在含氮的气氛中加热P小时; When the TFT is covered and that the crystalline silicon at 450-100 (TC uncovered surface is preferably at 500-80 (TC containing oxygen, hydrogen or nitrogen atmosphere, crystallized, crystallinity differences situation. The atmosphere It may be oxygen-containing atmosphere, an argon-containing atmosphere, an atmosphere containing nitrogen, an atmosphere containing oxygen and hydrogen, oxygen and nitrogen atmosphere containing hydrogen and nitrogen and an oxygen-containing atmosphere, a hydrogen and nitrogen atmosphere. the crystallizing according to the following conditions: (1) a heated hours in an atmosphere containing oxygen, and then heated in an atmosphere containing hydrogen hours B; (2) heating an oxygen-containing atmosphere at hours C, in an atmosphere containing nitrogen and then D was heated hours; (3) E h was heated atmosphere containing hydrogen, and then heated in an oxygen-containing atmosphere F hours, (4) heating in a hydrogen containing atmosphere G h, and then heated in a nitrogen atmosphere H h; (5) was heated in a nitrogen atmosphere I hour, heated in an atmosphere containing oxygen and now J h; (6) was heated in a nitrogen atmosphere K h, and then heated in an atmosphere containing hydrogen L h; ( 7) is heated in an oxygen containing atmosphere M h, heated in a hydrogen-containing atmosphere N hours and then heated in an atmosphere containing nitrogen P h; 8)在含氧的气氛中加热Q小时,在含氮的气氛中加热R小时,再在含氢的气氛中加热S小时;(9)在含氢的气氛中加热T小时,在含氧的气氛中加热U小时,再在含氮的气氛中加热V小时;(IO)在含氢的气氛中加热W小时、在含氮的气氛中加热X小时,再在含氧的气氛中加热Y小时;(11 )在含氮的气氛中加热Z小时,在含氧的气氛中加热A'小时,再在含氢的气氛中加热B'小时;或(12)在含氮的气氛中加热C'小时,在含氢的气氛中加热D'小时,再在含氧的气氛中加热E'小时。尤为可取的是(4)在含氢的气氛中加热G小时,再在含氮的气氛中加热H小时,(5)在含氮的气氛中加热I小时(例如4 小时),再在含氧的气氛中加热J小时(例如1小时),或(6)在含氮的气氛中加热K小时(例如4小时),再在含氢的气氛中加热L小时(例如l小时)。当存在覆盖膜时, 一般来说结晶性是 8) is heated in an oxygen containing atmosphere Q h, heated in an atmosphere containing nitrogen R h, and then heated in an atmosphere containing hydrogen hr S; (9) is heated in a hydrogen containing atmosphere T h, the oxygen-containing heated in an atmosphere U hours and then heated in an atmosphere containing nitrogen V h; (the IO) was heated in a hydrogen atmosphere W hours, heated at an atmosphere containing nitrogen X hours and then heated in an oxygen containing atmosphere Y h ; (11) was heated in a nitrogen atmosphere Z hours, heated in an oxygen containing atmosphere a 'hours and then heated in an atmosphere containing hydrogen B' h; or (12) was heated in an atmosphere containing nitrogen C ' hours, heated in an atmosphere containing hydrogen D 'hours and then heated in an oxygen containing atmosphere E' hours is particularly preferably (4) is heated in a hydrogen containing atmosphere G h, and then heated in a nitrogen atmosphere H h, (5) were heated in an atmosphere containing nitrogen h I (e.g. 4 hours), and then heated in an oxygen containing atmosphere J hour (e.g. 1 hour), or (6) was heated in a nitrogen containing atmosphere K h (e.g., 4 hours), L h and then heated (e.g. l h) in an atmosphere containing hydrogen. when there is a cover film, the crystallinity is generally 的,因此可以得到高迁移率的TFT。然而, 一般其漏电流变得显著。另一方面,无覆盖膜的TFT的优点在于漏电流小,可是结晶性不好,其迁移率低,因为它依温度实现非晶态。认为其特性是受渗入有源层的气氛中的氢、氧或氮所控制,结晶化可以在例如氮中,然后再在氢或氧中来实现。在同一衬底、同一时间以及同一工艺过程中形成特性不同的TFT。例如,前一种迁移率高的TFT可以用作矩阵中的驱动电路,而后一种漏电流小的TFT可以用作矩阵中的TFT。 The thus obtained high mobility TFT. However, in general the leakage current becomes significant. On the other hand, the advantages of TFT uncoated film that leakage current is small, but good crystallinity, low migration, since it amorphous achieved by temperature. characteristic is considered to penetrate into the active layer by an atmosphere of hydrogen, oxygen or nitrogen is controlled, for example nitrogen may be crystallized, and then the hydrogen or oxygen is achieved in the same substrate, , at the same time and in the same process to form different TFT characteristics. For example, the former can be used as a high mobility TFT matrix driving circuit, while the latter is a small leakage current of the TFT can be used as a TFT matrix.

与PMOS的迁移率相比,或者可以相对降低NMOS的迁移率, 在CMOS电路中,靠优选的条件,在NMOS区上不设置保护膜,而在PMOS区上设备保护膜,几乎可以消除两者间的差别。 Compared with the mobility of the PMOS or NMOS mobility can be relatively reduced in the CMOS circuit, by the preferred conditions, the NMOS region is not provided in the protective film, and in the PMOS region on the device protective film, virtually eliminates both the difference between.

热结晶化的温度是个重要参数,而TFT的结晶性在本发明是由温度决定的。 Thermal crystallization temperature is an important parameter, while the crystallinity of the TFT in the present invention is determined by the temperature. 一般,热退火的温度是受衬底和其它材料限制的。 In general, the thermal annealing temperature of the substrate is subject to restrictions, and other materials. 就衬底材料的限制而论,当用硅和二氧化硅用作村底时,热退火温度可高到IIO(TC。对于Coning 7059玻璃, 一种典型的无碱玻璃,要求退火温度低于650。C。然而,在本发明基于上述原因,必须为每个TFT,而不是为衬底,设置所要求的重要特征。当退火温度高时, 一般会促进晶体TFT的生长,迁移率提高,以及漏电流也提高。所以退火温度应为450〜1000。C。最好是500~800°C ,以便在同一个类似本发明的衬底上得到不同特征的TFT。 Substrate material limits terms, when used as a substrate of silicon and silicon dioxide Village, the thermal annealing temperature is high enough to IIO (TC. Coning 7059 glass for a typical E-glass, the annealing temperature is lower than required 650.C. However, in the present invention is based on the above-mentioned reasons, must each TFT, wherein the substrate is not important, provided the required. when the annealing temperature is high, generally promote the growth of crystals of the TFT, mobility enhancement, and the leakage current also increases. Therefore, the annealing temperature should 450~1000.C. preferably 500 ~ 800 ° C, in order to obtain different characteristics of TFT on the same substrate similar to the present invention.

本发明的一个实施例是,在液晶显示器有源矩阵电路或类似电路的显示单元中,多晶硅TFT被用作开关晶体管,当使有源层结晶化时, One embodiment of the present invention, the display unit in an active matrix liquid crystal display circuit or the like, a polycrystalline silicon TFT is used as the switching transistor, when the active layer is crystallized, the

在有源矩阵区不设置保护膜,另一方面,在外围电路区设置护膜,使 In the active matrix region is not protective film, on the other hand, the pellicle is provided in the peripheral circuit region, so that

前者转变成漏电流小的TFT,使后者转变成迁移率高的TFT。 The former into small leakage current TFT, the latter is converted into high mobility TFT.

图8 (A)表示如前面所述的具有一个显示电路部分(有源矩阵) 和为它而设的驱动电器(外围电路)的一个装置的构思图。 FIG 8 (A) as previously described represents a conceptual diagram of a device having a circuit section (an active matrix) provided for it and the electrical drive (peripheral circuit) are shown. 在图中, 表示一个显示装置,其中安置一个数据驱动器101和门驱动器102, 中间安置一个具有TFT的有源矩阵103,通过绝缘衬底107上的门线105和数字线106,将这些驱动器部分与有源矩阵相连接。 In the drawing, showing a display device in which is disposed a data driver 101 and gate driver 102, the intermediate is disposed having an active matrix TFT 103 through the gate line on an insulating substrate 107. 105 and digit line 106, to the driver portion connected to the active matrix. 有源矩阵103是具有NMOS或PMO STFT的象素单元的集合(图中的PM〇S )。 The active matrix 103 is set (PM〇S drawing) or have PMO STFT NMOS unit pixels.

对于驱动部分的CMO S电路,在有源层内的杂质,如氧、氮和碳的浓度最好是低于1 0 " / cm3,或优选低于1 0 1 7 /cm3,以便获得高迁移率。其结果是,TFT的阀值电压,例如在NMP S是0.5〜 2V,在PMO S是-0.5〜-3V,而迁移率在NMO S为3 0 ~ 1 5 0 cm2/V 's,在PMOS为20〜100 cm2/V • s。 For CMO S driving circuit portion, the active layer of impurities, such as concentration of oxygen, nitrogen and carbon is preferably less than 1 0 "/ cm3, or preferably less than 1 0 1 7 / cm3, in order to obtain high mobility rate. as a result, the threshold voltage of the TFT, for example, NMP S is 0.5~ 2V, the PMO S is -0.5~-3V, and the mobility of NMO S 3 0 ~ 1 5 0 cm2 / V 's, in the PMOS is 20~100 cm2 / V • s.

另一方面,采用在1 V的漏电压下其漏电流低至lpA的单个的或各个串联的元件,能降低并能进一步完全消除有源矩阵部分的辅助电容。 On the other hand, the use of 1 V at the drain leakage current low pressure lpA single or series of individual elements can be reduced and further the storage capacitor completely eliminate an active matrix portion.

本发明的第二个实施例涉及一个半导体存储器。 A second embodiment of the present invention relates to a semiconductor memory. 一个用单晶I c制成的半导体存储器件早已达到其速度极限。 The semiconductor memory device made of a monocrystalline I c already reached its limit speed. 虽然,必须增加晶体管的电流容量,以便使它以更高有速度工作,这将导致功耗的进一步增加,但不能以增加驱动电压来加以处理,因为对DRAM(来说),电容的容量不能再增加,它是靠电容器中存储电荷来执行记忆功能的。 Although, the current capacity of the transistors must be increased, so that it has a higher rate of work, which would lead to a further increase in power consumption, but to increase the driving voltage can not be processed because of the DRAM (for), capacity of the capacitor can not add, it is performed by the memory function of the charge stored in a capacitor.

为什么说单晶IC已经达到了它的速度极限,原因之一是因为由 Why single crystal IC has reached its speed limit, one of the reasons is because of

18衬底和布线的电容带来很大的损耗,如果用绝缘体做衬底,无须增加 Substrate 18 and the wiring capacitance of a great deal of loss, as the substrate if the insulator, without increasing

功耗即能以足够高的速度工作。 Power that is able to operate at a high enough speed. 基于此原因,已经提出一种具有so I(在绝缘体上的半导体)结构的Ic。 For this reason, there has been proposed having a so I (semiconductor on insulator) structure Ic.

就1晶体管/单元的结构来说, 一个DR AM的电路布局与前述的液晶显示装置的布局几乎相同,而在一个其结构不同于那种结构(例如3晶体管/单元)的DR AM中,当有源层晶体化时,在存储器存储单元(bit)部分不设置保护膜,相反,在驱动电路区域上设置保护膜, 因为要求按照与前述液晶显示装置相同的方法,以足够高的速度工作,使前者转变为漏电流小的TF丁,使后者转变为漏电流大的TFT 。 1 on the structure of the transistor / cell, one DR AM circuit layout and the layout of the liquid crystal display device is substantially the same, and a structure other than that in a structure (e.g., a transistor 3 / unit) DR AM, when crystal of the active layer in the memory cell (bit) portion of the protective film is not provided, the contrary, the protection film disposed on the drive circuit region, as required, to a sufficiently high speed of work according to the same method as the liquid crystal display device, the former into a small leakage current TF-butyl, the latter converted to leakage current of the TFT.

这种半导体存储器的基本组合结构与图8 A所示的结构相同。 8 A substantially same as that shown in FIG combined structure of such semiconductor memory. 例如,在DRAM中,标号(101 )可以是一个列解码器,(102) 是个行解码器,(10 3)是个存储元件部分,(104)是个单位存储单元(bit), ( 1 0 5 )是位(bit)线,(10 6 )是字线以及(107) 是(绝缘)衬底。 For example, in a DRAM, reference numeral (101) may be a decoder column (102) is a row decoder (103) is a storage element section (104) is a unit memory cell (bit), (1 0 5) is a bit (bit) line (106) and the word line (107) is an (insulating) substrate.

本发明的第三个应用例是个用于图象传感器或类似器件的驱动电路,图8(B)表示图象传感器的1位(比特)电路的实例,其中的触发电路108和緩沖电路109 —般由CMOS电路构成,并要求响应速度高,以便跟上施加给扫描线的高速脉沖。 The third application example of the present invention is a driving circuit for an image sensor or the like, and FIG. 8 (B) shows an example of a (bit) image sensor circuit, wherein the trigger circuit 108 and buffer circuit 109 - generally constituted by a CMOS circuit, and the required response speed is high, is applied to the scanning line so as to keep up with high-speed pulse. 另一方面,位于信号输出级的TFT 110起一个控制作用,从移位寄存器108和109接收一个信号, 经光电二级管,把积聚的电荷释放到数椐线。 On the other hand, TFT 110 plays a role of a control signal is located in the output stage, receiving a signal from the shift register 108 and 109, the photodiode, the charge accumulated is released to the line number noted.

对该TFT 110不仅要求响应速度高,而且要求漏电流小。 The TFT 110 requires not only a high response speed, and low leakage current required. 所以, 在该电路中,在电路108和109区域结晶时要设置保护膜,使它转变为高迁移率的TFT。 Therefore, in this circuit, when the circuit 108 and the crystallization region 109 is provided to the protective film, making it into a high mobility TFT. 相反,在TFT 110区域结晶时不须设置保护膜,使它转变成低漏电流的TFT。 In contrast, when the protective film is not required in the crystallization region of the TFT 110, it is converted into a low leakage current TFT.

在本发明中,氧化硅、氮化硅或氧氮化硅(SiNxOy)可用作覆盖膜。 In the present invention, silicon oxide, silicon nitride or silicon oxynitride (SiNxOy) may be used as the cover film. 虽然膜越厚,覆盖性能越好,但必须权衡生产率和保护性能,以便确定厚度,因为欲形成厚膜,则须花费时间。 Although the thicker the film, the better the coverage performance, but the productivity and protection performance must be weighed in order to determine the thickness, as a thick film to be formed, the time shall be spent. 尽管覆盖性能随膜的质量而异, 一般来讲,对氧化硅厚度必须大于20nm,对氮化硅厚度必须大于10nm。 Although the coverage performance varies with the quality of the film, in general, must be greater than a thickness of 20 nm of silicon oxide, silicon nitride must be greater than a thickness of 10nm. 当综合考虑批量生产率和可靠性时,对氧化硅膜和氮化硅膜,其厚度最好都是20〜200nm。 When considering mass productivity and reliability, the silicon oxide film and a silicon nitride film, the thickness thereof is preferably 20~200nm.

附图说明 BRIEF DESCRIPTION

本发明的上述和其它优点,通过下面的说明和附图,将变得更加清楚,在各个视图中,相同的标号代表相同的元部件。 The above and other advantages of the present invention, the following description and the accompanying drawings, will become more apparent from the various views, like numerals represent the same component parts.

图1 ( A)〜1 (C)是表示本实施例(TFT的结晶与布局)的顶视 FIG 1 (A) ~1 (C) shows the present embodiment (TFT crystalline layout) top view

图; Figure;

图2 (Al ) 、 2 ( A-2)及2 (B) ~2 (D)是表示实施例工艺(选择结晶工艺)的剖面图; FIG 2 (Al), 2 (A-2) and 2 (B) ~ 2 (D) is a sectional view of a process embodiment (selective crystallization process);

图3 (A) ~3 (C)是表示该实施例(见第一实施例)工艺的剖面 FIG 3 (A) ~ 3 (C) shows the embodiment (see the first embodiment) process cross-sectional

图; Figure;

图4 (A) ~4 (C)是表示该实施例(见第一实施例)工艺的剖面 FIG. 4 (A) ~ 4 (C) is a sectional view of this embodiment (see the first embodiment) process

图; Figure;

图5 (A) ~5 (C)是表示该实施例(见第二实施例)工艺的剖面 FIG 5 (A) ~ 5 (C) shows the embodiment (see the second embodiment) is a cross-sectional process

图; Figure;

图6 (A) ~6 (C)是表示该实施例(见第三实施例)工艺的剖面 FIG 6 (A) ~ 6 (C) shows the embodiment (see the third embodiment) cross-sectional process

图; Figure;

图7 (A)〜7 (E)是表示该实施例(见第四实施例)工艺的剖面 FIG 7 (A) ~7 (E) shows the embodiment (see the fourth embodiment) process cross-sectional

图; Figure;

20图8 (A)是当本发明被用于一有源矩阵装置之案例的方框图; 图8 (B)是当本发明被用于一图象传感器的驱动电路的一个电 20 FIG. 8 (A) is a block diagram when the present invention is applied to a case of an active matrix device; and FIG. 8 (B) when an electrical driving circuit of the present invention is applied to an image sensor

路图; The road map;

图9 (A) ~9 (C)是表示该实施例工艺的剖面图; FIG. 9 (A) ~ 9 (C) is a sectional view of the embodiment of the process;

图10 (A) ~10 (C)是表示该实施例工艺的剖面图;以及 FIG 10 (A) ~ 10 (C) is a sectional view of the embodiment of a process; and

图11 (A) ~11 (D)是表示该实施例工艺的剖面图。 FIG 11 (A) ~ 11 (D) is a sectional view of the embodiment of the process.

具体实施方式 Detailed ways

实施例1 Example 1

在本实施例中将介绍,用在Coning7059玻璃衬底上形成的各个岛状镍膜作起始点,使非晶硅膜结晶化,用所得到的晶体硅膜制造TFT 的方法。 In the embodiment described in the present embodiment, each of the island-shaped film as the starting point of nickel used in the form of a glass substrate Coning7059, the amorphous silicon film is crystallized, a method for producing crystalline silicon film obtained by a TFT. 根据岛状镍膜是在非晶硅膜之上还是之下形成,则有两种形成岛状镍膜的方法。 Island-shaped nickel film is formed over or under the amorphous silicon film according to, there are two methods of forming the island-shaped nickel film. 图2 (Al )表示在硅膜下形成镍膜的方法,而图2 (A-2)表示在硅膜上形成镍膜的方法。 FIG 2 (Al) represents a method of forming a nickel film in the silicon film, and FIG. 2 (A-2) represents a method of forming a nickel film on the silicon film. 对后一方法必须特别小心, 因为在工艺中,有选择地腐蚀镍是在非晶硅膜的整个表面上形成镍之后,镍和非晶硅相互反应,尽管其量很少,将产生硅化镍。 Care should be taken to the latter method, since in the process, the nickel is selectively etched after forming a nickel film on the entire surface of the amorphous silicon, amorphous silicon and the nickel react with each other, despite the small amount, it will produce a nickel silicide . 因为如果硅化镍照原样留下来,则不能得到好的结晶硅膜,本发明目的之在于, 必须用氢氯酸或氢氟酸完全去掉硅化镍。 Because if the nickel silicide to stay as it is, you can not get a good crystalline silicon film, object of the present invention that must be removed completely nickel silicide with hydrochloric acid or hydrofluoric acid. 因此,非晶硅从原始状态变薄些。 Therefore, the amorphous silicon thin some from the original state.

另一方面,对前一种情况,虽然没有引起这种问题,在此情况下, 除岛状部分之外,也用腐蚀法完全去掉镍膜。 On the other hand, the former case, although not caused such a problem, in this case, in addition to the island shaped portion, also removed completely by etching a nickel film. 用氧等离子或臭氧处理衬底,使岛区以外的镍氧化,可以排除残留镍的影响。 Ozone or oxygen plasma treatment of the substrate, other than nickel oxide islands, can eliminate the influence of residual nickel.

不论哪一种情况,均用等离子CVD方法,在衬底1A (Coning 7059)上形成厚度为2000A的底层氧化硅膜1B。 In either case, both plasma CVD method, formed on the substrate 1A (Coning 7059) a thickness of the bottom layer of the silicon oxide film 1B 2000A. 用等离子CVD方法或真空CVD法制备非晶硅膜1,厚200〜3000A,优选500~1500A。 Plasma CVD method or the like using a vacuum CVD 1 Preparation of the amorphous silicon film, a thickness 200~3000A, preferably 500 ~ 1500A. 基350〜450。 Based 350~450. C退火0.1~2小时去氪,把膜内氢的浓度保持在5at。 C 0.1 to 2 hours to anneal krypton, the hydrogen concentration of the film is maintained at 5at. /。 /. 以下之后,容易使非晶硅膜结晶化。 After less, an amorphous silicon film is crystallized easily.

就图2 ( Al )而论,是在形成非晶硅膜1之前,用溅射法使镍膜堆积到50-1000A,优选100-500A。 To FIG. 2 (Al) is concerned, the amorphous silicon film is formed prior to 1, the nickel film is deposited by sputtering to 50-1000A, preferably 100-500A. 再刻图形成岛状镍区2。 Then cut the island-shaped region in Figure 2 is formed of nickel.

就图2(A-2)而论,则相反,是在形成非晶硅膜l之后,用溅射法使镍膜堆积到50-1000A,优选I00-500A,再刻图形成岛状镍区2。 To FIG. 2 (A-2) is concerned, on the contrary, after forming an amorphous silicon film is L, the nickel film is deposited by sputtering to 50-1000A, preferably I00-500A, and then patterned to form an island region of nickel 2. 图1A表示上述的状态。 1A shows the state described above.

每个岛区镍是2x2)nm的方形,间隔设定为5-50 |um或例如20 Hm。 Nickel each island region is 2x2) nm square, interval is set to 5-50 | um or 20 Hm example. 用硅化镍代替镍,也取得了同样的效果。 Using nickel silicide instead of nickel, the same effect is also achieved. 当要形成镍时,将衬底加热至100-500°C,优选180-250。 When the nickel is to be formed, the substrate is heated to 100-500 ° C, preferably 180-250. C,能得到良好的结果。 C, can get good results. 那是因为改进了底层硅化镍层与镍膜的粘附,还因为由氧化硅与镍反应产生硅化镍,用氮化硅、碳化硅或硅代替氧化硅也能得到相同的效果。 That is because the improved adhesion of the nickel silicide layer underlying nickel film, but also because the nickel oxide to produce a silicon nickel silicide reaction, instead of silicon oxide, silicon nitride, silicon carbide, or the same effect can be obtained.

然后在氮气气氛中在450-580。 Then in a nitrogen atmosphere at 450-580. C或例如在55(TC退火8小时。这退火也可以在氮和氬混合气氛中进行。或者,此退火可以在氬气气氛中进行X1小时,然后在氮气氛中进行X2小时。图2(B)表示此工艺的中间状态,其中的镍从岛状镍区2推进到靠近中心的边缘,成为硅化镍3A,镍已通过的部位3已变成晶体硅。然后如图2(C)所示, 从两个岛状镍膜起始的结晶化衔接,而硅化镍3A留在中间,从而结晶化结束。 C, or for example. This annealing may be carried out in 55 (TC annealed for 8 hours of nitrogen and argon mixed atmosphere. Alternatively, the annealing may be performed in an argon atmosphere for X1 hours, and then in a nitrogen atmosphere for X2 hours. FIG. 2 ( B) shows an intermediate state of this process in which the island-shaped nickel from nickel-advancing area near the center to the edge 2, becomes nickel silicide. 3A, a nickel portion 3 has been passed into the crystalline silicon is then as shown in FIG 2 (C) are shown, two island-shaped adapter crystallization from starting nickel film, the nickel silicide 3A remaining on the intermediate to the end of crystallization.

图1 (B)表示从上看此状态中的衬底,其中图2 (C)中的硅化镍是晶间的边界4。 FIG 1 (B) denotes a substrate in this state seen from above, wherein the nickel silicide in FIG. 2 (C) is a boundary between crystal 4. 当继续退火时,镍沿晶间边界4移动,聚集岛状镍区的中间区5(虽然在此状态下未保持它们原来的形状)。 When continuing the annealing, the grain boundary between the nickel 4 moves along, the intermediate region 5 aggregation (although their original shape is not maintained in this state) island-shaped region of nickel.

用上述工艺可以得到晶体硅,但不希望镍从在此时产生的硅化镍扩散到半导体涂覆膜中。 Crystalline silicon can be obtained by the above process, but the undesirable diffusion of nickel from the nickel silicide generated at this time into the semiconductor coated film. 最好用氢氯酸或氢氟酸腐蚀,消除镍高度集 Preferably with hydrochloric acid or hydrofluoric acid etching to eliminate the nickel current collector height

22聚的区域。 22 Poly regions. 再有,因为镍和硅化镍的腐蚀速度十分大,在用氢氯酸或氢氟酸腐蚀时,硅膜不受影响。 Further, since the etching speed of nickel silicide and nickel is very large, when etching with hydrochloric acid or hydrofluoric acid, a silicon film is not affected. 同时去掉原设置镍的生长点的区域。 A nickel original region growing points simultaneously removed. 图2 (D)表示腐蚀后的状态。 FIG. 2 (D) shows a state after etching. 原来是晶间边界的部位转变为一个槽 The original intergranular boundary portion into a groove

4A。 4A. &于形成半导体TFT的区域(有源层或类似层)是不希望的, 以致要收缩该槽。 & In region (active layer or the like) forming semiconductor TFT is not desirable, so to shrinkage of the groove. 如图1 (C)所示,不使半导体区6跨过晶间边界4 来布局TFT。 As shown in FIG 1 (C), the semiconductor region 6 is not across the boundary 4 to intergranular layout TFT. 即,在平行衬底的水平方向,不在涂覆膜的厚度方向, 在镍作用下的晶体生长区内形成TFT。 That is, in the horizontal direction parallel to the substrate, the coating thickness direction of the film is not, under the crystal growth region formed of nickel action TFT. 应均匀安排晶体生长方向,还应尽量缩小残留的镍。 Should be uniform arrangement direction of crystal growth, but also to minimize the residual nickel. 另一方面,栅线7可以跨越晶间边界4。 On the other hand, the gate lines 7 across intergranular boundaries 4.

图3和图4表示用上述工艺得到的晶体硅制作TFT的方法实施例。 3 and FIG. 4 shows an embodiment of a method of fabricating a TFT using the crystalline silicon obtained by the above process. 在图3 (A)中,中间的标号字符X指示图2中原来是槽4A的地方,如图所示,在布局半导体TFT区域时,不能跨过X部位。 In Figure 3 (A), intermediate reference character X in FIG. 2 indicate the original place in the groove 4A, as shown in the layout of the semiconductor region of TFT, can not cross the X site. 即, 将图2所示工艺所得到晶体硅膜构图形成岛状半导体区lla和llb。 That is, the process shown in Figure 2 to obtain the crystalline silicon film is patterned to form an island semiconductor region lla and llb. 然而,用诸如RF等离子CVD、 ECR等离子CVD或溅射形成作为栅绝缘膜的氧化硅膜12。 However, the silicon oxide film 12 as a gate insulating film formed by such as the RF plasma CVD, the ECR plasma CVD or sputtering.

进一步,用真空CVD方法掺杂1 x 102Q~5 x 102G/cm3的磷,形成厚3000〜6000A的多晶硅膜,然后将它构成图(图3(A)),形成栅电极13a和13b。 Further, a vacuum CVD method using phosphorous doping 1 x 102Q ~ 5 x 102G / cm3, and a polysilicon film having a thickness 3000~6000A then it will block diagram (FIG. 3 (A)), a gate electrode 13a and 13b.

然后,用等离子掺杂方法掺入杂质。 Then, impurity-doped by plasma doping method. 至于掺杂气体,对N型TFT, 使用磷化氢(PH3),对p型TFT,使用乙硼烷(B2H6)。 As a doping gas, the TFT of the N-type, using phosphine (of PH3), the TFT of a p-type, using diborane (B2H6). 对磷化氬加速电压是80KeV,对乙硼烷是65KeV。 Acceleration voltage of an argon phosphide is 80KeV, of diborane is 65KeV. 在55(TC退火4小时,激活杂质,以形成杂质区14a到14b。用光能,如激光退火或闪光灯退火的方法,也可以用于激活(图3 (B))。 In 55 (TC annealed for 4 hours to activate the impurity to form impurity regions 14a to 14b. Light energy, such as laser annealing or flash lamp annealing method, and may also be used to activate (FIG. 3 (B)).

最后,淀积一层厚5000A的氧化硅膜作为层间绝缘体15,与正常制作TFT的情况类似,通过该层形成接能孔,在源和漏区形成布线 Finally, a silicon oxide film is deposited to a thickness of 5000A as an interlayer insulator 15, and the TFT is similar to normal, contact holes can be formed through the layer, a wiring is formed in the source and drain regions

23和电极16a〜16d。 23 and the electrode 16a~16d.

TFT (图中N沟型)就是按上述工艺制备的。 TFT (N channel type in FIG.) Is prepared by the process described above. 所得到的TFT的场效应迁移率,在N沟型是40〜60cm"V *s,在P沟型是30~50cm2/V .s。 The field-effect mobility of the TFT thus obtained, the N-channel type is 40~60cm "V * s, the P-channel is 30 ~ 50cm2 / V .s.

图4表示如何制备铝栅TFT的工艺。 Figure 4 shows how the process of preparing an aluminum-gate TFT. 在图4(A)中,中间的标号字符X指明原是图2中槽4A的地方。 In FIG. 4 (A), intermediate reference character X was originally specified place in the groove 4A 2 of FIG. 对半导体TFT区域的设置不应跨过X部位。 TFT semiconductor region disposed not to cross the X site. 即,将按图2所示工艺得到的晶体硅膜3构图形成岛状半导体区21a和21b。 That is, the process will be the crystalline silicon film shown in Fig 3 obtained patterned island-shaped semiconductor regions 21a and 21b. 然后,用诸如RF等离子CVD、 ECR等离子CVD或测射方法形成作为栅绝膜的氧化硅膜22。 Then, the silicon oxide film 22 as a gate insulating film formed by plasma CVD or exit measuring methods such as RF plasma CVD, the ECR and the like. 当用TEOS (四乙氧硅烷)和氧化原始气体掺杂等离子CVD方法时,能得到满意的效果。 When using TEOS (tetraethoxysilane) gas and the oxidizing dopant original plasma CVD method, satisfactory results can be obtained. 然后,賊射淀积含1%硅的铝膜(厚5000A),再构图形成栅导线和电极23a和23b。 Then, an aluminum film is deposited thief shot containing 1% silicon (thickness 5000A), and then is patterned to form the gate electrode wire 23a and 23b.

接着,将衬底浸入3%酒石酸的乙烯乙二醇溶液中,设置镍作为阴极,铝线作阳极,再在二者间通以电流,实施阳极氧化。 Next, the substrate was immersed in a 3% tartaric acid ethylene glycol solution, a nickel as a cathode, an aluminum wire as the anode, and then on to the current between them, anodic oxidation. 起初按2V/ 分增高其电压来施加电流,当达到220V时,将电压固定。 Initially by 2V / min increase its current voltage is applied, when it reaches 220V, the voltage is fixed. 当电流变成小于10|uA/M2,停止通电,结果,如图4 (A)所示形成厚2000A 的阳极氧化层24a和24b。 When the current becomes less than 10 | uA / M2, the energization is stopped, the results, as shown in FIG 4 (A) is formed 2000A thick anodized layer 24a and 24b shown in FIG.

然后用等离子体掺杂方法掺入杂质。 Then impurity-doped by plasma doping method. 关于掺杂气体,对N型TFT 用磷化氢(PH3),对P型TFT用乙硼烷(B2Hfi) „附图表示N型TFT。 对磷化氢加速电压是80KeV,对乙硼烷是65KeV。用激光退火激活杂质, 形成杂质区25a至25d。所用的激光是KrF激光(波长248nm),用能量密度为250〜300mJ/cm2的激光脉沖辐照5次(图4 (B ))。 About doping gas, on the N-type TFT using phosphine (of PH3), P-type TFT "denotes N-type TFT with the accompanying drawings diborane (B2Hfi). Phosphine acceleration voltage of 80 KeV, of diborane is 65KeV. impurity activation by a laser annealing to form the impurity regions 25a to 25d. KrF laser used was laser light (wavelength of 248 nm), with an energy density of the laser pulse irradiation 250~300mJ / cm2 of 5 (FIG. 4 (B)).

最后,淀积厚5000A的氧化硅膜,作为层间绝缘体26,类似于正常制备TFT的情况,通过该层形成接触孔,以便形成源和漏区的布线和电极27a〜27d(图4(C))。 Finally, 5000A thick silicon oxide film is deposited as an interlayer insulator 26, prepared similar to the normal case where a TFT, a contact hole is formed through the layer to form an electrode wiring and the source and drain regions 27a~27d (FIG. 4 (C )). 所得到的TFT的场迁率是,在N沟型为60〜120cm2/V • s,在P 沟型TFT为50~90cm2/V . s。 Field of the TFT move is obtained in the N channel type of 60~120cm2 / V • s, in the P-channel type TFT is 50 ~ 90cm2 / V. S. 在用此种TFT制作的移位寄存器中,确认在17V的漏电压,工作在6MHz,在20V漏电压工作在llMHz。 TFT produced using such a shift register, it is confirmed in the drain voltage of 17V, 6MHz work, work in the drain voltage at 20V llMHz.

实施例2 Example 2

图5表示一种制作铝栅TFT的情况,与图4所示相似。 FIG. 5 shows the case of fabricating an aluminum-gate TFT, similar to that shown in Fig. 然而,在此实施例中,非晶硅被用作有源层。 However, in this embodiment, amorphous silicon is used as the active layer. 如图5 (A)所示,在衬底31上淀积一层厚2000~3000A的非晶硅膜33。 FIG 5 (A), the amorphous silicon film by depositing a layer thickness of 33 2000 ~ 3000A on the substrate 31. 在非晶硅膜中可以混入适量的P型或N型杂质。 In the amorphous silicon film may be incorporated an appropriate amount of P-type or N-type impurity. 按上所述形成岛状镍或硅化镍涂覆膜34A和34B , 在此状态下,在55(TC退火8小时,或在60(TC退火4小时,使非晶硅膜横向生长而结晶化。 An island formed by the nickel or nickel silicide coating film 34A and 34B, in this state, in the 55 (TC annealed for 8 hours or 60 (TC annealed 4 hours, the amorphous silicon film is crystallized lateral growth .

然后,将如此得到的晶体硅膜构成如图5 (B)所示的图形,此时,因为在图中的中部(镍或硅化镍膜34A和34B之间的中间部位) 的硅膜含有大量有镍,实施刻图时,要去掉此部位,以形成岛状硅区35A和35B。 Then, the thus obtained crystalline silicon film constituting the pattern shown in Figure 5 (B), in which case, since the silicon film in the middle of the figure (nickel or nickel silicide film and the intermediate portion between 34A 34B) containing a large amount nickel, the practice of patterning, to remove this portion, to form island-like silicon regions 35A and 35B. 然后,在其上再淀积基本上本征的非晶硅膜36。 Then, on which the amorphous silicon film 36 is deposited and then substantially intrinsic.

此后,如图5 (C)所示,用诸如氮化硅或氧化硅之物质形成一层涂覆膜,作这栅绝缘膜37。 Thereafter, as shown in FIG 5 (C), the use of materials such as silicon nitride or silicon oxide coating film layer is formed, for which the gate insulating film 37. 用铝形成栅电极38,再用与图4情况相同的方法实施阳极氧化。 The gate electrode 38 is formed of aluminum, and then the same as the case of FIG. 4 anodic oxidation method. 然后用离子掺杂方法扩散杂质,以形成杂质区39A和39B。 Then impurity diffusion by ion doping method to form impurity regions 39A and 39B. 然后再淀积层间绝缘体40,形成接触孔以及在源的漏区形成金属电极41A和41B,完成TFT。 Then depositing the interlayer insulator 40, contact holes 41A and 41B and a metal electrode formed in the drain region of the source, to complete the TFT. 该TFT的特征在于,在源和漏部位的半导体膜是厚的,其阻抗是小的。 Characterized in that the TFT, the source and drain portion of the semiconductor film is thick, the resistance is small. 其结果,降低了源和漏区的阻抗,改进了TFT的特征。 As a result, reducing the impedance of the source and drain regions of the TFT characteristic is improved. 再有,接触可能容易形成接触孔。 Further, the contact is possible to easily form a contact hole.

实施例3 Example 3

图6表示制作CMOS型TFT的工艺过程。 6 shows a production process of a CMOS type TFT. 如图6(A)所示,在衬底51上淀积一底层氧化硅膜52,再在其上淀积一层厚1000-1500A的非晶硅膜53。 FIG 6 (A), the bottom layer is deposited a silicon oxide film 52 on the substrate 51, then depositing a layer thickness of 1000-1500A amorphous silicon film 53 thereon. 然后如上所述,形成岛状镍或硅化镍涂覆膜54,在此状态在550。 Then as described above, nickel or nickel silicide is formed the island-shaped coating film 54 in this state 550. C实施退火。 C annealing. 硅化镍区55沿涂覆膜的平面方向,而不是厚度方向移位,以此工艺推进结晶化。 Coating the nickel silicide region 55 along the planar direction of the film, rather than the thickness direction of displacement, in order to promote the crystallization process. 退火4小时,使非晶硅膜变成如图6 (B)所示晶体硅。 Annealed 4 hours, the amorphous silicon film becomes as shown in FIG 6 (B) shown in crystalline silicon. 硅化镍区59A和59B随着结晶化的推进被推向边缘。 Nickel silicide region 59A and 59B with the crystallization promotion is pushed to the edge.

将如此得到的晶体硅膜构图形成如图6 (B)所示的岛状硅区56。 The thus obtained crystalline silicon film is patterned is formed as shown in FIG 6 (B) island-shaped silicon region 56 as shown. 这里应特别小心,镍被高度集聚在岛区的两端。 Care must be taken here, the nickel is highly concentrated in the both ends of the island portion. 在形成岛状硅区之后, 形成栅绝缘膜57以及栅电极58A和58B。 After forming the island-shaped silicon region, a gate insulating film 57 and the gate electrodes 58A and 58B.

然后,用离子掺杂方法扩散杂质形成N型杂质区60A和P型杂质区60B,如图6 (C)所示。 Then, impurity diffusion is formed by ion doping method, an N-type impurity region and P type impurity region 60A 60B, FIG. 6 (C) shown in FIG. 此时,可以用磷作为N型杂质(掺杂气体是磷化氢PH3)进行掺杂,用60〜110KeV的加速电压使掺杂遍布整个表面,然后用光刻胶覆盖N沟型TFT区,之后再例如,用硼作为P型杂质(掺杂气体是乙硼烷B2HJ ,再用40~80KeV的加速电压进行掺杂。 In this case, phosphorus may be used as an N-type impurity (dopant gas is phosphine PH3) for doping, using an acceleration voltage of doping across the entire surface 60~110KeV, then covered with photoresist N-channel type TFT region, after another example, boron as a P-type impurity (dopant gas is diborane B2HJ, and then an accelerating voltage of 40 ~ 80KeV are doped.

掺杂后,用类似于图4情况的激光辐照,使源和漏区激活。 After the doping, laser irradiation similar to Figure 4 with the case of the activation of the source and drain regions. 然后, 再淀积层间绝缘体61形成接触孔以及在源和漏区形成金属电极62A、 62B和62C,制成TFT。 Then, an interlayer insulator 61 is deposited to form a contact hole and a metal electrode formed in source and drain regions 62A, 62B and 62C, formed TFT.

实施例4 Example 4

图7表示第四个实施例。 7 shows a fourth embodiment. 本实施例涉及一种方法,其中,用第一次热处理(预退火)使镍膜与非晶硅膜的一部分反应,在去掉未反应的镍膜后,再退火使非晶硅膜化,产生硅化物。 The present embodiment relates to a method, wherein a first heat treatment (pre-annealing) reaction of a portion of the amorphous silicon film, nickel film, after removing the unreacted nickel film and then annealing the amorphous silicon film technology, to produce silicide.

用賊射法在衬底(ConmgNo. 7059 ) 701上形成一底层氧化硅膜702 (厚2000A)。 By a thief shot underlayer was formed a silicon oxide film 702 (thickness 2000A) on a substrate (ConmgNo. 7059) 701. 然后,形成一层厚300〜800A,例如厚500A的硅膜703。 Then, forming a thick 300~800A, for example, a silicon film 703 of a thickness of 500A. 再用等离子CVD法形成一层氧化硅膜704。 Plasma CVD method and then a silicon oxide film 704 is formed. 该氧化硅膜704 The silicon oxide film 704

26用作掩膜材料,其厚度优选在500〜2000A。 26 as a mask material, its thickness is preferably in 500~2000A. 若太薄,因针孔使结晶化从意外的地方展开,若太厚,为形成厚膜要花更多时间,这不适于批量生产。 If too thin, because the pinhole crystallization launched from an unexpected place, if too thick, it takes more time to form a thick film, it is not suitable for mass production. 因而这里设在1000A。 Thus here in 1000A.

之后,用公知的光刻工艺,将氧化硅膜704构图。 Thereafter, using a known photolithography process, the silicon oxide film 704 is patterned. 然后用溅射法形成一层镍膜705 (厚500A )。 Then forming a nickel film 705 (500A thick) by sputtering. 镍膜705的厚度最好比IOOA厚[图7 (A)]。 The thickness of the nickel film 705 is preferably thicker than IOOA [FIG 7 (A)].

然后,使它在氮气气氛内,在250〜45(TC (—种预退火工艺)退火10〜60分钟。例如,在45(TC退火20分钟。结果,在非晶硅内形成一层硅化镍706。该层的厚度由预退火的温度和时间决定,而几乎与镍膜的厚度无关(图7 (B))。 Then, in a nitrogen atmosphere so that it, in 250~45 (TC (-. For example, a result, in the nickel silicide layer formed on the amorphous silicon 45 (TC 20 minutes annealing kinds of pre-annealing process) Annealing 10 to 60 minutes. 706. the thickness of the layer is determined by the pre-annealing temperature and time, almost regardless of the thickness of the nickel film (FIG. 7 (B)).

之后,腐蚀该镍膜。 Thereafter, etching of the nickel film. 硝酸或氢氯酸溶液适用于此腐蚀。 Nitric acid or hydrochloric acid solutions are suitable for this etching. 在用这些腐蚀剂腐蚀镍膜过程中,硅化镍层乎不被腐蚀。 During these etchant nickel film, the nickel silicide layer hardly corroded. 在本实施例中,使用一种在硝酸中加入作为緩沖剂的乙酸的腐蚀剂。 In the present embodiment, as the use of a buffer was added acetic acid in nitric acid etchant. 其配比是:硝酸:乙酸:水=1: 10: 10。 Ratio which is: nitric acid: acetic acid: water = 1: 10: 10. 在去掉镍膜之后,在55(TC退火4~8小时( 一种结晶化退火工艺)。 After removal of the nickel film at 55 (TC annealing 4 to 8 hours (A crystallized annealing process).

在结晶化退火工艺中,试过数种方法。 In the crystallization annealing process, we tried several methods. 第一种方法,如图7(C) 所示,在实施此工艺时,同时保留掩模材料704。 The first method, as shown in FIG 7 (C), in the practice of this process, while leaving the mask material 704. 结晶化按图7(C) 箭头所指方向推进。 Figure 7. promote crystallization direction (C) of the arrow. 第二种方法是在去掉所有的掩模露出硅膜之后进行退火。 The second annealing process is carried out after removing the mask to expose all of the silicon film. 第三种方法是在去掉掩模材料之后,在硅膜上形成由氧化硅或氮化硅组成的作为保护膜的新的涂覆膜707之后,进行退火,如图7 (D)所示。 The third method is after removal of the mask material, the silicon film formed of silicon oxide or silicon nitride as a new coating film after the protective film 707, annealing, FIG. 7 (D) shown in FIG.

虽然第一种方法简单,但掩模材料704的表面在预退火步骤与镍的反应,并在更高温度的结晶化退火工艺中变成硅化物,几乎不能腐蚀。 While the first method is simple, but the surface of the mask material 704 in the pre-annealing step with Nickel and becomes silicide annealing process at a higher crystallization temperature, corrosion hardly. 即,因为硅膜和掩模材料704的腐蚀速率几乎相等,为掩模材料去掉后,硅膜被露出的部位也大量被腐蚀,在衬底上产生台阶。 That is, since the silicon film and the mask material 704 is almost equal to the etching rate for the mask material is removed, the exposed portion of the silicon film is also a large number of corrosion, a step is generated on the substrate.

第二种方法很简单,很容易进行腐蚀,因为在结晶化退火工艺之前,掩;漠材料与镍的反应轻微。 The second method is simple, it is easy to corrosion, since prior to crystallization annealing process, mask; desert nickel material was mild. 然而,当进行结晶化退火时,硅表面 However, when the crystallization annealing, the silicon surface

完全被暴露,后来制造的TFT或类似物的特性要变坏。 Completely exposed, then the characteristics of a TFT or the like to be deteriorated.

虽然第三种方法可以稳定地得到优质晶体硅膜。 Although the third method can stably obtain high-quality crystalline silicon film. 但很复杂,因为增加一些工艺过程。 But it is complicated, because of the increased number of processes. 至于第四种方法,是第三种方法的一种改型,该 As a fourth method, a modification of the third method, the

方法包括:在硅表面被暴露的状态下,放入一个炉内,先通氧在500〜55(TC加热大约1小时,以便在表面形成厚20〜60A的薄氧化硅膜, 作为对结晶化退火条件的探讨改为通氮。根据该方法,在结晶化起始阶段形成氧化膜。但在此氧化阶段只在硅化镍膜的附近被结晶化,后来将用作TFT的区(图中右侧部位),没有被结晶化。因此,在远离硅化镍层706的区域硅膜的表面是很平坦的。特性比第二种方法改进许多,与第三种方法几乎相等。 The method comprises: a silicon surface is exposed in a state placed in a furnace, oxygen in the first pass 500~55 (TC heated for about 1 hour, so as to form a thin silicon oxide film on the surface of a thick 20~60A, as the crystallization Discussion annealing conditions to a nitrogen. according to this method, an oxide film is formed at the initial stage of crystallization. However, in the oxidation stage is crystallized only in the vicinity of the nickel silicide film later serving as a TFT region (the right in FIG. side portion), not crystallized. Thus, the surface region of the silicon film remote from the nickel silicide layer 706 is very flat. many improved characteristics than the second method, the third method is almost equal to.

晶体硅膜是这样得到的。 Crystalline silicon film is obtained. 从此以后,将硅膜703构图,同时去掉镍浓度高的部位(设置生长起始区的区域)和生产点(在图中箭头末端的斜线部位),同时只保留镍浓度低的区域。 Since then, a silicon film 703 is patterned, and removing a portion of high nickel concentration (growth start region setting area) and the production points (hatched portions in an arrow tip), while retaining only low nickel concentration regions. 按上所述,形成将用于TFT有源层的岛状硅区708。 Pressing the island-shaped silicon region for the TFT active layer 708 is formed. 然后用等离子CVD形成厚1200A由氧化硅构成的栅绝缘膜709,覆盖住区域708。 Was then formed by plasma CVD thickness of the gate insulating film 709 made of silicon oxide, 1200A, area 708 is covered. 再用厚6000A的掺磷硅膜形成栅电极710和第一层的布线711,用栅电极710作掩模,以自对准方式,将杂质注入有源层708,形成源/漏区712。 Then 6000A thick phosphorus-doped silicon film, a gate electrode 710 and the wiring 711 of the first layer, using the gate electrode 710 as masks in a self-aligning manner, the impurities into the active layer 708, source / drain regions 712 are formed. 然后用可见或近红外强光辐照,对改进结晶化是有效的。 Then with a visible light or near infrared radiation, it is effective for improving the crystallization. 再用等离子CVD法形成厚6000A的氧化硅膜做层间绝缘体713。 6000A-thick silicon oxide film formed by plasma CVD and then the interlayer insulator 713 do. 最后,在层间绝缘体中制出接触孔,再用厚6000A的铝膜形成第二布线714、源/漏电极兼布线715。 Finally, the interlayer insulator prepared in the contact hole, and then forming an aluminum film 6000A thick second wiring 714, the source / drain electrode 715 and the wiring. 以上述的工艺完成TFT (图7 (E))。 In the above-described process is completed TFT (FIG. 7 (E)).

28实施例5 Example 28 5

图9表示本实施例。 FIG 9 showing the present embodiment. 在本实施例中,在TFT型液晶显示装置的有源矩阵区和外围电路中,形成多晶硅TFT。 In the present embodiment, the TFT active matrix type liquid crystal display device and the peripheral circuit region, forming a polysilicon TFT.

首先,在有耐热性质的玻璃衬底如石英玻璃120上,用溅射法, 淀积厚20〜200nm的一底层氧化膜121。 First, on the nature of the heat-resistant glass such as quartz glass substrate 120 by a sputtering method, a deposition of a thickness of 20~200nm underlying oxide film 121. 再用甲硅烷或乙硅烷作原材料,用等离子CVD法或真空CVD法。 Then disilane or monosilane as raw material, plasma CVD method or a vacuum CVD method. 在其上淀积30〜50nm的非晶硅膜。 30~50nm amorphous silicon film is deposited thereon. 这里,氧或氮在非晶硅膜中的浓度低于1018/cm3,最好低于1017/cm3。 Here, the concentration of oxygen or nitrogen in the amorphous silicon film is less than 1018 / cm3, preferably less than 1017 / cm3. 本实施例中,将氧的浓度设置在低于1017/cm3。 In this embodiment, the oxygen concentration is set lower than 1017 / cm3. 用溅射法在非晶硅膜上形成厚100-150nm的氧化硅膜或厚30-100nm的氮化硅膜作为覆盖膜。 100-150nm thick silicon oxide film is formed to a thickness of 30-100nm or amorphous silicon film, silicon nitride film as the cover film by sputtering. 然后构图,仅留下外围电路区域的覆盖膜122。 Then patterned to leave only the film 122 covering the peripheral circuit region. 然后, 在含20-100vol。 Then, containing 20-100vol. /。 /. 的氧或氮的氩或氮的气氛中(600。C )保存4-100小时,使它结晶。 Oxygen or nitrogen atmosphere of argon or nitrogen (600.C) save 4-100 hours it crystallized. 结果,外围电路区的硅膜123A的结晶性是好的,而象素区的硅膜123B的结晶性不好。 As a result, the crystalline silicon film of the peripheral circuit region 123A is good, and the crystalline silicon film of the pixel region 123B good. 图9 (A)示出此状态。 FIG. 9 (A) shows this state.

接下来,将硅膜构成如图9(B)所示的用于形成外围电路TFT 区124A和用于形成象素TFT区124B的岛状。 Next, a silicon film in FIG. 9 (B) for the island-shaped peripheral circuit region TFT 124A and 124B for forming a pixel TFT forming region shown. 然后用溅射法或类似方法形成栅氧化膜125。 Then the gate oxide film 125 is formed by sputtering or the like. 这可用TEOS (四乙氧硅烷)的等离子CVD 法代替溅射法形成。 This can TEOS (tetraethoxysilane) plasma CVD method instead of the sputtering method. 当用TEOS形成该膜时,最好在形成当中或之后, 在高于65(TC的温度退火0.5-3小时。 When the film is formed of TEOS, preferably during or after formation at a temperature above 65 (TC annealing temperature for 0.5-3 hours.

在此之后,用LPCVD法形成厚0.2-2 Mm的N-型硅膜,并将它构成图形,在每个岛区形成栅电极126A-126C。 After this, a thickness of 0.2-2 Mm is formed of N- type silicon film by LPCVD, and it constitutes a graphics, gate electrodes 126A-126C are formed on each island region. 具有较好耐热性能的金属材料,诸如钽、铬、钛、钨和钼可用来代替。 A metal material having good heat resistance, tantalum, chromium, titanium, tungsten and molybdenum may be used instead, such as.

然后,用栅电极部分作掩模,以自对准方式,用离子掺杂法,把杂质注入每个TFT的岛状硅膜。 Then, using the gate electrode portion as a mask in a self-aligning manner by ion doping, the impurity implanted in the island-like silicon film of each TFT. 此时,首先采用磷化氢(PH3)作掺杂气体,把磷注入整个表面,然后用光刻胶(未画出)覆盖图中岛区 In this case, first using phosphine (PH3) as a doping gas, the phosphorus implant the entire surface is then covered with photoresist FIG island region (not shown)

29124A的右侧和矩阵区,之后采用乙硼烷(B2H6)作掺杂气体,把硼注入到左侧的岛区124A。 29124A and right areas of the matrix, after using diborane (of B2H6) as a dopant gas, boron is implanted into the left side of the island portion 124A. 磷的剂量设置为2-8x io15/cm2,而硼的剂量是4-10x I015/cm2,因此硼的剂量应超过磷的剂量。 Phosphorus dose setting 2-8x io15 / cm2, and the dose of boron is 4-10x I015 / cm2, and therefore the dose of boron phosphorus dose should exceed. 这样就产生一个P型区127A和N-型区127B及127C。 This creates a P-type region and the N- type regions 127A and 127B 127C.

在550和75(TC间的温度退火2-4小时进行激活它。本实施例中, 在60(TC进行热退火24小时。该退火工艺激活了离子注入区。 75 and 550 in the temperature (TC between 2-4 hours for annealing to activate it. In this embodiment, the 60 (TC thermal annealing is performed for 24 hours. The annealing process to activate the ion-implanted region.

用激光退火可以完成此工艺。 This can be done with a laser annealing process. 因为用激光退火时,对衬底的热损伤小,所以可以用普通无碱玻璃,例如,Conign7059。 Because laser annealing, thermal damage to the substrate is small, it is possible to use an ordinary non-alkali glass, for example, Conign7059. 另外,可用耐热性差的材料如铝作栅电极材料。 Further, materials with poor heat resistance can be used such as aluminum as the gate electrode material. 按上述的工艺产生了P型区127A 及N-型区127B和127C。 Generating a P-type region and the N- type regions 127A and 127B 127C according to the process described above. 这些区的薄层电阻是200-800Q/口。 The sheet resistance of these regions are 200-800Q / port.

此后,用溅射法在整个表面形成厚300-1000nm的氧化硅膜,作为层间绝缘体128。 Thereafter, a silicon oxide film having a thickness of 300-1000nm entire surface by sputtering, as an interlayer insulator 128. 这可以是用等离子CVD法形成的氧化硅膜。 This may be a silicon oxide film formed by plasma CVD method. 用等离子CVD法。 Plasma CVD method. 特别是用TEOS作原材料,可以得到阶梯覆盖良好的氧化硅膜。 Using TEOS as a raw material in particular, good step coverage can be obtained a silicon oxide film.

然后用溅射法产生一层ITO膜,再构图形成象素电极129。 Then produce a layer of ITO film by sputtering, and then patterned to form the pixel electrode 129. 在TFT 源/漏(杂质区)产生接触孔,以形成氮化钛或铬制成的布线130A-130E。 A contact hole is generated in the TFT source / drain (impurity region), to form the wiring 130A-130E made of titanium nitride or chromium. 图9 ( C )表示用左侧的NTFT和PTFT产生反向器电路。 FIG. 9 (C) is represented by the left side of the NTFT and PTFT generating inverter circuit. 布线130A-130E可以是氮化钛或铬为底层的铝多层布线,以便降低薄层电阻。 Wirings 130A-130E may be aluminum nitride, titanium or chromium multilayer wiring underlayer, in order to reduce sheet resistance. 最后,在氢气中,在200-350。 Finally, in hydrogen, at 200-350. C退火0.5-2小时,以减少硅有源层的悬空键。 C annealing for 0.5-2 hours to reduce the dangling bonds of the silicon active layer. 外围电路和有源矩阵电路可一起集成。 An active matrix circuit and a peripheral circuit may be integrated together. 在本实施例中, 在外围电路部,典型的迁移率对NMOS为80cm2/V . s,对PMOS为50cm2/v . s,而在象素TFT (NMOS )中,迁移率是5-30cm2/v • s。 In the present embodiment, in the peripheral circuit portion, a typical pair of NMOS mobility of 80cm2 / V. S, pair of PMOS is 50cm2 / v. S, whereas the TFT in the pixel (NMOS), the migration rate of 5-30cm2 / v • s.

实施例6 Example 6

图10表示本实施例。 FIG 10 showing the present embodiment. 在本实施例中,采用本发明减少CMOS电路中的NMOS和PMOS的迁移率之差。 In the present embodiment, the present invention is to reduce the difference in the mobility of the CMOS circuit in NMOS and PMOS.

首先,用溅射法在Coning7059衬底131上淀积厚20-200nm的底层氧化膜132。 First, 20-200nm thick is deposited by sputtering of the underlying oxide film 132 on the substrate 131 Coning7059. 用曱硅烷或Z硅烷作原材料,用等离子CVD法或真空CVD法,再在其上淀积厚50-250nm的非晶硅膜。 Yue Z with silane or silanes as raw materials, plasma CVD method or a vacuum CVD method, an amorphous silicon film is then deposited thereon to a thickness of 50-250nm. 在非晶硅膜中氧或氮的浓度底低于10,cn^或最好低于10力cn^。 The concentration of the amorphous silicon film is lower than the oxygen or nitrogen bottom 10, cn ^ 10, or preferably less than the force cn ^. 为此目的,真空CVD 法是适宜的。 For this purpose, the vacuum CVD method is suitable. 本发明中,氧浓度被设置为低于1017/cm3。 In the present invention, the oxygen concentration is set to less than 1017 / cm3.

在PMOS区上设置覆盖膜133 (厚50-150nm的氧化硅膜)。 PMOS region provided on the cover film 133 (silicon oxide film of a thickness of 50-150nm). 然后在氩气或在含50%以上的氧或氢的氮的气氛中,在60(TC退火4-100 小时使之结晶化。其结果,在覆盖膜之下的区域134A的结晶性虽好, 但无覆盖膜的区域134B结晶性却不好。图10 (A)表示出此种状态。 Then the atmosphere of argon or nitrogen containing 50% or more of oxygen or hydrogen, at 60 (TC annealed 4-100 hours for crystallization. As a result, the crystallinity of the region 134A under the cover film is good , but non-crystalline region 134B of the cover film is not good. FIG. 10 (a) shows such a state.

接着,将硅膜构成岛状,以便形成PMOS区135A和NMOS区135B,构图10 (B)所示。 Next, island-shaped silicon film to form a PMOS region and the NMOS region 135A 135B, composition 10 (B).

然后用溅射法形成厚50-150nm的氧化硅膜125,覆盖这些岛区作为栅绝缘膜136。 Then a silicon oxide film 125 is formed by sputtering a thickness of 50-150nm, cover the island as the gate insulating film 136. 然后用賊射法形成厚0.2-2 |um的铝膜,并构图形成栅电极。 0.2-2 thick is then formed by a thief INCIDENCE | UM aluminum film, and patterned to form the gate electrode. 在电解液中给它输送电能,在栅电极之上和侧面形成阳极氧化膜。 In the electrolyte transport electric power to it, the anodized film formed over the gate electrode and the side. 用上述的工艺在每个岛状区形成栅电极部分137A和137B。 The gate electrode portions 137A and 137B formed in each island-like region by the process described above.

然后,用离子掺杂法,用栅电极部分作掩膜以自对准方式,将杂质注入每个TFT的岛状硅膜。 Then, by ion doping method, using the gate electrode portion as a mask in a self-aligned manner, the impurity implanted in the island-like silicon film of each TFT. 此时,首先用磷化氢(PH3)作掺杂气体,把磷注入整个表面,用光刻胶仅覆盖图中的岛区135B,用乙硼烷(B2HJ作掺杂气体,将硼注入岛区135A。磷的剂量设置为2-8x 1015/cm2,硼的剂量设置为40-10 x I015/cm2,以使硼的剂量超过磷的剂量。 At this time, first with phosphine (PH3) as a doping gas, the phosphorus implant the entire surface, covered with photoresist island portion 135B only figure, with diborane (B2HJ as the dopant gas, implanting boron into the island area 135A. dose of phosphorus was set to 2-8x 1015 / cm2, dose amount of boron to 40-10 x I015 / cm2, so that a dose exceeding a dose of boron phosphorus.

虽然掺杂过程破坏了硅膜的结晶性,但它的薄层电阻仍可保持在lKQ/口左右。 Although the doping process destroys the crystalline silicon film, but its sheet resistance can be maintained at about lKQ / port. 然而,若此种程度的薄层电阻还高,再在600 。 However, if such a higher degree of sheet resistance, then at 600. C退火2-4小时,可降下薄层电阻。 C 2-4 hours annealing, the sheet resistance can be lowered. 用强光或激光辐照可得到相同效果。 Light or laser irradiation with the same effect can be obtained.

这样就形成了P型区138A和N-型138B。 Thus forming a P-type region 138A and N- type 138B. 这些区的薄层电阻为200-800Q/口。 The sheet resistance of these regions is 200-800Q / port. 然后用賊射法在整个表面上形成厚300-1000nm的氧化硅膜作层间绝缘体139。 Then exit thief was formed between the silicon oxide film as the insulator layer 139 in a thickness of 300-1000nm on the entire surface. 这可以是用等离子CVD法形成的氧化硅膜。 This may be a silicon oxide film formed by plasma CVD method. 用等离子CVD方法特别是用TOES作原材料,可得到阶梯覆盖良好的氧化硅膜。 A plasma CVD method as a starting material especially with TOES, good step coverage can be obtained a silicon oxide film.

然后在TFT的源/漏(杂质区)形成接触孔,以形成铝布线140A-140D。 Then the TFT source / drain (impurity region) forming a contact hole, to form an aluminum wiring 140A-140D. 最后,在氬气中的250-350。 Finally, 250-350 in argon. C的温度退火2小时,以减少硅膜的悬空键。 C annealing temperature for 2 hours to reduce the dangling bonds of the silicon film. 用上述工艺得到的TFT的典型迁移率,对PMOS和NMOS均为60cm2/v . s。 Typically the mobility of the TFT obtained by the above process, both of PMOS and NMOS 60cm2 / v. S. 当用本发明的工艺制作移位寄存器时,证实在20V的漏电压下,工作在10MHz以上。 When produced by the process of the shift register of the present invention, it demonstrated in the drain voltage of 20V, working in more than 10MHz.

实施例7 Example 7

图11表示本实施例。 FIG 11 showing the present embodiment. 本实施例涉及晶体管和硅电阻相结合的电路。 The present embodiment relates to a silicon resistor and a transistor circuit combined. 用杂质掺杂的硅可用作晶体管的保护电路。 Impurity-doped silicon may be used as the protective circuit transistor. 首先,用溅射法在Conmg7059衬底140上淀积厚20-200nm的底氧化膜。 First, 20-200nm thick is deposited by sputtering a bottom oxide film on the substrate 140 Conmg7059. 在其上,再用等离子CVD法或真空CVD法,以曱硅烷或乙硅烷作原作料,淀积厚100-250nm的非晶硅膜。 Thereon, and then a plasma CVD method or a vacuum CVD method to Yue silane or disilane as the original material, an amorphous silicon film is deposited to a thickness of 100-250nm. 这里,在非晶硅膜中,氧或氯的浓度层低于1018/cm3,或最好低于1017/cm3。 Here, the amorphous silicon film, the concentration of oxygen or chlorine layer is less than 1018 / cm3, or preferably less than 1017 / cm3.

淀积20-200nm的氧化硅覆盖143,并在氩或氮的气氛中,在60(TC退火4-100小时,使其结晶化。图11 (A)表示出此状态。 The deposited silicon oxide capping 20-200nm 143, and in an atmosphere of argon or nitrogen, in 60 (TC annealed 4-100 hours to crystallize. FIG. 11 (A) shows this state.

下面,将硅膜构成岛状,以形成晶体管区144A和电阻区144B, 如图11 (B)所示。 Next, the island-shaped silicon film to form a transistor region and the resistor region 144A 144B, as shown in FIG. 11 (B). 然后用溅射法形成厚50-150nm的氧化硅膜覆盖那些岛区作栅绝缘膜145。 Then 50-150nm thick silicon oxide film is formed covering the island as those for the gate insulating film 145 by sputtering. 然后,用溅射法形成厚0.2-2 jLim的铝膜, 再构图形成栅电极。 Then, an aluminum film having a thickness of 0.2-2 jLim by sputtering, and then patterned to form the gate electrode. 给在电解液内的铝膜输送电能,在栅电极的上部和侧面形成阴极氧化膜。 Aluminum in the electrolyte to transport electrical energy, a cathode and an oxide film is formed in an upper side surface of the gate electrode. 用上述的工艺,在每个岛区上,形成栅电极 Using the above process, on each island region, a gate electrode

部分146。 Section 146.

然后,用栅电极部分作掩膜,以自对准方式,用离子掺杂法,把杂质,如磷注入到每个TFT的岛状硅膜。 Then, using the gate electrode portion as a mask in a self-aligning manner by ion doping method, an impurity such as phosphorus implanted into the island silicon film of each TFT. 磷的剂量为2-8 x 1015/cm2。 Dose of phosphorus is 2-8 x 1015 / cm2.

用上述的掺杂工艺形成杂质区147A和147B。 147A and 147B forming an impurity region by doping process described above. 因为相同的杂质量被注入到两个掺杂区。 Since the same two impurities are implanted into the doped region. 当按照实际的要求热退火时,它们表示出相同的电阻率。 When annealed according to the actual requirements of heat, which shows the same resistivity. 然而,情况却是,例如当对后者要求较高的电阻时,而前者反倒要求较低的电阻。 However, it is the case, for example, when the resistance of which requires a higher, while the former actually require lower resistance. 然后,仅在晶体管区,如图11 (C)所示, 形成厚50-150nm的氧化硅覆盖膜148。 Then, only in the transistor region, as shown in FIG. 11 (C), a silicon oxide having a thickness of 50-150nm cover film 148. 然后在含大于50vol。 Then containing greater than 50vol. /。 /. 的氧或氢的氮或氩的气氛中,在550-65(TC的温度,退火4-20小时。可用磷化氢代替氧或氢。然而,退火温度最好低于80CTC,因为倘若退火温度太高,磷化氢将被热分解,并扩散到半导体中,反而降低了电阻率。 当杂质的电阻区是P-型时,可以用乙硼烷(B2H6)。 Hydrogen, oxygen or nitrogen or argon atmosphere, at 550-65 (temperature TC, the annealing 4-20 hours. Phosphine instead of oxygen or hydrogen can be used, however, the annealing temperature is preferably lower than 80CTC, because if the annealing temperature is too high, the phosphine is thermally decomposed and diffused into the semiconductor, but lower resistivity. when the impurity region is a P- type resistor, it is possible with diborane (of B2H6).

用上面的工艺,当晶体管的杂质区的薄层电阻是20-800Q/口时, 电阻的杂质区的薄层电阻是2K-100Q/口。 Using the above process, when the sheet resistance of the impurity region of the transistor is 20-800Q / port when the sheet resistance of the resistance of the impurity region is 2K-100Q / port. 用溅射法在整个表面上形成厚300-1000nm的氧化硅膜,作为层间绝缘体149。 300-1000nm thick silicon oxide film is formed on the entire surface by a sputtering method as an interlayer insulator 149. 这可以是用等离子CVD法形成的氧化硅膜。 This may be a silicon oxide film formed by plasma CVD method. 用等离子CVD法,特别是用TEOS作原材料,可以得到覆盖阶梯良好的氧化硅膜。 Plasma CVD method using TEOS as a raw material in particular, good step coverage can be obtained a silicon oxide film.

在TFT的源/漏(杂质区)形成接触孔,以形成铝布线150A-150C。 The TFT source / drain (impurity region) forming a contact hole, to form an aluminum wiring 150A-150C. 最后,在氢气中在250-350。 Finally, 250 to 350 in hydrogen. C温度退火0.5-2小时。 C annealing temperature for 0.5-2 hours. 以便减少硅膜悬空键。 In order to reduce the dangling bonds of the silicon film. 经上述工艺可区分其厚度相同,杂质注入量相同的区域的薄层电阻。 Following the above process may distinguish which is the same thickness, the same amount of impurities sheet resistance region.

如上所述,在某种意义上说,本发明是个划时代的发明,这促进了非晶硅在较低温度和较短时间实现结晶化,并为工业提供不可估量 As described above, in a sense, the present invention is an epoch-making invention, which promotes the crystallization of amorphous silicon to achieve at lower temperatures and shorter time, and provide invaluable industrial

33的效益。 33 benefits. 因为所用的设施、仪器和技术很普通的,而对批量生产则是极为优良的。 Because the facilities used, the equipment and technology is common, while the production is very good. 虽然在前述的实施例中,着重对镍进行了解释,而同样 Although in the foregoing embodiment, focusing on the nickel explained, and the same

的工艺可适用于另一些加速结晶化的金属元素,例如Fe、 Co、 Ru、Rh、 Pd、 Os、 Ir、 Pt、 Sc、 Ti、 V、 Cr、 Mn、 Cu、 Zn、 Au和Ag中的 The process may be applied to accelerate the crystallization of other metal elements, such as Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag

任一元件素。 A member of any element.

例如,假定处理一片村底须花两分钟,而在常规固相生长方法中需要15个退火炉,因为至少需要24小时的退火。 For example, assume that a village substrate processing shall take two minutes, 15 annealing furnaces required in the conventional solid phase growth method, since at least 24 hours annealing. 本发明可使退火炉的数减到小于1/6,因为退火时间可缩短到4小时或更短的时间。 The present invention allows reduced to less than 1/6 of the number of the lehr, because the annealing time can be shortened to four hours or less. 由于衬底加工成本的下降,以及TFT成本的下降,以此生产率的提高、设备投资的降低以及因此而来的新需求的上升。 Due to the decrease of the substrate processing costs, and a decline in the cost of TFT, in order to improve productivity, reduce equipment investment and the consequent rise of new demand. 所以,本发明对工业是很有利的,理所当然地应获得专利。 Therefore, the present invention is industrially very advantageous, of course, to be patented.

另外,本发明以TFT有源层结晶条件的最小改动一有或者无覆盖膜,解决了常规的结晶硅TFT生产工艺中的难题。 Further, the present invention is to minimize crystallization conditions change a TFT active layer with or without a cover film, to solve the conventional crystalline silicon TFT production process problems.

本发明尤其可改进动态电路和具有该电路的装置的可靠性和性能。 In particular, the present invention can improve reliability and performance, and dynamic circuits having the circuit device. 一般,虽然对液晶显示的有源矩阵来说,结晶硅TFT的ON/OFF比是低的,并无论如何均难以投入实用,本发明认为这类问题已^皮解决。 In general, although the active matrix liquid crystal display, the crystalline silicon TFT of the ON / OFF ratio is low, and in any event are difficult to put into practice, according to the present invention that such problems have been resolved transdermal ^. 虽然未以实施例表明,很清楚,当实施本发明时,将TFT用作实施立体单晶半导体集成电器的装置会是有效的。 Although not showed in Example, it is clear that when the embodiment of the present invention, the TFT is used as the single crystal semiconductor integrated electrical perspective embodiment of the device will be effective.

例如,可用半导体电路知单晶半导体上做成外围逻辑电路,并通过层间绝缘体中介物,在其上设置TFT,来构成存储元件部分。 For example, the semiconductor circuit can be used to make known the peripheral logic circuit on a single crystal semiconductor, and through the intermediary of an interlayer insulator, on which the TFT is provided, to constitute a memory element portion. 在此情况下,存储元件部分可以是利用本发明的TFT的DRAM电路,而它们驱动电路是由^皮做成单晶半导体电路的CMOS构成。 In this case, the memory element portion may be a TFT of the present invention utilize a DRAM circuit, and they are driven by a circuit made of a single crystal semiconductor transdermal ^ CMOS circuit configuration. 再有,当此种电路被用于微处理机时,可节省其面积,因为可把存储器部分在上层制造,认为本发明对工业是很有用的发明。 Further, when such a circuit is used for microprocessor, the area can be saved, since the memory can be manufactured in the upper part, that the present invention is useful for industrial invention.

34虽然参照其优选实施例已特别表示和介绍了本发明,但本领域的技术人员应了解到,在形式和细节上可以进行上述的和其它的改变,仍不应脱离本发明的精神和范畴。 While the preferred embodiments thereof with reference 34 has been particularly shown and described embodiments of the present invention, those skilled in the art should understand that the above and may be other changes in form and details, should not be an departing from the spirit and scope of the invention .

Claims (20)

  1. 1. 一种半导体器件的制造方法,包括以下步骤:在衬底上形成非晶硅膜;为非晶硅膜提供用于加速结晶化的金属元素;使所述的被提供了用于加速结晶化的金属元素的非晶硅膜结晶化;在结晶化的硅膜上形成栅绝缘膜;在栅绝缘膜上形成第一栅电极和第二栅电极;在结晶化的硅膜中形成一对第一杂质区和一对第二杂质区;以及形成与该对第一杂质区的一个和该对第二杂质区的一个电连接的布线,其中,该对第一杂质区的所述一个与该对第二杂质区的所述一个接触。 A method of manufacturing a semiconductor device, comprising the steps of: forming an amorphous silicon film on a substrate; providing a metal element for accelerating crystallization of an amorphous silicon film; the acceleration is provided a method for crystallization metal element amorphous silicon film is crystallized; forming a gate insulating film on the crystallized silicon film; forming a first gate electrode and second gate electrodes on the gate insulating film; forming a pair of crystallized silicon film a first impurity region and a pair of second impurity region; and forming, wherein the first impurity region of said one of the first impurity region and the wiring of a second one of the pair is electrically connected to the impurity region the one contact to the second impurity region.
  2. 2. 根据权利要求1所述的半导体器件的制造方法,其中,该用于加速结晶化的金属元素包括镍。 The method of manufacturing a semiconductor device according to claim 1, wherein, for accelerating the crystallization of the metal element include nickel.
  3. 3. 根据权利要求1所述的半导体器件的制造方法,其中,该对第一杂质区由磷组成。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the pair of first impurity regions composed of phosphor.
  4. 4. 根据权利要求1所述的半导体器件的制造方法,其中,该对第二杂质区由硼組成。 The method of manufacturing a semiconductor device according to claim 1, wherein the pair of second impurity regions of boron.
  5. 5. 根据权利要求1所述的半导体器件的制造方法,还包括步骤: 在形成该对第一杂质区和该对第二杂质区之后,用激光照射结晶化的硅膜。 The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: the first impurity region and the pair of second impurity regions after, irradiated with a laser crystallized silicon film is formed.
  6. 6. 根据权利要求1所述的半导体器件的制造方法,其中该结晶化步骤是以从50(TC至800。C的温度进行的。 The method of manufacturing a semiconductor device according to claim 1, wherein the crystallization step is carried out in from 50 (the temperature TC to 800.C.
  7. 7. 根据权利要求1所述的半导体器件的制造方法,还包括步骤: 在结晶化步骤之后,将结晶化的硅膜中用于加速结晶化的金属元素的浓度降低。 The method of manufacturing a semiconductor device of claim 1, further comprising the step of claim: After the crystallization step, the crystallized silicon film for reducing the concentration of a metal element which accelerates the crystallization of.
  8. 8. —种半导体器件的制造方法,包括以下步骤: 在衬底上形成非晶硅膜;为非晶硅膜提供用于加速结晶化的金属元素; 使所述的被提供了用于加速结晶化的金属元素的非晶硅膜结晶化;在结晶化的硅膜上形成栅绝缘膜; 在栅绝》彖膜上形成第一栅电极和第二栅电极; 在结晶化的硅膜中形成一对第一杂质区和一对第二杂质区;以及形成与该对第一杂质区的一个和该对第二杂质区的一个电连接的布线,其中,该对第一杂质区的所述一个与该对第二杂质区的所述一个4妄触,并且其中,在该结晶化的硅膜的两端中,该用于加速结晶化的金属元素处于高浓度。 8 - The method of manufacturing a semiconductor device, comprising the steps of: forming an amorphous silicon film on a substrate; providing a metal element for accelerating crystallization of an amorphous silicon film; the acceleration is provided a method for crystallization metal element amorphous silicon film is crystallized; forming a gate insulating film on the crystallized silicon film; a gate insulating "hog film forming the first gate electrode and second gate electrodes; forming a crystallized silicon film a pair of first impurity regions and a pair of second impurity region; and forming the pair of impurity regions of a first one of the pair and the wiring is electrically connected to the second impurity region, wherein the pair of said first impurity region a jump to a contact 4 of the pair of the second impurity region, and wherein both ends of the crystallized silicon film, for accelerating the crystallization of a metal element at a high concentration.
  9. 9. 根据权利要求8所述的半导体器件的制造方法,其中,该用于加速结晶化的金属元素包括镍。 The method for manufacturing a semiconductor device according to claim 8, wherein, for accelerating the crystallization of the metal element include nickel.
  10. 10. 根据权利要求8所述的半导体器件的制造方法,其中,该对第一杂质区由磷组成。 10. A method of manufacturing a semiconductor device according to claim 8, wherein the pair of first impurity regions composed of phosphor.
  11. 11. 根据权利要求8所述的半导体器件的制造方法,其中,该对第二杂质区由硼组成。 11. A method of manufacturing a semiconductor device according to claim 8, wherein the pair of second impurity regions of boron.
  12. 12. 根据权利要求8所述的半导体器件的制造方法,还包括步骤: 在形成该对第一杂质区和该对第二杂质区之后,用激光照射结晶化的硅膜。 12. A method of manufacturing a semiconductor device according to claim 8, further comprising the step of: the first impurity region and the pair of second impurity regions after, irradiated with a laser crystallized silicon film is formed.
  13. 13. 根据权利要求8所述的半导体器件的制造方法,其中该结晶化步骤是以从50(TC至80(TC的温度进行的。 13. A method of manufacturing a semiconductor device according to claim 8, wherein the crystallization step is carried out in from 50 (TC to 80 (TC temperature.
  14. 14. 根据权利要求8所述的半导体器件的制造方法,还包括步骤:在结晶化步骤之后,将结晶化的硅膜中用于加速结晶化的金属元素的浓度降低。 14. A method of manufacturing a semiconductor device according to claim 8, further comprising the step of: after the step of crystallization, the crystallized silicon film for reducing the concentration of a metal element which accelerates the crystallization of.
  15. 15. —种半导体器件的制造方法,包括以下步骤: 在衬底上形成非晶硅膜; 为非晶硅膜提供用于加速结晶化的金属元素; 使所述的被提供了用于加速结晶化的金属元素的非晶硅膜结晶化;在结晶化的硅膜上形成栅绝缘膜;以及在栅绝缘膜上形成栅电极,在结晶化的硅膜的两端中,该用于加速结晶化的金属元素处于高浓度。 15. - The method of manufacturing a semiconductor device, comprising the steps of: forming an amorphous silicon film on a substrate; providing a metal element for accelerating crystallization of an amorphous silicon film; the acceleration is provided a method for crystallization metal element amorphous silicon film is crystallized; forming a gate insulating film on the crystallized silicon film; and forming a gate electrode on the gate insulating film, at both ends of the crystallized silicon film, for accelerating the crystallization a metal element in a high concentration.
  16. 16. 根据权利要求15所述的半导体器件的制造方法,其中,该用于加速结晶化的金属元素包括镍。 16. The method of manufacturing a semiconductor device according to claim 15, wherein for accelerating the crystallization of the metal element include nickel.
  17. 17. 根据权利要求15所述的半导体器件的制造方法,还包括步骤:在^f册电极之上形成层间绝缘体。 17. A method of manufacturing a semiconductor device according to claim 15, further comprising the step of: forming an interlayer insulator on the electrode volumes ^ f.
  18. 18. 根据权利要求15所述的半导体器件的制造方法,其中,该两端包括^圭化物。 18. A method of manufacturing a semiconductor device according to claim 15, wherein the two ends thereof comprises ^ Kyu.
  19. 19. 根据权利要求15所述的半导体器件的制造方法,其中该结晶化步骤是以从500。 19. A method of manufacturing a semiconductor device according to claim 15, wherein the crystallization step is from 500. C至80(TC的温度进行的。 To C 80 (TC is the temperature.
  20. 20.根据权利要求15所述的半导体器件的制造方法,还包括步骤:在结晶化步骤之后,将结晶化的硅膜中用于加速结晶化的金属元素的浓度降低。 20. The method of manufacturing a semiconductor device according to claim 15, further comprising the step of: after the step of crystallization, the crystallized silicon film for reducing the concentration of a metal element which accelerates the crystallization of.
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EP0481777A2 (en) 1990-10-17 1992-04-22 Sel Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing gate insulated field effect transistors
EP0497592A2 (en) 1991-01-30 1992-08-05 TDK Corporation Non single crystal semiconductor device and manufacturing method

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Publication number Priority date Publication date Assignee Title
EP0481777A2 (en) 1990-10-17 1992-04-22 Sel Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing gate insulated field effect transistors
EP0497592A2 (en) 1991-01-30 1992-08-05 TDK Corporation Non single crystal semiconductor device and manufacturing method

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