JPS58115851A - Active matrix substrate - Google Patents

Abstract

PURPOSE:To enable to manufacture the substrate for an active matrix panel at a low temperature and moreover by a simple process by a method wherein an Al layer or an Al alloy layer to be used as a low temperature impurity diffusion source is used for a wiring layer, and moreover for up to the gate electrode material. CONSTITUTION:A silicon thin film 21 is formed on the transparent substrate 20, and moreover after a gate insulating film 22 is formed and the gate electrode material 23 is deposited, the gate electrode 25 is formed by patterning, and a gate insulating film 24 is formed using the gate electrode thereof as the mask. Then the Al layer or the Al alloy layer 26 of Al-Si, etc., to be used both as the diffusion source and as the wiring layer is formed according to the evaporation method or the sputtering method, and after then by performing annealing at 300-450 deg.C for about 5-20min, Al diffuses in the Si film as impurities at a comparatively low temperature. As a result, source and drain diffusion layers 27, 28 and a channel 29 are formed, and after then the Al layer or the Al alloy layer used as the diffusion source is patterned to be utilized as it is as the wiring material for lead wires 30, 31 from the source and the drain, etc. Because the diffusion source is used as the wiring layer as it is, simplification of the process can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display panel substrate using an active matrix, which is applied to large-capacity displays such as liquid crystal displays, that is, an active matrix substrate.

Conventionally, time division driving has been performed in display panels such as liquid crystals. However, in this method, the time division duty ratio is limited to 1/16 to 1/32. On the other hand, with the development of information equipment, demand for display panels with increasingly high resolution display performance is becoming stronger. Such a high-resolution display requires at least 100 horizontal lines, and therefore requires a drive duty ratio greater than 1/100, but this cannot be achieved using the conventional time-division drive method. For example, television image display requires a resolution of at least 240 lines x 200 lines, which is an area that is quite difficult to achieve with conventional time-division driving methods. Therefore, for this improvement, active
A method called matrix drive has been considered. In this method, each pixel retains a charge, and display data is written to the pixel in a very short time, stored until the next 97 retrieval, and the liquid crystal is driven at the same time. A duty ratio of 11,500 or more is also possible.

The first diagram shows an active matrix -w system SE/I/1 using MOS transistor 4, and timing 4! ! 3 turns transistor 4 ON, 0IF
When F is controlled and turned ON, data is written into the capacitive liquid crystal 5 by data@2, and is held after oyF. Conventionally this MOS)
Although the transistor 4 has been formed on a single crystal 81 substrate,
For reasons such as difficulty in increasing the area, high cost, and low contrast, it has been proposed to use thin film transistors (TUFT) using amorphous silicon or polycrystalline silicon. However, since this method uses a low melting point substrate such as soda glass, the process temperature is low;
As in the past, phosphorus (P) was used as the source/drain diffusion layer.
Diffusion of non-blunt substances such as carbon dioxide and boron (B) is impossible using conventional thermal diffusion methods.

Further, the ion implantation method has the disadvantage that the equipment cost is high and the resistance of the diffusion layer cannot be lowered unless high temperature annealing is performed. As described above, the structure or manufacturing method of a transistor using a silicon thin film involves processes that cannot be realized using the same method as the conventional method of forming a MOS (MOS) transistor using single crystal silicon, and is also too complicated.

Therefore, an object of the present invention is to provide a TIFT using a silicon thin film with a simple process and an active matrix substrate using the TNT.

The present invention uses At or At alloy as an impurity source as a method for forming an impurity diffusion layer at a low temperature, and further uses this At or At alloy as an impurity diffusion source as it is in a line layer in order to simplify the process. It is something.

FIG. 2 shows an embodiment of the invention. A silicon thin film 21 is formed on a transparent substrate 2°, and a gate insulator M22 and a gate electrode material 25 are further deposited.

(a) After this, a gate electrode 25 is patterned, and a gate insulating film 24 is further formed using this gate electrode 25 as a mask. (b) After this, an alloy layer 26 of A4 or Aj-8i, which serves as a diffusion source and a wiring layer, is formed by vapor deposition or sputtering, and then heated at 300°C to 450°C for 5 minutes to 2 minutes.
By annealing for about 0 minutes, At diffuses as an impurity into the S1 film at a relatively low temperature. This uses the principle that kt diffuses at a relatively low temperature compared to conventional P and B because AL itself is a low melting point metal and has a low eutectic humidity with Sl. However, if the thickness of the At or At alloy layer is large compared to the thickness of the S1 film, 81 may diffuse into the At. It needs to be equal to or thinner. As a result, source/drain diffusion layers 27, 28 and channel 29
is formed.

(c) After this, the kl or At alloy layer used as the diffusion source is patterned to form lead lines 30.3 from the source/drain.
It can be used as is as a first class wiring material.

(b) As a result, the diffusion source can be used as it is as a wiring layer, making it possible to simplify the process.

FIG. 3 shows another embodiment of the invention. After depositing and patterning the silicon thin film 36 on the transparent substrate 35,
An insulating film serving as a gate insulating film is applied and patterned to form a gate film 57. (b) After this, annealing is performed at 300° C. to 450° C. for about 5 minutes to 20 minutes while the At or At alloy layer 37 is placed, and source/drain diffusion layers 39 and 40 are formed by low-temperature diffusion of Mut. Ru. At this time, the thickness of the S1 film is usually 300X to 1μ, and the thickness of the At layer is 2μ.
000 back ~s,, o o o l. (b) After this, the At layer is patterned, and the gate electrode 41 is formed at the same time as the wiring layers such as the source/drain leads 142 and 43. (c) After that, an interlayer insulating film, for example 810□ 45, is applied, and after contact holes 47 are opened, a transparent conductive film 46 such as Nesa, To, etc., which will become a liquid crystal drive electrode is formed. ) The advantage of this method is that the Mut'pkt alloy layer not only serves as an impurity diffusion source (P-type) and wiring layer, but can also serve as a gate electrode, compared to the method shown in Figure 2. It becomes possible to simplify the process.

4th v! J shows an example of an active matrix cell pattern 5o formed by the method shown in FIG.

After depositing an insulating film on the silicon thin film 53 and buttering it, game)! Form 1155 and its &A
or At alloy is deposited on the entire surface, and after impurity diffusion, patterning is performed to form gate electrode 54, data 11151, source-drain extraction &[56,5
form 7. After this, an interlayer insulating film is applied, contact holes 58 and 59 are opened, and a transparent conductive material is deposited thereon to form the tings 1152 and the liquid crystal drive electrodes 60.
form.

As described above, the present invention focuses on the low eutectic temperature of At and 81, and uses it as a low-temperature impurity diffusion source, and furthermore, the At or At alloy layer provided for this purpose is used as a wiring layer, and furthermore, as a gate electrode. By using it as a material, it will be possible to manufacture substrates for active matrix panels at low temperatures and in a simple process, and it will be effective in realizing large-capacity liquid crystal display panels using TIFT. be.

[Brief explanation of the drawing]

Figure 1 is an active matrix, Figure 2 is
FIG. 3 shows an example of the manufacturing process of an active matrix substrate including TPT according to the present invention. FIG. 4 shows an example of a pixel cell pattern obtained by the process shown in FIG. 4...TIFT 5...LCD 20,!
55...Transparent substrate 21.56.55...S1 film 22.37.55 Mountain gate film 25.54...Gate electrode 26.58...Member or At alloy 27.28.39.40 ...Impurity diffusion layer 45...
Interlayer insulating film 46.52.60... Transparent conductive material or above Applicant Suwa Seikosha Co., Ltd. Agent Patent attorney Tsutomu Mogami (d) Figure 2 (A) (Even 1; Figure 13 Figure 4

Claims (1)

[Claims] (1) Forming the source and drain of the TIPT in an active matrix substrate that controls writing or holding of display data from a data line to pixels arranged in a matrix by a timing line connected to the gate of a thin film transistor (TNT). 1. An active matrix substrate characterized in that At or k1 alloy is used as an impurity source for a diffusion layer in which a wiring layer is formed.