TW200425515A - Crystalline silicon TFT panel for LCD or OLED having a LDD region - Google Patents

Abstract

The present invention relates to a crystalline silicon TFT panel for LCD or OLED. According to the present invention, the pixel area of TFT panel is formed with a pixel transistor and a storage capacitor containing a crystalline silicon film using metal to activate the side crystal (MILC), and a low density doping area with dopant density below 1E14/cm2 is simultaneously formed at the periphery of channel for the pixel transistor, which can effectively reduce the OFF current of the pixel transistor. Thus, the present invention provides the benefits required by the semiconductor device, that is, the pixel transistor and the driving circuit for the TFT panel can be simultaneously produced with a relatively simple method, and individually satisfy the OFF current of ON current characteristics for the pixel transistor and the driving circuit, respectively.

Description

200425515 5. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a crystalline silicon thin film transistor (TF T) panel, which can be used in a TFT liquid crystal display (LCD) or an organic electroluminescent display (0ELD). The present invention provides a crystalline silicon thin film transistor (TFT) panel that can be used in a TFT LCD or an OELD. The pixel transistor located in the pixel region of the TFT panel and the driving transistor located in the peripheral region are simultaneously induced by the use of a metal to induce lateral crystallization (M). It is formed by the crystal stone of the ILC method, and it can satisfy the characteristics that the transistor needs a low off current (I off) in the pixel region and the transistor that forms the driving circuit in the peripheral region needs a high on current (I 〇n ) Characteristics. [Prior technology] This problem is related to the amorphous stone τ FT commonly used in traditional LCDs and 0 ELD. It is easy to be manufactured on glass substrates at temperatures below 350 ° C. However, due to the electronic swimming of amorphous stone The property is low, so that there is a problem that the amorphous chip TFT cannot be used in a circuit for high-speed operation. Furthermore, an amorphous TFT is used in the LCD, and a tape carrier package (TCP) is used to drive the IC. The pixel transistor can be formed in the substrate, and the glass substrate and the PCB can also be connected to each other around the substrate. Therefore, there will be other problems such as the need for additional drivers! The cost of c and women's clothing is increased. 'Another problem is that' due to mechanical and thermal shock, the connection between TCP drive 1C and PCB or the connection between TCP drive 1C and glass substrate is separate, or the connection part. The shrinkage resistance of the component will increase, and when the padpitch between the signal line and the scanning line becomes shorter, as the resolution of the LCD panel increases, TCP joining becomes difficult. & «u

Page 5 200425515 I 'V. Description of the invention (2) ^ With regard to LCDs using crystalline silicon TFTs, crystalline silicon can be used for LCD switching elements, etc., because the active layer of TFTs has good electronic mobility. And other driving circuits, and the pixel transistor and the driving transistor can be formed on the TFT panel at the same time. In addition, the crystallized TFT self-calibration (se 1 f-a 1 i gned) structure makes the crystalline silicon TFT's stage shift (1 eve 1 shift) electric dust lower than that of the amorphous crystalline TFT. Since the N-channel and P-channel used in the crystalline silicon of the crystal stone τ ρ τ I are formed, a CMOS circuit can be formed. In addition, because it is similar to the standard CMOS process for silicon wafers, the crystalline silicon T F T process can be used in semiconductor production lines. FIG. 1 is a schematic diagram of a TFT panel of the LCD 10, forming a pixel region I® 11 and a peripheral region such as a driving circuit region 12. A multi-pixel array including a pixel transistor, a storage capacitor, and the like are all formed in the pixel region, and a driving device for driving these pixels is formed in the driving circuit region 12. In crystallized 丨 -TFT LCDs, the analog circuit in the hybrid drive mode is like an operational amplifier (0P amPi if ier) or a digital analog & converter (DAC) that is difficult to manufacture for crystalline silicon TFTs and used as a separate product. Body circuits and switching units, such as multiplexers formed on a substrate, are usually used to replace all drivers on the substrate. Figure 2 is an equivalent circuit diagram of a unit pixel formed in the pixel area of the TFT panel of LCD10. Each unit pixel contains a data bus (V d), a gate bus (vg), a pixel transistor with a gate connected to the gate bus (Vg) 2 1. Connect to information The data bus line and the source (source) and drain ((11 ^ 11〇, ...) of the pixel electrode are used to maintain the signal state of the pixel transistor 21 until the next signal

Page 6 200425515 V. Description of the invention (3) The storage capacitor 22 (Cst) is coming and a liquid crystal injection unit 23 (CLC) connected in parallel to the storage capacitor 22. At the same time, the storage capacitor 22 and the liquid crystal injection unit 23 are respectively connected to a common electrode 24 (vcom). The pixel area and the driving circuit area of the crystal TFT panel of the LCD are formed on the common electrode at the same time. In order to effectively drive a driving device such as a switching device, the pixel area needs to have a low off current (I 0ff). The current that flows into the pixel transistor under the condition of high voltage and the surrounding area needs to have a high on-current (I ο η), such as the current that flows into the thin film transistor in the state where the gate voltage is used. Please refer to Figure 2. Especially, the off current of the pixel transistor 21 is very high. “Because the charge accumulated in the storage capacitor 22 leaks out, the driving voltage used to the liquid crystal injection unit 23 cannot be maintained until the next signal period. Therefore, The stability and consistency of the display are significantly reduced. The thin-film transistor system for TFT panels used in crystalline silicon LCDs is manufactured by the following methods. An amorphous silicon layer is first formed on a glass substrate, and then the amorphous silicon is solid phase crystallized (solid phase crystallization) and laser crystallized. 4 Crystallization by laser crystallization, direct deposition method, rapid thermal annealing (rapid thermal a η nea 1 ing), and other methods. A feature of the present invention is that the crystalline layer of the thin film transistor uses a metal induced lateral crystallization method (MILC) instead of the existing crystallization method of amorphous silicon. If the MI LC method is used, the crystalline silicon TF T has the advantage that it can be simultaneously formed in the pixel region and the peripheral region in a simple step at a lower temperature than the existing crystallization method. However, similar to the crystalline silicon crystallized by other methods, the crystalline silicon has a higher off-current than the amorphous stone by crystallization using the M I L C method. Especially for non-selection in the pixel area

Ν 4 Μ Page 7 200 ^ 25515 V. Description of the invention (4) During the period, there is no loss of the radio wave signal accumulated in the pixel, which is usually required at this time. The off current is lower than 1 E-1 1 A. However, using Μ The crystalline silicon TFT formed by the ILC method shows a good current characteristic and a poor off-current characteristic (that is, the off-current is relatively south). Therefore, ‘5 at this time has another disadvantage because it cannot meet the characteristics required by thin film transistors in the pixel region.’ For this ’, a structure and a manufacturing method of ^ crystallized T F T panel are needed.

The crystalline silicon TFT can be effectively formed simultaneously in the pixel region and the driving circuit region of the TFT panel of the crystalline silicon LCD, and can satisfy the conditions that the pixel region requires a low off current and the driving circuit region requires a high on current. [Summary of the Invention] As the defects of conventional technology need to be improved, the inventors have exhausted their mental research to overcome them, and have developed the crystalline silicon thin film transistor (T F T) panel of the present invention. Therefore, the main purpose of the present invention is to provide a thin film transistor (T-FT) panel, which uses a metal-induced lateral crystallization method (M ILC) to make a pixel transistor and a driving transistor including a crystalline silicon active layer. Simultaneously and separately formed in the pixel region and the driving circuit region of the TFT panel of the LCD or the OELD, and the characteristics of the off current and the on current in the pixel region and the driving circuit region can be satisfied separately and simultaneously. [Embodiment] Before the present invention is specifically described, a crystalline silicon thin film will be formed by ML LC.

200425515

5. Description of the invention (5) The manufacturing method of the film transistor is described below. A thin film transistor is used for a display device such as an LCD. It is manufactured in the following manner. First, silicon is deposited on a transparent substrate made of glass, quartz, etc., a gate electrode is formed thereon, and a dopant or dopant ( d 〇pants) implant the source and drain regions and activate the annealing step

Then, an insulating layer is formed thereon. The functional layer and the channel of the thin film transistor constituting the source and drain regions are generally made by depositing a stone layer on a transparent substrate made of glass by a chemical vapor deposition (CVD) method, sputtering, or the like. However, the silicon layer directly deposited on the substrate by the above method such as the C VD method is amorphous silicon, and thus the electron mobility is low. For example, a thin film transistor used in a display requires a fast operation speed and miniaturization, and the integration degree of the driving integrated circuit (ICs) increases and the aperture ratio (aperture r a t i) of the pixel region decreases. It is necessary to increase the electronic mobility of the silicon layer to simultaneously form the driving circuit and the pixel transistor and increase the pixel aperture ratio. Therefore, the amorphous silicon layer is processed by annealing (annealing), and the crystal has a high degree of electronic mobility. Crystalline silicon layer.

Therefore, various methods have been proposed to crystallize an amorphous silicon layer into a polycrystalline silicon layer of a thin film transistor. The solid phase crystallization (SPC) method anneals an amorphous silicon layer at a temperature below about 600 ° C for several hours to tens of hours, and the temperature below about 600 ° C is the transition temperature (Tg) of the glass constituting the substrate. ). Since the Shixi layer of the SPC method requires a long time thermal annealing, there is a problem of productivity, and if the substrate has a large area, a long time annealing treatment at a temperature below 600 ° C will cause the substrate to deform. The excimer laser crystallization method (ELC) uses an excimer laser beam to scan the silicon layer to locally generate a short-time high-temperature crystallizable silicon layer. However,

Page 9 200 ^ 25515 V. Description of the invention (6) The ELC method has technical problems that cannot accurately control laser beam scanning and manufacture only one substrate at a time. Therefore, the ELC method also has a defect that the productivity is lower than that of manufacturing a batch of substrates in the furnace.

In order to overcome the shortcomings of the traditional way of crystallizing the silicon layer, the phenomenon that when amorphous metals such as nickel, gold, and aluminum are injected into the amorphous silicon can cause the amorphous silicon phase to change into polycrystalline silicon at a low temperature of about 200 ° C, this phenomenon It is called metal-induced crystallization (M IC). In the thin film transistor manufactured by using this MIC phenomenon, a small amount of metal will remain in the polycrystalline silicon that constitutes the thin film transistor active layer, and therefore the problem of leakage current will occur in the channel of the thin film transistor. Recently, a method using a metal-induced lateral crystallization (M ILC) crystalline stone layer has been proposed. In this method, silicon is successfully induced to crystallize, and a metal silicide layer (si 1 pesticide), not to allow metals to directly induce phase changes in silicon (see SW · Lee & SK Joo, IEEE Electron

Device Lette's metal can be used for silicon crystalline metals due to the metal-containing r, 17 (4), p. Induced MILC. Mining components do not remain. Silicide sideways increase and Pd will not cause ML C to other operating characteristics of metals such as Ni active layers. Shi Xiyu can therefore damage another excellent substrate. Crystallization at about 300 to 600 ° C without a relatively low temperature for several substrates and 'induced crystallisation under MILC, causing damage to the substrate 160, 1996) MILC was used to pass the silicon layer through MILC The method has the advantage of the characteristics of the silicon layer junction leakage. Degrees of about 300 to 500 can be simultaneously in the furnace, so silicon can have the advantage of several pieces of damage, and even, nickel crystals crystallize and become thinner. In addition, crystalline one-phase substrates to the second layer at t, Colonization. Therefore, the membrane transistor can be induced to crystallize by ’without inhabiting. For lower temperature shoulders, a slope edge can be used in the furnace.

Page 10 200425515 V. Description of Invention (7) The same is true for the board. Figures 3A to 3D show the conventional steps of forming a crystal layer of a TFT using the MIC and MILC phenomena. As shown in Figure 3A, an amorphous second layer is deposited on an insulating substrate 30 having a buffer layer (not shown). Amorphous fragments are patterned by photolithography to form the active layer 31, and then a gate insulating layer 32 and a gate electrode 33 are formed in a manner commonly used at present. Subsequently, the gate insulating layer 32 is formed on the active layer 31. As shown in FIG. 3B, a source electrode region 31S, a channel region 31C, and a drain electrode are formed on the active layer 31 by doping dopants into the entire substrate of the gate electrode 33 as a photomask. Area 31D. As shown in FIG. 3C, a photoresist 3 4 (PR) covers the gate electrode 3 3. Some portions of the source region 3 1 S and portions of the drain region 3 1 D surround the gate electrode 3 3. Then, a The Jin Lu metal layer 35 is deposited on the entire surface of the photoresist and the substrate. As shown in Figure 3d, the photoresist 34 is removed and the entire surface is annealed at a temperature of 300 to 600 ° C. Therefore, the source and drain regions 36 directly above the residual metal layer 35 are controlled by The MIC phenomenon is crystallized, but the metal offset portion of the source and drain regions and the channel region 37 on the gate electrode are crystallized by the MIC phenomenon induced by the residual metal layer 35. As shown in FIGS. 3A to 3D, the photoresist-shaped source and drain regions 3 1 S and 3 1 D covering both ends of the gate electrode 3 3 are due to the residual metal component in the channel region 3 due to the MIC IC phenomenon. 1C and the boundary between the channel region 31C and the source / drain regions 3 1S, 3 1 D. However, if a metal layer is deposited on the boundary, a leakage current and a decrease in the operating characteristics of the paralytic region are formed. In order to solve this problem, a metal compensation region is formed around the channel region to prevent the channel region from being induced by metal. Except for the channel area, the source / drain area is not strongly affected by residual metal components △

Page 11 200425515 1-* 1 'V. The effect of the invention description (8) |-| However, considering the operation, the distance between the source and drain regions and the channel region I ^ is about 0.01 to 5 // m, making it Crystallization is caused by the M 1C phenomenon, and only the channel-region and the metal-compensated region are crystallized by the M I LC phenomenon, so that the crystallization of the transistor active layer requires less time. The characteristic of the present invention is to control the dopant concentration around the injection channel to improve the off-current characteristics of the transistor in the TFT panel, especially the pixel region for the crystalline silicon TFT drain current according to the method described in FIGS. 3A to 3D. Phenomenon, such as the on and off currents of transistors based on various dopant concentrations around the injection channel area. Table 1 shows the changes in the on-current and off-current according to the different dopant concentrations around the channel region of the thin-film transistor crystallized by M LC. Table 1 Dopant concentration around channel area {/ cm2} 5.00E12 1.00E13 1.00E14 3.00E15 Off current (A> 1.00E-12 5.00E-12 3.00E-11 5.00E-11 On current <A> 8.00E -15 2.00E-14 3.00E-04 5.00EM Switching current ratio 8.00E07 4.00E07 1.00E07 1.00E07 (with the width of the transistor W = 10 // m, length L = 6 / zm, VD = 10V, ON® current At the gate voltage VG = 2 0 V, the off current is measured at the gate voltage VG =-5 V) Figure 4 is a graph drawn in Table 1. As shown in Table 1, if injected through

Page 12 200425515 V. Description of the invention (9) The dopant concentration around the channel is increased, and the on-current and off-current of the drain electrode are both increased. If the dopant concentration is 5 · 0 0 E 1 2 / c m2, the off current and on current are 1. 0 0 E-1 2 and 8 · 0 0 E-1 5 respectively, and the switching current ratio is 8 · 0 0 E 0 7; However, if the doping-substance concentration is 3. 00E15 / cm2, the off and on currents are 5. 00E-11 and 5. · 0 0 E-0 4, respectively, and the switching current ratio is 1. · 0 0 E 0 7. It can be known from the above that when the dopant concentration around the injection channel is increased, the increase of the off current is higher than that of the on current. · As shown in Figure 4, the image formed in the pixel area of the TFT panel of the LCD. · The transistor needs to have an off current lower than IE-11 A and an on current higher than IE-5A. In the doping process of the drain electrode, the dopant concentration of the source region and the non-electrode region is generally lE14 / cm2 or higher. As shown in Tables 1 and 4, the on-current of the transistor at this concentration is higher than 1 E-5 A. Therefore, even if a dopant is injected into the channel region around the general doping process, the pixel transistor The characteristics required for the on-current can also be achieved. However, in order to maintain the electrical signal in the non-selected area of the pixel, the off-current of the pixel transistor needs to be lower than the threshold of 1 E- 1 1 A, and the implanted dopant concentration At 1E1 4 / cm2 or higher, the off current will be higher than the threshold. If the off-state current of the pixel transistor of the LCD is higher than 1 E- 1 1 A, there will be problems of daytime flicker and crosstalk. Therefore, the off-state current of the pixel transistor in a crystalline silicon TFT panel manufactured by M ILC must be continuously maintained. Below the threshold. As shown in Tables 1 and 4, if the dopants around the φ body channel of the thin film transistor manufactured by MILC are injected at 1 00E1 4 / cm2 or lower, the non-polarized current is reduced to less than 1. 0 0E- 1 1 A threshold value, so the effect of keeping the off current of the pixel transistor below the threshold value is to maintain the doping around the injection channel.

Page 13 200425515 I Description of the invention (10) Debris is less than 1 · 〇〇 El 4 / cm2. However, if a general process is used, it will be difficult to keep the dopant concentration lower than 1 · 〇〇E 丨 4 / c. To solve the problem, the feature of the invention is to form a low concentration around the transistor channel region. In the impurity region, if the concentration of the implanted dopant is lower than the LDD ^ yf (lightly doped drain, L igh 11 y-D 〇ped D rai η) of other active layers, the dopant concentration in this region is kept low. At 1.0E14 / cm2. A method for forming a lightly doped region in a f-transistor and a pixel transistor of a TFT panel according to the present invention is described below. _ Figures 5A to 5? Are diagrams of a method for simultaneously manufacturing a pixel transistor and a driving transistor by using MILC on a TFT panel according to the present invention. Although this embodiment describes forming a pixel transistor and a storage capacitor in a pixel region and forming a CMOS transistor in a driving region, the present invention is not limited thereto. Based on the fact that more than two TFTs can be formed in the pixel region and are used to drive U U Σ ρ ·: MOδ, N_MOS, CMOS, or a combination thereof. Although in this implementation, the crystal and the capacitor layer of the storage capacitor will be connected to each other, it is necessary to know that the pixel transistor and the capacitor layer of the storage capacitor do not necessarily need to be connected. Can form an electrical connection. In addition, although the electrode of the storage capacitor formed by this layer, other layers such as metal ^ tun pole, and those skilled in the art know that the layer composed of the same material 2 as the gate insulating layer, such as the intermediate insulating layer, forms storage. Capacitor mouth (Dielectric Layer ·). It is a cross-sectional view on the base of a shielding layer 51 for preventing the substrate 50 from spreading pollutants. The substrate 50 is made of transparent insulating materials such as glass-free glass, Shiyang, Digas, etc., and the shielding layer 51 is made of deposited oxygen.

200425515 V. Description of the invention (11)-Silicon oxide (Si〇2), silicon nitride (SiNx), silicon oxynitride (Si〇x can be added at a temperature of about 600 or less, and the thickness can be 300 to 100. 〇〇A or better is composed of 500 to 3 00 A composite materials, can use deposition methods such as electric beam assisted chemical vapor phase> PECVD, low-level chemical vapor deposition system (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), electron cyclotron resonance chemical vapor deposition (ECR-CVD), or sputtering. As shown in Figure 5B, an active layer constituting a thin film transistor An amorphous stone layer 52 (a-Si) is formed on the shielding layer 51. The amorphous stone layer 52 formed by amorphous silicon layer is deposited by PECVD, LPCVD, or a sputtering method, and has a thickness of 300 to 100, 〇〇〇A or better is 500 to 1000A. In order to form an N-MOS or a P-MOS in the pixel area and a CMOS for the driving device in the driving circuit area (as shown in Figure 5C), Photolithography was used to form the pattern, and the amorphous silicon was patterned using an etching gas plasma for dry etching. Figure 5B shows the pixel area and the driving circuit area interacting with each other. However, in an actual structure, an array of a plurality of unit pixels is formed in a pixel region and a driving circuit spaced from the unit pixel array is formed. At the same time, it can be seen that a unit pixel region and a driving circuit region are connected to each other to describe A method for manufacturing a pixel transistor and a driving transistor at the same time. In this embodiment, an amorphous silicon island 52P is formed in the pixel region 79 in order to form an N-MOS or a P-MOS. Two amorphous silicon islands 5 2 D of 0 S are formed in the driving circuit region 8. Although the CMOs are formed in the driving circuit region in this embodiment, a variety of driving circuits can be formed in the driving circuit region if necessary. , Such as N-MOS, P-MOS, CMOS, or a combination thereof. After the amorphous silicon layer 52 is patterned, a gate insulating layer is formed to form the gate insulating layer.

20 ^ 425515 I...

V. Description of the invention (12)-The upper insulating layer 53 and a gate electrode form a metal layer 54 thereon (as shown in Fig. 5C). By-depositing silicon dioxide (Si02), silicon nitride (SiNx), silicon oxynitride (SiOxNx) or a combination thereof to form the insulating layer 53, the thickness may be 300 to 3, 0 0 0 A or better 5 0 0 to 1, 0 0 0 A, by sputtering, evaporation, PECVD, LPCVD, APCVD, or ECR CVD and other deposition methods to deposit metal materials or conductive materials such as doped polycrystalline silicon to form the gate metal layer 5 4 On the insulation layer-53 'Thickness is 1,000 to 8,000 people or better is 2,000 to 4,000 in. Figures 5D and 5E are a process of forming a gate electrode 56 and a capacitor electrode 57 using a wet or dry etching step after the photoresist pattern 55 is formed. This photoresist pattern 55 is photolithographically The operation is formed on the gate metal layer 54 on the amorphous silicon island 5 2 p having a pixel transistor and the amorphous silicon island 5 21) having a driving transistor. As shown in the figure, three electrodes are formed in the pixel region, and a gate electrode is formed on the amorphous silicon island 52D on the left side of the driving circuit region. PR) 81 is covered to form CMOS. Two of the three left electrodes 56 are formed in the pixel region and are used to form a double gate electrode of the pixel transistor, and the other right electrode is used as an electrode of a storage capacitor connected to the pixel transistor. In each preferred embodiment, the double-gate electrode formed on the pixel transistor can reduce the power-off ^^ Because the interface between the source and the drain region is enlarged and the multi-gate $ is used, the electric field strength of the weak. Although in this embodiment, only two gates are formed in the structure, the driving transistor can use more or less than two gates = crystals, and more than two gates. As shown in Figure 5E, the preferred embodiment of the present invention has

Page 16 200425515 V. Description of the invention (13) The a distance # 8 2 of the deciding pattern passes through the undercut structure of the gate electrode w in the patterned photoresist. As described above, the gate electrode layer is over-etched to make LD]) (Lightiy

The Doped Drain) region is formed around the gate electrode of the transistor. &lt; FIG. 5F shows a state where a gate insulating layer 58 and a two-capacitor dielectric material layer 59 are formed by omnidirectionally etching the insulating layer 53, and a patterned photoresist is used as a photomask. As described above, the photoresist-resistant over-etched gate electrode, the gate insulating layer 58 and the | electrical material layer 59 have a wider width than the gate electrode 59 and the capacitor electrode M. FIG. 5G shows a process for removing photoresist and using a gate electrode as a photomask doped with dopants. First, the pixel transistor is doped with a high concentration of dopants at a low energy and the left driving transistor is not covered by photoresist. If as shown in the figure ^ 1108 7? 1 'manufacturing, with? 113? Or human 8 as the dopant (1) 〇1) 3111 :), the doping dose is about 1E14 to 1E22 / cm3 (preferably 1E15 to 1E21 / cm3), and the energy is 10 to 100KeV (preferably i. s100KeV) and use a large amount of doping (shower doping) or ion implantation method (i0I1 implantation method); however, if p-MOS TFT is manufactured, b2h6, B or Ms is used as the dopant (Dopant), the doping dose About i E1 3 to

lE22 / cm3 (preferably 1E14 to 1E2 1 / cm3) and energy of 10 to 70KeV (preferably 10 to 3 OKeV). Figure 5G shows the process for implanting N-type dopants. Because the high-concentration dopants are doped with low energy, the source and drain regions of the thin-film transistor are not penetrated through the gate insulation layer, and the dopants are implanted only in the area covered by the gate insulation layer. According to the present invention, since the gate insulating layer of a pixel transistor is wider than the gate electrode, it is prevented from being doped at a high concentration and low energy.

Page 17 20Q425515 V. Description of the invention (14) The impurity dopant is implanted in the low-dose-dosage area of Shixi, and the first description is the N-type seeding of high-energy and low-concentration dopant. The doped agent is 150 K eV. The conditions are as follows: two energies B or BH3 are used as dopants with a low level of 20 to 1000KeV, and the degree of impurity replacement is 60%. If the dopant area can be mixed with the above-mentioned technique, the dopant driving circuit will not form a low-concentration dopant driving circuit around the gate channel without doping. The 0 layer in the dopant has a gate as follows. The amount of impurities before being mixed is about 8 4 0. The gate layer is covered with a large amount of low-concentration doping conditions, and the high-dopant low-energy is used to change the low-concentration doped insulating layer. An insulating layer with a low dopant is formed around the channel. A metal is formed around the channel area to perform low-energy horsepower doping. The N-MOS TFT is then doped with 1E11 to 1E20 / cm3 with ph3, P, or AS. The energy is 50 to doping, ion implantation, or other ion implantation doping; P-MOS TFTs are doped with B2H6 at a dose of about 1E11 to iE20 / cm3 with high energy and low concentration. The gate electrode drive circuit area with low concentration doping with sufficient energy level of the insulating layer forms a low concentration to control the dose of dopants, and the injection low concentration is controlled below 1 E1 4 / cm2. South concentration is doped with high energy and low concentration, but the series is mature. If a high concentration dopant is implanted at a high energy, a high concentration dopant is implanted into the silicon layer, so the doped region is passed. If high is deleted from the above process, a complementary interface is formed in the thin chirped crystal channel to replace the low-concentration doped region. In addition, a low-energy high-concentration doping method can be used. A doping method can be used to control the doping energy so that the layer can be confined and only a part of the dopants can be implanted into the silicon layer.

Page 18 200425515 V. Description of the invention (15) ^ If the low-concentration doped region or the abutment surface; and the channel, the transistor's off-current can be reduced and its formation in the non-polar region is adjacent to achieve this purpose, low concentration The doped ^ domain is also very stable. It is a width of 1, 0 0 0 to 2 0, 0 0 0 A, and it is preferable that the shimming contact surface is formed to have a low pixel crystal off current to 1 Ε -1 1 Α or less', Note f 2 〇, Qu 〇 0 0 Α. In order to reduce the dopant concentration, it is controlled below 1E14 / cm2. A low-concentration doped region is formed in both the crystal and the driving transistor of the f * concentration-doped region of the clay. ^ The off current of the driving transistor does not need to be limited like a pixel transistor, so a low-concentration doped region may not be formed in the driving transistor. 'After the process of the 5G picture', the insulating layer 5 8 and the gate electrode 5 6 are formed and closed in the above-mentioned manner. The eye diagram, 5 D and 5 F are formed in the entire pixel area and are formed in a photoresist ( PR) The driving area covered by 8 1 (as shown in Figure 5 η = the transistor on the other side of the CMOS transistor (the preferred embodiment is a ν-type transistor), P is formed on the side of the CMOS transistor -Type transistor. Although this embodiment describes that in order to form a CMOS transistor in the driving area, first form a ^ -type transistor and then a P-type transistor, but the order in which the transistors are formed can be changed. See Figure 5I The photoresist located on the gate electrode is etched back to make the photoresistor width equal to the gate electrode. Please refer to Figure 5J. After the gate insulating film and the C MOS transistor gate electrode are on one side, such as a P-type transistor Form a pattern (as shown in Fig. 51) 'Replacement of relative polarity (such as P-type) to other transistors that make up the C M 0 S transistor is first doped at a high concentration and low energy and then doped at a low concentration High energy, refer to the conditions in Figure 5 G. As mentioned above, the dopant is doped through the gate at a low concentration and high energy. Xi injection stone layer insulating layer, and therefore, low concentration impurity regions

Page 19 200425515 V. Description of the invention (16) Formed around the P-type transistor channel area. Set the concentration of the impurity to 83 and high. Chen Du pushes the miscellaneous area. Although the transistors are all formed with low concentration, the current characteristics do not require the formation of low-concentration doped regions. Refer to Figure 5K, shifted to Figure 5L, which shows a manufacturing step of MILC induced by a substrate followed by a metal. Can induce (Ni), palladium (Pd),

Sn \ Sb &gt; In the examples of Cu, Co, Cr, the metal using Ni as the image, such as Ni, Pd, can be applied to the active layer, but the thickness of the metal layer is sufficient to induce the selection such as 1 to 10, 0 0 〇 A, please refer to Fig. 5L. — The general compensation area of each transistor on the metal plate that induces MILC 6 1 can prevent the operating characteristics. The metal is directly deposited in the area of Ni 5 8 p-type dopants. The low-energy energy and low-concentration doping 84 i sequence change was performed, and in addition, a complementary contact surface was formed around the channel to replace the ",", and this example is described in the pixel transistor and the driver f ϋ 然而: The solar body, therefore, does not drive the photoresist in the transistor. The photoresist used as a photomask in the doping process is removed; and the photoresist is removed from the entire pixel and the moving area. Crystallization: The metal that MILc caused by silicon contains nickel. In addition, T ·, Tr, Ru can also be used to induce MILC phenomenon. It is now commonly used through sputtering, gamma method, PECVD, and ^ Amorphous stone layer: by plating method ... 2 is preferred, 10] = 0 range of phenomenon Ren Si ’s gate insulation A j A. The entire place of the deposition J covers the periphery of the channel, so m, m, and the compensation region 61 are formed around the base region. As shown in Figures 3A to 3D, gold metal Leakage and reduction of components around the channel can induce a silicon layer on a metal that induces M I LC, such as the generation of M IC phenomenon. In this embodiment, a shape

Ag Cd

Au, A1, Pt, etc.

Page 20 200425515 V. Description of the invention (17) The gate insulating layer of the ΐΐ Γ electrode simultaneously forms a low-concentration doped Ϊ complement region around the channel region. Therefore, the low-concentration doped region 60 and the subordinate compensation region 61 are formed on Same area. Although this embodiment describes the use of a patterned gate insulating layer to form a low-concentration doped region and a metal region, it is intended to compensate the region by photo-blocking light before inducing the use of MILC metal (such as the first 3)). Therefore, low-concentration europium, the metal-compensated regions of region 14 do not necessarily overlap each other in the same region, and low-concentration doped regions may form part of the metal-compensated regions, and vice versa

— After applying N i to the transistor in the pixel region and the driving region, an annealing step is performed on the crystalline transistor active layer (see FIG. 5M). According to any method provided by the amorphous silicon induced by the M I L C phenomenon to perform crystallization-annealing, such as a rapid thermal annealing method (R τ Α), the active layer is applied for a short time of several seconds to several minutes. Occasionally, a halogen-tungsten lamp or a xenon lamp is used as a heating source, and the temperature is 500 ° to 12 ° ° C: or the active layer is heated by an excimer laser for a very long time by the ε L C method. Short time. In the present invention, the temperature of the silicon crystal in the furnace is 40 to

Heating at 600 ° C. for from 0.1 to 500 hours, more preferably from 0.5 to 20 hours. Since the temperature of crystallization of amorphous stone in the furnace is lower than the glass transition temperature of the glass substrate, any deformation or damage of the substrate can be prevented. Since a large number of substrates can be fired in the furnace at the same time, a large number of processes can be applied and the production efficiency can be increased. The induced metal ^ is deposited on the amorphous silicon region through the annealing step to crystallize by the M & C phenomenon ', and the metal-free region is crystallized by the \ ILC phenomenon spreading from the metal-using region. According to the present invention, since the annealing conditions for inducing amorphous silicon crystallization by MILC are similar to the annealing bars for activating the inducer of the implantation layer

200425515

V. Description of the invention (18) # crystallization and dopant of the active layer are performed in a single step. The other iSi layer that stores the drain of the U! Crystal and is formed on the outside of the pixel transistor is also annealed at the same time. This issue: ^ ^ means that the storage capacitor and the pixel transistor pass through the same steps at the same time, considering the day g and the 4th day of the rib. Farther than the same steps, the Japanese car fights and has the same structure. Because it is like: = u day inch crystal seconds, the dielectric layer 5 9 made by J Hezheng is fixed on the phase layer 5 with excellent electronic inscription. The junction between the electric mobility and the capacitor electrode 57 made of the same material as the gate electrode = Zi Yuangu has good electrostatic capacitance and electrostatic characteristics. ^ Referring to FIG. 5N, an intermediate insulating layer 62 is formed on the substrate and the pixels and driving regions of the substrate. The intermediate insulating layer 62 is formed by pECVD, &quot; WCVD, APCVD, ECR CVD, or sputtering. It is made by crystallizing silicon, lice silicon, silicon oxynitride, or a mixture thereof by other deposition methods, and has a thickness of 丨 10,000 to 15,000 A, preferably 3,000 to 7,000. A. Referring to FIG. 50, the contact electrode 63 is formed, and photolithography is used as a photomask to form a pattern. A wet or dry silver-etched intermediate insulating layer is used to form a contact hole (C ο ntacth ο 1 e). The electrode 63 can connect the source, the drain and the gate of the transistor to an external circuit, and the contact electrode 63 can be formed by depositing a metal or a conductive material such as sputtering, evaporation, and CVD, such as doping polycrystalline silicon. To the entire intermediate insulating layer with a thickness of 5 0 to 1 0, 0 0 A, preferably 2 0 0 to 6 0 0 A, and then the metal or conductive material is dry or wet Make the desired shape pattern in the engraved way. Subsequently, an insulating film 64 covering the contact electrode 63 is formed and then patterned in a general manner. A pixel electrode 65 for the electric field of the liquid crystal of the LCD unit pixel is formed in the pixel transistor region. Therefore, complete the TFT panel of the LCD

Page 22 200425515 V. Description of the invention (19) (as shown in Figure 5P) 'According to the aforementioned manufacturing method, the crystalline pixel transistor with two bucket electrodes and the storage connected to the pixel transistor are extremely useful for using MILC The pixel area of the LCD substrate, and the crystal drive / shape is CMOS, is formed in the pixel area at the same time using a low temperature step. Bright body The present invention describes the TFT panel of L C D, however, the TFT panel for 0ELD of the present invention does not need any modification and change. Figure 6A is a voltage-driven TFT panel effect circuit. Each unit pixel contains an information data bank (two rows H), a gate bus line (Vg), and one including j (Gate of Vd line and connection to information and data sink (switching technology) TFT 7 丨. Set 7 line f source and drain to a signal of 1 to the next signal coming T 7j = The gate electrode of the TFT driving TFT 73 and the holding addressing TFT are used to receive the table. | 2 Asia Union, and the driving voltage electrocoating (Vdd) of one pixel sub-luminous material output organic electro-optic, so only one applies the voltage to C. Since TFT LCD is not a self-generating pixel, however, since the pixel TF T of the element electrode is only sufficient to guide the organic electronic light emitter 桠 = alum voltage, OLED cannot be obtained — so additional use is needed as acceptance; The voltage level of the phenomenon, the pixel drives TF τ 7 3. The output of the addressing TFT 7 of the closed-pole signal is shown in Figure 6B, which is the equivalent circuit diagram of Cao Yuan pixels; Pixels with two addressing TFTs The unit 78 of the TFT panel of 0ELD and a storage capacitor 76. The first eight, 75, two pixel driving TFT 77, and the signal from the cable (Vgl) are printed as $ fTFT 74, which is passed through the first gate bus to accept a Information bus

20Q425515 I Le Wu, Invention Description (20) line (V d) message, and the second addressing TFT 75 is turned on to provide the first addressing TFT through the signal from the second gate bus (Vg2). The output of 74 is to the gates and storage capacitors 76 of the pixel driving TFTs 77 and 78. When the first-addressed TFT 74 and the second-addressed TFT 75 are turned on, electric charges are accumulated in the storage capacitors 76 which generate voltages in turn. Subsequently, the driving voltage is applied to the gates of the first and second pixel driving TFTs 77 and 78. Even if the second addressing TFT 75 is turned on, the voltage is applied to the storage capacitor to keep the pixel driving TF T 7 7 and 7 8 turned on until During another signal period, the driving current can be continuously provided to the unit pixels of the OELD.

In the crystalline silicon TFT panel of OELD, the pixel region and the peripheral region are formed on a common substrate at the same time. In order to effectively drive a driving circuit such as a switching device, the pixel region needs to have a low off current (I 0f ί), such as no gate voltage. State, current flows to the pixel transistor (hereinafter, the pixel transistor of OELD is considered to include addressing TFT and pixel driving TFT, unless they are opposite), and the surrounding area needs to have a high on current (I on), such as the gate When a voltage is used, a current flows to the thin film transistor. In the crystalline silicon TFT panel of OELD, the off-current of the thin-film transistor that directly supplies current to the storage capacitor is preferably lower than 1E-11A, especially the addressing TFT 71 in FIG. 2A and the second addressing TFT 75 in FIG. 2B. . If the off current of the addressing TFT is higher than 1E-1 1 A, even if the output of the addressing TFT 71 in FIG. 2A and the second addressing TFT 75 in FIG. 2B cause the individual potentials of the storage capacitors 7 2 and 7 6, they cannot be maintained. The charge is accumulated until the next signal period. Therefore, there is a problem that the gate potential of the pixel driving TTF cannot be maintained, and the on state of the pixel driving TFT cannot be maintained. Despite its good on-current characteristics, polycrystalline silicon is crystallized as M I L C

Page 24 200425515 V. Description of the invention (21) TFT has a relatively high off-current, but according to the formation of an LDD region in a elementary transistor, it is possible to resolve the problem ^ ^ ^

Forming the -LDD region can directly provide current: Yu image: Bar J = address TFT can maintain the lightning created by the storage capacitor H at Λ, 5A, 50 ®,, ^ t Ϊ ^ τ ^ τ. However, other pixel transistors can also be formed in the pixel region according to this condition, and in the manufacturing method described above, in order to induce the crystallization of the amorphous silicon layer, the low temperature crystalline N 1 is applied to the amorphous silicon layer to guide the heat treatment. On this day ^ ^ is applied to amorphous silicon with N 1, and the substrate is heated at 2000 to 700, it reacts with silicon in Ni & amorphous silicon to produce silicide of metal in &amp; well step, Ν 丨 ^ ^ On the gate oxide layer and the gate metal remains in a metallic state. When or before the crystallization heat treatment, the silicide of the metal formed on the surface of the amorphous silicon is not oxidized when exposed to the atmosphere, so that the problem of the deterioration of the crystal quality of the stone can be prevented by the oxidation of the metal that induces crystallization. Since it remains as a metal-like impurity, Ni deposited on other parts can be selectively removed by conventional etching. / pk After the Ni layer is deposited, an etching step is immediately conducted to form a non-a thin and uniform Ni layer. While depositing the ni layer on the silicon, a very thin nickel silicide layer is formed by inverse of Shi Xi In addition, during the etching step, it cannot be removed: the excess Ni of nickel silicide is formed, and the Ni layer deposited on other electrodes such as gate electrodes or substrates can be completely removed. The thickness of about 1 A is very thin, and the silicidated 7-foot knife is enough to cause the M I LC of the amorphous layer. Money-cutting reagents in nickel and / or metal records

Μ

Page 25 200425515 V. Description of the invention (22) There is selectivity. For example, ferric chloride, 1 HC 03/5 HC 1, 1 5 0 C H3 C 0 0 Η / 5 0 HN03 / 3HC1 can be used as an etchant. Using this method, the milc source metal remaining in Shi Xi (such as N i) can be minimized. A certain amount of boron is injected into the amorphous silicon to conduct the heat treatment in advance, and the crystallization speed and crystalline quality, such as the grain size and crystalline consistency, obtained by the M I LC have been significantly improved. Therefore, when the N-type TFT is manufactured, the N is implanted. Before or after the type dopant, boron is implanted into at least a part of the amorphous silicon layer, which can effectively improve the speed and quality of crystallization through the M ILC. In addition, the concentration is more than 1 X 1 013 / cm2. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of implementation of the present invention. Any person skilled in the art can make some modifications and decorations without departing from the spirit and scope of the present invention. And all equal changes and modifications made in accordance with the present invention shall be covered by the scope of patent application of the present invention, and the definition shall be subject to the scope of patent application. Although two gate electrodes are formed in the pixel transistor in this embodiment, more gate electrodes can be formed within the scope of the present invention, and although C MOS is formed in the driving area, the driving circuit includes various Thin film transistors such as P-M0S, N-M0S and CMOS, or a combination thereof, can be formed in the driving region. In addition, although a single gate electrode is formed in the driving transistor described in this embodiment, it may also include more than two Gate electrode. In addition, although it is described that the N-TF T and PTFT are formed separately and the dopants are also implanted separately ν — τ ρ τ and P-TFT, but the gate pattern can be formed at the same time as N — TFT and ρ — TFT, When N, -TFT dopants are implanted, N-TFT region can be formed with photoresist as photomask, and ρ -τρτ region can be formed with photoresist as photomask. N-TFT and P-TFT can be formed. Of course, if

Page 26 200425515 V. Description of the invention (23) Some TFTs, such as pixel transistors and driving transistors, are formed using only one type of TFT. These additional photomask steps are not required. Therefore, although the electrode describing the storage capacitor is formed of crystalline silicon, the electrode may be replaced by another layer such as a metal layer. Those skilled in the art can use a material different from the gate insulating layer to make a layer, such as an intermediate insulating layer, to form a dielectric layer of a storage capacitor.

As mentioned above, according to the present invention, a pixel transistor, a storage capacitor, and a driving device can be formed at the same time at a low temperature, so that a substrate such as an LCD or an OELD is not damaged. And because a low-concentration doped region and a metal compensation region are formed around the channel of the pixel transistor and the driving transistor of the TFT panel of the present invention, the on-current characteristics of the pixel transistor and the driving device of the LCD or 0ELD can be achieved, The off current can also be effectively reduced to the required level.

20q425515 f on page 27, the diagram is briefly explained. The first diagram is a schematic diagram of the position of the TFT panel area of the LCD. The second diagram is an equivalent circuit diagram showing the structure of a unit pixel formed on the TFT panel of the LCD. Section 3A Figures to 3D are cross-sectional views of a conventional method for manufacturing thin-film transistors using MILC. Figure 4 is a variation of the drain current based on the dopant concentration injected into the metal displacement region of the TFT manufactured by M ILC. FIG. 5A to FIG. 5P are process diagrams of manufacturing a crystalline silicon TFT panel for an LCD according to the present invention

Figure 6A is an equivalent circuit diagram of the structure of a TFT panel unit pixel of OELD. Figure 6B is an equivalent circuit diagram of the structure of a TFT panel unit pixel of OELD. Figure No. Brief description: LCD ... 10 pixel area. .... 11 Drive circuit area ··· 1 2 pixel transistor ··· 2 1 storage capacitors ... 22 LCD injection unit ··· 2 3 common electrode ... 24 insulating substrate .. ... 30

Action layer ... 31 Channel area ... 31C

Drain area 3 1 D source area 3 1 S gate insulation layer 3 gate electrode ... 33 photoresistor ... 3 4 Residual metal layer ... 3 5 source and drain areas ... 36 channel area ... 37 substrate ... 50 shielding layer ... 51

Page 28 200425515 Schematic illustration of amorphous silicon layer · · · amorphous silicon island · · · metal layer · · · · gate electrode · · · gate insulating layer · low concentration doped region · intermediate insulating layer · · Insulating film · · · Addressing TFT · · Pixel driving TFT Addressing TFT · · Pixel driving TFT Pixel area · · · Photoresistor ... Area of low energy and high concentration doped with Ni directly deposited 2P 46802413579135 5255566677777888 .5 .. ............ Amorphous islands · Insulating layers · Photoresist patterns · Capacitor electrodes · Dielectric material layers · Metal compensation area contact electrodes · Pixel electrodes · Storage capacitors Addressing TFTs Storage capacitors Pixel driving TFT driving circuit area a distance. High energy low concentration doping

5 2 D 5 5 5 6 6 7 7 7 7 8 8 8 5 7 9 5 2 4 6 8 0 2 4

Page 29

Claims (1)

200425515 6. Scope of patent application 1 · A crystalline silicon thin film transistor (TFT) panel for TFT LCD or 0ELD, which includes: a transparent substrate including a pixel region with several unit pixels and a driving circuit region; At least one pixel transistor is formed in each unit pixel of the pixel region on the substrate and includes a crystalline silicon active layer, a gate insulating layer, and a gate electrode, respectively. The active layer is metal-induced lateral crystallization (M I LC) crystal, a storage capacitor, formed in each unit pixel on the substrate; a plurality of driving transistors, formed in the driving circuit area on the substrate, and each including a crystalline silicon acting layer crystallized in M ILC, a gate An insulating layer and a gate electrode; wherein, a low-concentration doped region implanted with a low-concentration dopant, or a complementary contact surface without implanted dopants is formed around a channel of at least one pixel transistor. 2. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the application, wherein the low-concentration doped region is formed under a gate insulating layer of a pixel transistor. 3. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the scope of the patent application, wherein the concentration doped region is from 10,000 to 20,000. 4. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the scope of the patent application, wherein the dopant concentration implanted into the concentration doped region is 1E 14 / cm2 or less. 5 · Crystalline Silicon Thin Film Transistor (TFT) Panels such as those in the first patent application Page 30 200425515 6. Scope of patent application. One of the metal compensation areas that does not contain MILC-inducing metal material is formed around the channel of the pixel transistor. 6. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the application, wherein the low-concentration doped region is also formed in the driving transistor. 7. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the patent application, wherein two or more gate electrodes are formed in the pixel transistor. 8. For example, the crystalline silicon thin film. Transistor (TFT) panel of the patent application, wherein the transparent substrate is a glass substrate. 9. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the patent application scope, wherein the storage capacitor includes a crystalline silicon layer crystallized in M ILC and a dielectric layer and a dielectric layer subsequently formed on the crystalline silicon layer. Capacitive electrode, the crystalline silicon layer of the pixel transistor and the crystalline silicon layer of the storage capacitor are connected to each other, the gate insulating layer of the pixel transistor and the dielectric layer of the capacitor are formed of different materials at the same time, and the gate electrode of the pixel transistor and the capacitor The electrodes are formed simultaneously from different materials. 10. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the application, wherein the image transistor is composed of N-MOS or P-M0S, and the driving transistor is composed of CMOS. 1 1. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the patent application scope, wherein the gate insulating layer of the pixel transistor is at least wider than a gate electrode, and a gate insulating layer is used in a low-concentration doped region It is formed as a photomask by low energy and high concentration doping, and by using a gate electrode as a photomask and high energy and low concentration doping. 1 2 · If the patent application scope of item 1 of the crystalline chopped film transistor (T F T) surface Page 31, 200425515 VI. Patent application board, in which M ILC is applied to an amorphous silicon layer through a metal that induces M ILC, and the gate insulating layer of the pixel transistor and the driving transistor is wider than the gate electrode, and then The gate electrode and the gate insulating layer are annealed in a state where they are used as a photomask. 1 3. The crystalline silicon thin film transistor (TFTT) panel according to item 12 of the patent application scope, wherein the MILC-inducing metal used for doping includes at least Ni, Pd, Ti, hg, Au, A1, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt. The thickness is 1 to 200A. The sputtering method, evaporation method or CVD method is used and the annealing step is performed in the furnace at a temperature of 4 0 to 6 0 0. ° C for 0.1 to 50 hours. 14. If the crystalline silicon thin film transistor (TFT) panel of item 1 of the scope of patent application, wherein a shielding layer to prevent the diffusion of dopants is formed on the transparent substrate 15 The pixel transistor includes at least one pixel driving transistor and at least one addressing transistor flowing to the storage capacitor. 16. The crystallization plate according to item 1 of the scope of patent application, in which the active layer of the pixel transistor is crystallized, and at the same time, the substrate is heated by a heat treatment on a warm plate. 17. The crystalline plate according to item 1 of the scope of patent application, wherein the active layer of the pixel transistor is made of ferric chloride, 1HC03 / 5HC1 Silicon thin film transistor (TFT) surface One addressing transistor, at least one with several gate electrodes can provide a silicon thin film transistor (TFT) surface by depositing one μI LC source metal degree 2 0 to 7 0 ° C The silicon substrate thin film transistor (TFT) surface is guided by a nickel layer deposited thereon to form a junction. 1 50CHUCOOH / 50HNOq / 3HCl Page 32 200425515 6. Scope of patent application Selecting an etchant to etch the deposited nickel layer; and heat-treating a substrate. 1 8. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the patent application scope, wherein the boron concentration of the active layer injected into the pixel transistor exceeds 1 X 1 before a heat treatment is induced to induce the active layer to perform MI LC 013 / cm2. Page 33