TWI229943B - Crystalline silicon TFT panel for LCD or OELD having an LDD region - Google Patents

Abstract

The present invention relates to a crystalline silicon TFT panel for LCD or an OELD. According to the present invention, a pixel transistor and a storage capacitor, which include a crystalline silicon thin film, are formed at a pixel region of the TFT panel using MILC, and a low-concentration doped region having an impurity concentration of 1E14/cm<2> or less is simultaneously formed around the channel region of the pixel transistor so as to effectively lower an off current of the pixel transistor. Thus, the present invention has an advantage in that semiconductor devices required in the pixel region and the driving circuit region of the TFT panel can be simultaneously fabricated through a relatively simple process, and thus, an off current characteristic and an on current characteristic that are required in the pixel region and the driving circuit region, respectively, can be simultaneously satisfied.

Description

1229943 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a crystalline silicon thin film transistor (τ F T) panel, which can be used in a TFT liquid crystal display (LCD) or an organic electroluminescent display (OELD). In the present invention, a crystalline silicon thin film transistor (TFT) panel that can be used in a TFT LCD or OELD, wherein a pixel transistor located in a pixel region of a τ FT panel and a driving transistor located in a peripheral region are simultaneously induced by using metal to induce lateral crystallization ( It is formed by crystalline silicon based on the M I LC) method, which can satisfy the characteristics that the transistor requires a low off current (I off) in the pixel region and the transistor that forms the driving circuit in the peripheral region needs a high on current (I on ) Characteristics. [Prior technology] This problem is related to the amorphous silicon TFTs commonly used in traditional LCDs and 0ELDs. It is easy to manufacture glass substrates at temperatures below 350 ° C. However, due to the low electronic mobility of amorphous silicon, A problem arises in that amorphous silicon TF T cannot be used in circuits that operate at high speed. Furthermore, an amorphous silicon TFT is used in the LCD, and a tape carrier package (TCP) is used to drive the 1C. The pixel transistor can be formed in the substrate, and the glass substrate and the PCB can also be connected to each other around the substrate. Therefore, there are other problems such as the need for additional driver ICs and increased installation costs. Another problem is that due to mechanical and thermal shock, the connection between TCP driver 1C and PCB or between TCP driver 1C and glass substrate. The connection part is separated, or the shrinkage resistance of the connection part increases, and when the pad interval (pa dpit ch) between the signal line and the scanning line becomes shorter, such as an LCD panel As the resolution increases, TCP joining becomes difficult.

1229943 V. Description of the invention (2) Regarding LCDs using crystalline silicon TFTs, because crystalline silicon constitutes the active layer of TFTs and has good electronic mobility, crystalline silicon can be used in driving circuits for switching elements of LCDs, etc. The crystal and the driving transistor can be formed on the TFT panel at the same time. In addition, due to the self-al igned structure of the crystalline silicon TFT, the level shift voltage of the crystalline silicon TFT is lower than that of the amorphous silicon TF T, and also due to the crystallization of the crystalline silicon TF τ The N-channel and P-channel used in Shi Xi are formed, so a CMOS circuit can be formed. In addition, because it is similar to the standard CMOS process for silicon wafers, the crystalline TFT process can be used in semiconductor production lines. u is a schematic diagram of a TFT panel of the LCD 10, which forms a pixel region U and an edge region such as a driving circuit region. Containing prime, 2, storage capacitors, etc. are formed in the pixel area &quot; Medium: 2 τίτ (OP ampl if drive analogy circuit is like an operational amplifier converter (DAC) 'It is difficult to manufacture and used in The integrated circuit and the switching unit of the multiplexed and separated crystalline silicon TFT on the substrate are formed in a mobile device. / 通 # is used to replace all the drivers that are formed on the substrate. The picture is / pixels, etc. The effective power is converted into a unit (Vd) of the pixel area of the MLCD102 TFT panel, an nf. Each unit pixel includes a data bus line (Vg ^ bus line (vg)), and one has a bus connected to the gate The pixel transistor 21 of the cable and the idle pole connected to the information material is used to maintain the source. The source and drain of the electrode (dra i Π), a signal for the pixel transistor 21 Status until next news

1229943 V. Description of the invention (3) The storage capacitor 2 2 (C s) is coming and a liquid crystal injection unit 23 (CLC) connected in parallel to the storage capacitor 2 2. At the same time, the storage capacitor 22 and the liquid crystal injection unit 23 are connected to a common electrode 24 (Vcom), respectively. In the crystalline silicon TFT panel of LCD, the pixel region and the driving circuit region are formed on a common electrode at the same time. In order to effectively drive a driving device such as a switching device, the pixel region needs to have a low off current (I 0ff). The current flowing into the pixel transistor in the state, and the surrounding area needs to have a high on-current (I ο η), such as the current flowing into the thin film transistor in the state where the gate voltage is used. Please refer to Figure 2. Especially, the off current of the pixel transistor 21 is very high. Due to the charge leakage accumulated in the storage capacitor 22, the driving voltage used to the liquid crystal injection unit 23 cannot be maintained until the next signal period. The stability and consistency of the display are significantly reduced. A thin-film transistor system for a TFT panel for a crystalline silicon LCD is manufactured by the following method. An amorphous silicon layer is first formed on a glass substrate, and then the amorphous silicon is crystallized in a solid phase (S 〇1 id P hase Crysta 1 1 izati ο η), laser crystallization (Laser Crystallization), direct deposition method (Direct Deposition Method), rapid thermal annealing (rapid thermal a nea nea 1 ing) and other methods of crystallization. A feature of the present invention is that the active layer crystallization of a thin film transistor uses a metal-induced lateral crystallization method (ML LC) to replace the existing crystallization method of amorphous stone. Right 1 more M 1 L·L ~ ... π π 日 日 丄 i . 丄 ～ 你 班 现 3 ί ί ΐ ΪCompared with lower temperature, you can get the same day in one simple step: ^ The advantages of the prime region and the surrounding region. 'However, similar to Sayou ^ crystalline silicon, crystalline silicon uses the MlLc method ^; silicon has a constant off current. In particular, for non-selected

Page 7 1229943 V. Description of the invention (4) During the period, the radio wave signal accumulated in the pixel is not lost. At this time, the off current is usually lower than 1 E-1 1 A. However, the crystalline silicon formed by the M ILC method TF T shows a good current characteristic and a poor off-current characteristic (that is, the off-current is relatively high). Therefore, at this time, there is another disadvantage, that is, the characteristics required for the thin film transistor in the pixel region cannot be met. To this end, a structure and manufacturing method of a crystalline silicon TFT panel are needed, so that the crystalline silicon TFT can be effectively formed at the same time. The pixel region and the driving circuit region of the TFT panel of the crystalline silicon LCD can simultaneously satisfy the conditions that the pixel region requires a low off current and the driving circuit region requires an on current. [Summary of the Invention] As the defects of conventional technology need to be improved, the inventors have exhausted their mental research to overcome them, and have developed the crystalline silicon thin film transistor (T F T) panel of the present invention. Therefore, the main purpose of the present invention is to provide a thin film transistor (TFT) panel, which uses a metal induced lateral crystallization (M ILC) method to simultaneously make a pixel transistor and a driving transistor including a crystalline silicon active layer. The pixel region and the driving circuit region of the TFT panel of the LCD or the OELD are respectively formed, and the characteristics of the off current and the on current in the pixel region and the driving circuit region can be satisfied separately and simultaneously. [Embodiment] Before concretely explaining the present invention ', the crystals formed by ML C are thinned.

1229943 V. Description of the invention (5) The thin film of the film transistor is formed by first forming a source and a step, and then using a layer and a thin film method, and sputtering. However, the broken layer is an amorphous crystal, which requires fast integration) to reduce the driving circuit and the layer's crystallization through annealing. Therefore, polycrystalline silicon layers are provided. Annealing below ° C will result in long-term thermal degeneration of the substrate, which will cause deformation at temperature. The quasi-scanned silicon layer enables the manufacturing method to be described as follows. The crystal can be used in a display device such as an LCD. Silicon is deposited on a transparent substrate made of glass, quartz, or the like in the following manner, and the dopants or dopants are injected into the source drain. The region is annealed and an insulating layer is formed thereon. The channels for the transistor that constitute the source and drain regions are generally deposited on a transparent substrate made of glass by chemical vapor deposition (CVD, etc.), and directly deposited on the substrate by the above method such as C VD method. Silicon, so the electronic mobility is low. For example, the display uses the thin film electric speed of the operating speed and miniaturization, driving integrated circuits (IC s degree increases and the aperture ratio of the pixel area (aperture). It is necessary to increase the electronic gaming of the silicon layer Mobility can form a pixel transistor at the same time and increase the pixel aperture ratio, so the amorphous silicon (a η nea 1 ing) is processed and crystallized to produce a layer with a high electronic mobility. Various methods are used to crystallize the amorphous silicon layer into a thin film The solid-phase crystallization method (SPC) of a transistor is an amorphous silicon layer at a temperature of about 600 to several tens of hours, and the temperature below about 600 ° C is the glass transition temperature (Tg). Because of the SPC The silicon layer of the method requires fire, so there will be productivity problems, and if the substrate is large and the annealing temperature is below 600 ° C for a long time, the substrate molecular laser crystallization method (ELC) is performed by excimer. Laser Beam locally produces a short period of high temperature can instantly crystallize the silicon layer, however

1229943 V. Description of the invention (6) The ELC method has technical problems that cannot accurately control laser beam scanning and manufacture only one substrate at a time. Therefore, the ELC method also has a defect that the productivity is lower than that of manufacturing a batch of substrates in the furnace. In order to overcome the shortcomings of the traditional way of crystallizing the silicon layer, the phenomenon that when amorphous metals such as nickel, gold, and aluminum are injected into the amorphous silicon can cause the amorphous silicon phase to change into polycrystalline silicon at a low temperature of about 200 ° C, this phenomenon It is called metal-induced crystallization (M IC). In the thin film transistor manufactured by using this MIC phenomenon, a small amount of metal may remain in the polycrystalline silicon constituting the thin film transistor active layer, and therefore, a problem of leakage may occur in the channel of the thin film transistor. Recently, a method using a metal-induced lateral crystal (M I LC) crystalline silicon layer has been proposed. In this method, Shi Xi is successfully induced to crystallize, and at the same time, a metal silicide layer is formed by continuous lateral proliferation reaction between the metal and Shi Xi. (Si 1 icide), is not to allow metals to directly induce the phase change of silicon (see SW · Lee &amp; SK Joo, IEEE Electron Device Letter, 17 (4), ρ · 160, 1996), nickel, Ibar, etc. are known Metals can be used to induce M ILC. The silicon layer is crystallized by M I L C, and the metal component used to induce silicon crystallization does not remain in the silicon layer crystallized by the M I C method. Because the metal-containing silicide multiplies laterally, the silicon layer crystallizes. Therefore, it has the advantage that metals such as Ni and Pd do not affect the characteristics of current leakage and other operating characteristics of the active layer of the thin film transistor. In addition, ML C 'silicon can induce crystallization at a relatively low temperature of about 3000 to 500 ° C, so another advantage is that several substrates can be crystallized in the furnace at the same time without causing damage to the substrate. And, by the LC phenomenon, silicon can induce crystallization at a relatively low temperature of about 300 to 600 ° C. Therefore, several substrates can be crystallized in the furnace at the same time without causing damage to the substrate. Advantages, even glass-based

Page 10 1229943 V. Description of Invention (7) The same applies to the board. Figures 3A to 3D show the conventional steps of forming a crystalline crystalline layer of a TFT using MIC and MILC phenomena. As shown in FIG. 3A, an amorphous silicon layer is deposited on an insulating substrate 30 having a buffer layer (not shown). Amorphous silicon is patterned by photolithography to form the active layer 31, and then a gate insulating layer 32 and a gate electrode 3 3 are sequentially formed on the active layer 31 in a conventional manner. As shown in FIG. 3B, by doping dopants in the entire substrate of the gate electrode 33 as a photomask, a source region 3 1 S, a channel region 3 1 C and a channel region 3 1 C are formed on the active layer 31. One drain region 3 1 D. As shown in FIG. 3C, a photoresist 3 4 (PR) covers the gate electrode 3 3. Some portions of the source region 3 1 S and portions of the drain region 3 1 D surround the gate electrode 3 3. Then, a The metal layer 35 is deposited on the entire surface of the photoresist and the substrate. As shown in FIG. 3D, the photoresist 34 is removed, and the entire surface is annealed at a temperature of 300 to 600 ° C. Therefore, the source and drain regions 36 directly above the residual metal layer 35 are caused by the M IC phenomenon. It is crystallized, but the metal offset portion of the source and drain regions and the channel region 37 on the gate electrode are crystallized by the MI LC phenomenon induced by the residual metal layer 35. As shown in FIGS. 3A to 3D, the photoresist-shaped source and drain regions 3 IS, 3 1D covering both ends of the gate electrode 3 3 are due to the metal component that induces the MIC phenomenon remaining in the channel region 31C and the channel region. The boundary between 31C and the source / drain regions 31S, 3 1 D. However, if a metal layer is deposited on the boundary, leakage and operating characteristics of the channel region are reduced. In order to solve this problem, a metal compensation region is formed around the channel region to prevent the channel region from being induced by metal. Except for the channel area, the source / non-electrode area will not be strongly affected by residual metal components.

1229943 V. Description of the invention (8): Use the domain as the It area, • The body C is only energized and crystallized by the f channel J crystals. The crystals produced by the liquid crystal are concentrated in the U-negative region. However, in consideration of the operation, the source and the drain region i are separated by about 0. 0 1 to 5 // m, allowing it to pass through. The M IC phenomenon causes the junction region and the metal compensation region to crystallize by the M ILC phenomenon, and the time required for crystallization of the {layer is reduced. The characteristic of the present invention is to control the off-current characteristics of the transistor in the 4-channel TFT panel around the injection channel, especially like the crystalline silicon TFT image according to the method described in FIGS. 3A to 3D. On current and off current of doped 4 crystal. Table 1 shows the variation of the current with different dopant concentrations around the channel region of the implanted i-film transistor. Table 1 Dopant concentration around channel area {/ cm2} 5.00E12 1.00E13 1.00E14 3.00E15 Off current (A> 1.00E-12 5.00E-12 3.00E-11 5.00E-11 On current (A> 8.00E -15 2.00E-14 3.00E-04 5.00E-04 Switching current ratio 8.00E07 4.00E07 1.00E07 1.00E07 (The width W of the transistor is 10 // m, the length L = 6 // m, VD = 10V, The on-current is measured at the gate voltage VG 220V, and the off-current is measured at the gate voltage VG =-5 V. Figure 4 is a graph drawn in Table 1. As shown in Table 1,

Page 12 1229943 &quot; &quot; ——_____ &amp; Description of the invention (9) ^ ^ $ Dopant concentration is increased, the on and off currents of the drain are increased ° If the dopant concentration is 5. 〇〇 E 1 2 / c m2, the closing current and the opening current are 1 · 00E-1 2 and 8 · 00E-1 5 respectively, and the switching current ratio is 8. 00E07; however, if the dopant concentration is 3 · 〇〇E 1 5 / c m2, the off current and on current are 5 · Ο E-1 1 and 5 · Ο E-0 4 respectively, and the switching current ratio is 1 · 〇〇E 0 7. From the above, it can be known that when the dopant concentration around the injection channel is increased, the increase of the off current is higher than the increase of the on current. As shown in FIG. 4, the pixel electric aa body formed in the pixel area of the TFT panel of the LCD needs to have an off current lower than 1 £ — 1 1 A and an on current higher than 1 £ — &amp; a to form a thin film transistor In the doping process of the source and drain electrodes, the dopant concentration in the electrode region and the drain region is generally 1E14 / cm2 or more: as shown in the source and the first figure, the concentration The power-on of the following transistors is shown in Table 1 E-5 A, so even if the dopant is used in a general doping process Note: = Around the domain, the pixel transistor can achieve the characteristics / characteristics required for the on-current. In order to maintain the electrical signal in the non-selected area of the pixel, the current in the I channel must be lower than the threshold of 1E-11A, and the threshold of the implanted dopant is 1E14 / cm2 or higher. , The off current will be higher than the threshold. If the current of Lcd and ^ degrees is higher than 1 E- 11 A, screen flickering and stringing will occur. The transistor of the crystalline silicon TFT panel manufactured by M ILC is 9 and the problem, because it needs to be maintained continuously. Below the threshold. The off current of the bean, as shown in Table 1 and Figure 4, if the dopants around the channel of the body made of M 丨 Lc are injected 丨 · 〇〇E14 / cm2 or lower, the film transistor current is reduced to less than l.OOE—11A threshold value, so the effect of the off current used to keep the power off of the electrode is lower than the threshold value.

1229943 V. Description of the invention (10) The sundries are lower than 1.00E14 / CW. However, if a general process is used, the problem of keeping the dopant concentration below 1 · 〇〇E 1 4 / cm 2 is the solution. ^ = The feature of the present invention is that the area around the transistor channel is "this problem". In the impurity region, if the concentration of the implanted dopant is lower than that of other doping f (lightly doped pole, Lightly — Dope d Dra i η), this region / time is kept below 1 · 〇E 1 4 / c m2. According to the present invention, ^ TF〗 T ^. Qin Lei said, touch the bamboo ... a personal touch% 111 Γ panel combination and i = f pixel transistor to form a lightly doped region in the transistor The specific implementation examples are described below . The imaging f 5A to 51 &quot; is a manufacturing method of simultaneously describing a body and a driving transistor with MILC on a TFT panel according to the present invention. Although this embodiment has two trace regions, a pixel transistor and a storage capacitor are formed, and the driving transistor of the present invention is not limited to the CMOS transistor. Two or more T F Ts can be formed in the pixel region according to the region, and ′, N-MOS, CMOS, or a combination thereof is described in the driving example. Although this implementation is familiar with this technology, the transistor and the capacitor layer of the storage capacitor will be connected to each other, but the pixel transistor and the capacitor layer of the storage capacitor need to be connected to each other. Can form an electrical connection. In addition, although this layer can be used as an electrode to replace the storage capacitor formed by the Shi Xi layer, other layers such as electrodes made of different metals ^ and the person skilled in the art knows that the insulating layer with the gate (Die 1 ee + The formed layers, such as the intermediate insulating layer, form a dielectric flute (C LaYer) for the storage capacitor. FIG. 5A is a top view of the shielding layer 51 formed on the substrate 50 to prevent diffusion of the contaminants from the substrate 50. The substrate 5 〇 is made of transparent insulating materials such as non-glass inspection, ~ oxidized stone, etc., and the shielding layer 5 1 is made of deposited oxygen

1229943 V. Description of the invention (π) Silicon silicon (Si02), silicon nitride (SiNx), silicon oxynitride (SiOxNx) or the temperature can be below about 60 ° C, and the thickness can be 300 to 10, 0 〇〇A or better is composed of 500 to 3 00 A composite materials, can be used deposition methods such as plasma-assisted chemical vapor deposition system (PECVD), low pressure chemical vapor deposition system (LPCVD), conventional Pressurized chemical vapor deposition (APCVD), electron cyclotron resonance chemical vapor deposition (ECR-CVD) or sputtering; ship method. As shown in Fig. 5B, an amorphous silicon layer 52 (a-Si) constituting an active layer of a thin film transistor is formed on the shielding layer 51. The amorphous silicon layer 5 2 formed by amorphous stone is deposited by pECVD, LpcvD or sputtering method, and has a thickness of 300 to 丨 〇, 〇 〇 〇 〇 A or better is 5,000 to! 0 0 0 A. In order to form a N_M0s or a = P-M0S in the pixel area and a driving circuit area (as shown in the 5th), a pattern is generated by using a light micro: an etching gas plasma for dry etching. 1 ^ The domain and the drive circuit area are adjacent to each other, the image, the image f, and Ka Mu Ren, in the real estate, an array of multiple unit pixels is formed in the pixel area to move the circuit area to each other, with: = = Metapixel region and the manufacturing method formed in the second drive. In this embodiment, an amorphous silicon island 52p of w-P-M0S is reported, and A is not in order to form an N-M0S or ΓΜης. Said 2 ρ $ is formed in the pixel area 79, in order to form two amorphous stone islands 5 Cm 0 Γ) shape of C Μ 0 S # 士人 w 太 慎 # Μ Φ », + Γ f is formed in the driving circuit area 8 〇 Although CMOS is formed in the domain of the Qin Leiyou FA Shi Γ ί, if there is a need for P-MOS, CMOS or a combination of them. Circuits, such as N-MOS, in the amorphous stone layer 5 2 , 丄, ^ After tea, a gate insulating layer is formed to form

Page 15 1229943 V. Description of the invention (12) The insulating layer 53 and a gate electrode form a metal layer 54 (as shown in the figure). Deposition silicon dioxide (S i 0 2), silicon nitride (S i NX), oxynitride / (SiOxNx) or a combination thereof by PECVD, LPCVD, APCVD, ECR CVD, etc. to form an insulating layer 53 The thickness can be 300 to 3,000 A or more preferably 500 to 10,000 A by sputtering, evaporation, PECVD, LPCVD, APCVD or ECR or conductive materials such as pompano On the mixed polycrystalline chip 53, the thickness is from 1,000 to 8,000. Figures 5D and 5E are pattern etching steps to form a gate electrode 5 6 and a pattern 5 5 by photolithography. Amorphous stone with driving transistor. As shown in the figure, the three electrodes form the entire surface of the amorphous silicon island on the right side of the drive circuit area. Two pairs of the three electrodes are used to form a pixel transistor. In the embodiment, the pixel transistor is formed due to the weak electric field strength at the interface between the source and drain regions. Although two gates are formed in the body, the driving power is more than two gates. As shown in FIG. 5E, the CVD and other deposition methods of the present invention deposit a metal material to form a gate metal layer 54 on the insulating layer or more preferably from 2,000 to 4,000. After the photoresist pattern 55 is formed, a wet or dry capacitor electrode 57 is used. The photoresist is formed by the gate metal layer 54 on the amorphous silicon island 5 2 P island 52D of the pixel transistor in the pixel region. One gate electrode is formed on the amorphous silicon island 5 2 D, and the driving circuit surface is covered with a photoresist (PR) 8 1 to form a side electrode 5 6 formed in the pixel region and a gate electrode, and the other right electrode 5 7 is stored Capacitor electrode. In the better practice, the double-gate electrode can reduce the off current, and the system area is expanded. When using multiple gates, only the structure description in the embodiment is described. The pixel transistor can use more or less than two gates. Example has a through

Page 16 1229943

V. Description of the invention (13) The a distance 8 2 over-etched the undercut structure of the gate electrode 56 in the patterned photoresist. As described above, the gate electrode layer is over-etched to form a L β β (L 丨 U 乂 Doped Drain) region in the channel region above the intermediate electrode of the transistor. FIG. 5F shows that an insulating layer 53 is formed by the omnidirectional etching. In the state of the gate insulating layer 58 and a capacitor dielectric material layer 59, a patterned light ^ is used as a photomask. As described above, the photoresist-resistant over-etched gate electrode, the gate insulating layer 58 and the dielectric material layer 59 Figure 5G with gate electrode 59 and capacitor electrode 57 higher than that of gate electrode 59 shows a process of removing photoresist using gate electrode as a photomask doping dopant. First, doping the pixel transistor with high energy at low energy Concentration of the dopant and the left driving transistor is not covered by the photoresist. If the N-MOS TFT is manufactured as shown in the figure, PH3, P or AS is used as the dopant, and the doping dose is about 1E14. To lE22 / cm3 (preferably 1E15 to lE21 / cm3), energy of 10 to 10OKeV (preferably i〇s 100KeV), and large amount doping (shower doping) or ion implantation method); then if p — M0s τρτ is manufactured, n, B or BH3 is used as a dopant (Dopant), and doped lE22 / cm3 (Preferably 1E14 to 1E21 / r ^ 3,

(Preferably 10 to 30) i5G = energy is 10 to 70 KeV range. Due to low energy doping and high doping, the second layer is implanted with an insulating layer of N-type dopant to form a thin film transistor: the original crystal, so it will not penetrate through: the insulating layer of the crystal is wider than the idler earth. According to the present report, "percentage of pixel electromagnetism" &amp; and prevention of doping at high concentration and low energy

1229943 V. Description of the invention (14) The impurity f is implanted in the silicon layer, so a low-dose region with a low dopant is formed around the channel. The gate insulating layer forms a metal offset region 'around the channel region as described below. First, the N-type dopant is first doped with low energy and high concentration 83 and then is doped with high energy and low concentration 84. The N-M0S TFT is doped with ph3, P, or AS as a dopant, and the dosage is about 丨 E 丨 丨 to 1 E 2 〇 / c m3, and the energy is 50-150 K e V. The conditional acquisition method is used for doping with high-energy B or BH3 as a low-concentration dopant with a dopant of 20 to 1000 KeV, and replacing the impurity region 60 with the gate insulation. Although the doped region can be mixed with the above-mentioned technique, the dopant driving circuit that does not form a low-energy concentration around the gate channel does not exchange impurities. In order to form a low-concentration, it replaces most of the high-energy and low-energy parts. Dopants. Low-concentration doping conditions pass through the gate layer cover and cooperate with high dopants and low energy to change the doping concentration of the low-concentration dopant in the insulating layer. Doping concentrations in insulation doping, ion implantation, or other ion implantation Doping. The P-MOS TFT is doped with B2H6 at a dose of about 1 E 1 1 to 1 e 2 0 / cm3 with high energy and low concentration. Low concentration doping with sufficient energy level of the insulating layer = low concentration of the gate electrode driving circuit area> The degree of dopant control is controlled by implanting the low concentration below 1E14 / cm2. A f concentration is doped with high energy and low concentration, and then the j series is cooked. If high-concentration doped high-concentration dopants are implanted into the silicon layer with high energy, the hetero-region is widened. If the high-via-butt contact surface is formed in the thin film transistor channel from the above process, the low-concentration doped region is replaced. In addition, the doping method with a concentration of 2 4 氐 can be used to make the doping energy so that the confined layer can be confined and only a part of the impurity can be injected into the stone layer.

1229943 V. Description of the invention (15) If the low-concentration doped region or the complementary channel can reduce the transistor's off-current and 3 = f, the drain region is adjacent to τ to achieve this purpose, and the low-concentration impurity region is determined by =. The width is 1,000 to 20,000, preferably 5 丄, and the patch surface is formed to have a low pixel crystal off current to 1 E-1 1 A or less, ′ 卞 A. In order to reduce the dopant concentration, it is controlled below 1E14 / cm2.太 眚 # :: Doped region crystals and driving transistors form low-concentration doped regions at the same time. However, the off-state current of the driving transistor does not need to be limited as a pixel transistor, so it may not be the same in a driving transistor. A low-concentration doped region is formed. After the process of FIG. 5G, the gate insulating layer 5 8 and the gate electrode 56 are formed in the above-mentioned manner. Please refer to the graphs 5 D and 5 F in the entire pixel area and in the photoresist (PR) The transistor on the other side of the C M 0 S transistor (the preferred embodiment is an N-type transistor) in the driving region (shown in Figure 5) covered by the 8 1 is on the side of the CMOS transistor. A P-type transistor is formed. Although this embodiment describes that in order to form a CMOS transistor in the driving region, an N-type transistor is formed first and then a P-type transistor is formed, but the order in which the transistors are formed can be changed. Please refer to Fig. 5I, the photoresistor on the gate electrode is touched back to make the photoresistor width equal to the gate electrode. Please refer to Figure 5J. After the gate insulating film and the CMOS transistor gate electrode are located on one side, a P-type transistor is patterned (as shown in Figure 5 丨) and the relative polarity (such as P-type) Dopant to its composition of C MOS transistor whose = 1 crystal is first doped with high concentration and low energy and then doped with low concentration and high energy 'conditions with reference to FIG. 5G. As mentioned above, the low-concentration high-energy dopant is implanted into the silicon layer through the gate insulating layer. Therefore, the low-concentration doped region

Page 19 1229943 V. Description of the invention (16) It is formed around the channel region of the P-type transistor. The amount of high-concentration doping 83 and high-energy low-concentration doping P: type doping 2 = row low-energy ′ by deleting the high-energy doping step at the channel periphery sequentially, and the low-concentration doped region. Although this embodiment describes the formation of $ 2, both sides replace the transistor to form a low-concentration doped region. The second pixel electric BS body and the driving current characteristics are not as good as the pixel transistor, which will result in a low level when the driving transistor is connected Concentration doped region. Therefore, the driving transistor does not refer to FIG. 5K, and is removed during the doping process. FIG. 5L shows that the entire pixel on the substrate and two = act as a photoresistor; and then a metal-induced M ILC will form an electrical circuit. Crystal = area shift = photoresist, followed by manufacturing steps. MIL can be induced by amorphous silicon: use layer m: crystal (Ni), palladium (Pd), and the metal of C phenomenon can include nickel 2, Sb, Cu, Co, Cr, Mo, Tr, Ru In the examples, Ni, Ni, Pd, etc. are used to induce MILC, and metals such as Ni and Pd can be transmitted through the bell splash method. The induced MILC method is applied to the active layer. However, the thickness of the method, PECVD, and implanted metal layer is more than enough to induce the amorphous stone layer by the <machine plating method, and the gold used is 1 to 10. 0 0 0 A, preferably 1 () M ILC phenomenon has an arbitrary range _ Please refer to FIG. 5L, because the gate is absolutely 200A. The layer where no metal is induced to deposit on the MILC covers the periphery of the channel, so the channel area around each transistor on the board. The metal compensation area 61 is formed in the base compensation area 61 to prevent the metal from surrounding. As shown in Figures 3A to 3D, the operating characteristics of gold, this metal composition can reduce the leakage around the channel and reduce the area where Ni is directly deposited 85 to produce a Mlr \ f layer on a metal that induces MILC. In this embodiment, a shape

1229943 V. Description of the invention (17) The pattern is wider than the gate area and the metal contact area. 60 and the metal reference area have a pattern offset area. The note cover can form a metal doping area and a low-concentration gold doped area. At the crystallizing stage, the M ILC phenomenon is used to induce the step, such as 500 minutes to 12 minutes, in a short time of a quick minute. 〇 Very short time heating at 6 0 ° C. 0.1 Silicon is crystallized in the furnace to prevent any annealing of the substrate. Therefore, it can be directly deposited on the crystal, and in the region of the annealing strip that does not crystallize the MILC phenomenon and drives the crystal. Layers of amorphous and hard annealing are performed by halogen one: or ELC. From the present invention to 50 hours, the temperature is lower than that of deformation or damage. The amorphous second region of a large-scale system is suitable for metal crystals. According to this task, which is similar to the RTA provided by the annealing step of Ni, the crane lamp or xenon method will work, and the silicon junction is better to 0. For glass substrates, due to the large range, the increase in the field through the dedomain is achieved by According to the invention, the closed-electrode insulating layer formed by chemical implantation as an electrode provides simultaneous formation of a low-concentration complementary region around the channel region. Therefore, the core is: the complementary region 61 is formed in the same region. Although the free-electrode insulating layer described in this embodiment forms a low-concentration doped region and gold ^ f j before the use of the M ILC metal is induced, the region is blocked by photoresistance, as shown in FIG. 3. Therefore, the low-density compensation areas do not necessarily overlap each other in the same area, and the domains can be formed in a part of the metal compensation area, and vice versa after the transistor is applied, as shown in Figure 5M. According to the method of crystallization and annealing, the active layer is heated for several seconds to several hours. The lamp is used as the heating source and the layer is heated by excimer laser. The temperature of the crystal in the furnace is from 400 to 5 to 20 hours. Thanks to the amorphous glass transition temperature, preventable substrates can be produced simultaneously in the furnace. The induced metal fire step is annealed by the M I C phenomenon and the area spread of the metal is used to induce the amorphous silicon layer by the M I C.

Page 21 1229943-^ --------- V. Description of the invention (18) &quot; &quot; ------- The crystallization and dopant of the active layer are performed in a single step. The amorphous silicon layer in the storage region formed on the drain side of the pixel transistor and formed on the outer side of the pixel transistor is also crystallized simultaneously through the annealing step. Another characteristic of the present invention is that the storage capacitor and the pixel transistor are formed through the same process and have the same structure. Since the dielectric layer 5 9 made of the same material as the gate insulating layer of the pixel transistor is fixed between the crystalline silicon layer 5 2 P having excellent electron mobility and the capacitor electrode 57 made of the same material as the gate electrode, Therefore, the storage capacitor has good electrostatic capacitance and electrostatic characteristics. Referring to FIG. 5N, an intermediate insulating layer 62 is formed after the pixels on the substrate and the transistor in the driving area are crystallized. The intermediate insulating layer 62 is deposited by a deposition method such as PECVD, LPCVD, APCVD, ECR CVD, or sputtering. Silicon silicon, silicon nitride, silicon oxynitride, or a mixture thereof is made of crystals and has a thickness of 1,000 to 15,000, preferably 3,000 to 7,000. Referring to FIG. 50, a contact electrode 63 is formed, a pattern is formed by using photolithography as a photomask, and a contact hole (C ntact ho 1 e) is formed by wet or dry etching the intermediate insulating layer, and the contact electrode is formed. 6 3 The source, drain and transistor gates can be connected to an external circuit, while the contact electrode 6 3 is formed by depositing metal or conductive materials such as sputtering, evaporation, CVD, etc., such as doping polycrystalline silicon to On the entire intermediate insulating layer, the thickness is 500 to 10,000 A, preferably 2,000 to 6,000 A ', and then the metal or conductive material is produced by dry or wet etching as required. Shape pattern. Subsequently, an insulating film 64 covering and contacting the electrode 63 is formed and then patterned by a general method. A pixel electrode 65 for the electric field of the liquid crystal of the LCD unit pixel is formed in the pixel transistor region. Therefore, complete the T F T panel of l c D

Page 22, 1229943 V. Description of the invention (19) (as shown in FIG. 5P), according to the aforementioned manufacturing method, a crystalline pixel transistor having two gate electrodes and a storage capacitor connected to the pixel transistor are formed by using The pixel region of the LCD substrate of MILC, and the crystal driving transistor such as C M 0 S, are simultaneously formed in the pixel region using a low temperature step. This invention describes the TFT panel of an LCD. However, the principle of the present invention can also be applied to the TFT panel of an OELD without any modification or change. Fig. 6A is an equivalent circuit of a unit pixel of a TFT panel of a voltage-driven OELD. Each unit pixel includes an information data bus (V d), a gate bus (V g), and a gate including a gate connected to the gate bus and a source connected to the information data bus Addressing with the drain (switching technology) TFT 71. The addressing TFT 71 drain is connected in parallel with the storage capacitor 7 2 that keeps the signal from the addressing TFT 71 to the next signal coming, and the gate of one pixel driving TFT 7 3 is used to receive the reference voltage (V dd) to output the organic electronic light emitting material. Driving voltage (Vc). Since the TFT LCD does not emit light by itself, only one pixel TF T applying a voltage to the pixel electrode is used for the unit pixel. However, only with the data signal voltage, OELD cannot obtain a voltage level sufficient to guide the organic electronic light-emitting material to generate light. Therefore, it is necessary to additionally use a pixel driving TFT 73 as an output of an addressing TFT 71 which receives a gate signal, for example. Please refer to FIG. 6B, which is an equivalent circuit diagram of a unit pixel of a TFT panel of a current-driven OELD; a unit pixel of a TFT panel of a current-driven OELD has two addressing TFTs 74, 75, two pixel-driving TFTs 77, 78 与 76 A storage capacitor 76. The first fixed address TFT 74 is turned on by a signal from the first gate bus (V g 1) to receive an information data bus.

Page 23, 1229943 V. Description of the invention (20) The information from the (20) line (Vd), and the second addressing TFT 75 is turned on to provide the first addressing TFT 74 through the signal from the second gate bus (Vg2). The output is to the gates and storage capacitors 76 of the pixel driving TFTs 77 and 78. When the first and second addressing TFTs 74 and 75 are turned on, the electric charges are accumulated in the storage capacitors 76 which generate voltages in turn. Subsequently, the driving voltage is applied to the gates of the first and second pixel driving TFTs 77 and 78. Even if the second addressing TFT 75 is turned on, the voltage is applied to the storage capacitor to keep the pixel driving TF T 7 7 and 7 8 turned on until During another signal period, the driving current can be continuously provided to the unit pixels of the OELD. In the crystalline silicon TFT panel of OELD, the pixel region and the peripheral region are formed on a common substrate at the same time. In order to effectively drive a driving circuit such as a switching device, the pixel region needs to have a low off current (I 0ff). State, current flows to the pixel transistor (hereinafter, the ELD pixel transistor is considered to include the addressing TFT and the pixel driving TFT, unless they are opposite), and the surrounding area needs to have a high on current (I on), such as the gate In the state where the voltage is used, a current flows to the thin film transistor. 0 In an ELD crystalline broken TFT panel, the off-state current of the thin-film transistor that directly supplies current to the storage capacitor is preferably lower than 1E-11A, especially the addressing TFT 71 in FIG. 2A and the second addressing TFT in FIG. 2B 75. If the off current of the addressing TFT is higher than 1E-1 1 A, even if the output of the addressing TFT 71 in FIG. 2A and the second addressing TFT 75 in FIG. 2B cause the individual potentials of the storage capacitors 7 2 and 7 6, they cannot be maintained. The charge is accumulated until the next signal period. Therefore, there is a problem that the gate potential of the pixel driving TTF cannot be maintained, and the on state of the pixel driving TFT cannot be maintained. In spite of its good on-current characteristics, polycrystalline silicon is crystallized as M I LC

Page 24 1229943 V. Description of the invention (21) T F T has a relatively high off current. However, according to the present invention, this problem can be solved by forming an L D D region in the pixel transistor. The formation of an L D D area due to the addressing T F T can directly provide current to the storage capacitor of the pixel area, which can solve the off-current problem of the TFT panel of the OELD. Subsequently, the addressing TFT can maintain the voltage created by the storage capacitor during the signal period. The OLED panel of OELD is manufactured by the manufacturing method described in Figures 5A to 50. Although only one pixel TFT is described, other pixel transistors can be formed in the pixel region according to this condition. In order to induce the The amorphous silicon layer is crystallized, and Ni, which induces low temperature crystallization, is applied to the amorphous silicon layer to guide the heat treatment. In the present invention, Ni is applied to amorphous silicon, and the substrate is heated at 2000 to 700 ° C. In the deposition step, Ni to amorphous silicon reacts with silicon to generate a silicide of the metal, and Ni is deposited. To the gate oxide layer and the gate metal remains in a metallic state. When or before the subsequent crystallization heat treatment, the silicide of the metal formed on the surface of the amorphous silicon is not oxidized when exposed to the atmosphere, and therefore the problem of deterioration of the crystal quality of the stone eve due to oxidation of the metal that induces crystallization can be prevented. Since it remains in a metallic state, Ni deposited on other portions can be selectively removed by a conventional etching step. After the Ni layer is deposited, an etching step is immediately conducted to form a very thin and uniform Ni layer. While the Ni layer is deposited on the silicon, a very thin nickel silicide layer is formed by reacting with the silicon, and During the etching step, excess Ni that does not form nickel silicide is removed, and at the same time, the Ni layer deposited on other parts, such as the gate electrode or the substrate, can be completely removed. A very thin nickel silicide with a thickness of about 1 Λ is sufficient to cause the M I L C of the amorphous silicon layer. Reagents for the etching step on nickel silicide and metallic nickel

Page 25 1229943 V. Description of the invention (22) There is selectivity. For example, ferric chloride, 1HC03 / 5HC1, 150CH3COOH / 50 Η N 〇3 / 3 HC 1 can be used as an etchant. Using this method, the side effects of μ i lC source metals (such as Ni) remaining in silicon can be reduced. To the lowest. A certain amount of boron is injected into the amorphous silicon to conduct the heat treatment in advance, and the crystallization speed and crystal quality obtained by the M ILC, such as the grain size and the crystal consistency, have been significantly improved. Therefore, when the N-type TFT is manufactured, the N-type TFT is implanted. Before or after the dopant, boron is implanted into at least a part of the amorphous silicon layer, which can effectively improve the speed and quality of crystallization through MI LC. In addition, the concentration of boron exceeds 1 X 1013 / cm2. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of implementation of the present invention. Any person skilled in this art can make some changes and modifications without departing from the spirit and scope of the present invention. Retouching, as well as any equal changes and modifications made according to Benmeming, shall be subject to the scope of patents covered by the patent application scope of the present invention. In this embodiment, it is described that two gate electrodes are formed in a pixel transistor, and more gate electrodes can be formed within the driving range. Although the crystal is formed as &quot; P Mnf, CMOS is driven, The circuit includes a variety of thin-film electricity. In addition, although too, N—MOS and ^ 08 or a combination thereof can be formed in the driving area pole, it is also described in the embodiment to form a single gate electricity P_TF in the driving transistor. Tau contains more than two gate electrodes. In addition, although it is described that N-TFT and ρ-T f T, ^ patterns are formed separately and dopants are also implanted separately N-TF Τ Ν-TFT doped ^ and gate patterns can be formed at the same time between N-TFT and P -TFT, when using photoresistor, etc. as an umbrella, N_TFT area is covered with photoresist, and N-TFT and P-TFT can be formed under the condition of nine covers in P-TFT area. Of course, if

Page 26 1229943 V. Description of the invention (23) Some TFTs, such as pixel transistors and driving transistors, are formed using only one type of TFT, and these additional photomask steps are not required. Therefore, although the electrode describing the storage capacitor is formed of crystalline silicon, the electrode may be replaced by another layer such as a metal layer. Those skilled in the art can use a material different from the gate insulating layer to make a layer, such as an intermediate insulating layer, to form a dielectric layer of a storage capacitor. As mentioned above, according to the present invention, a pixel transistor, a storage capacitor, and a driving device can be formed at the same time at a low temperature, so that a substrate such as an LCD or an OELD is not damaged. And because a low-concentration doped region and a metal compensation region are formed around the channels of the pixel transistor and the driving transistor of the TFT panel of the present invention, the on-current characteristics of the pixel transistor and the driving device of the LCD or OELD can be achieved, and the pixel transistor's The off current can also be effectively reduced to the required level.

1229943 on page 27 Brief description of the diagram. The first diagram is a schematic diagram of the position of the TFT panel area of the LCD. The second diagram is an equivalent circuit diagram showing the structure of the unit pixel of the TFT panel formed on the LCD. Figure 3D is a cross-sectional view of a conventional method for manufacturing a thin film transistor using MLLC. Figure 4 is a graph of the change in the drain current generated according to the dopant concentration injected into the metal displacement region of a TFT manufactured with MLLC. 5A to 5P are process diagrams for manufacturing a crystalline silicon TFT panel for an LCD according to the present invention. FIG. 6A is an equivalent circuit diagram of a pixel structure of a TFT panel unit of 0ELD. FIG. 6B is a TFT panel unit of 0ELD. The equivalent circuit diagram of the structure of the pixel is clearly described as a single simple lgu # Figure. Layer domain edge D, electricity, electrical layer, area C, dynamic storage, and pole resistance plate L drive storage as a drain source base area, area, road capacity area Pole and 02241D2460 IX OA- 0 &lt; 0 IX oo oo oo LO 3 · Pixel area · 1 · 3 1 C source area · · · 3 1 S gate electrode .. .... 33 Residual metal layer ... 5 5 channel area ... 37 Shield layer ... 51

1229943 on page 28 Brief description of the amorphous stone layer · · · Amorphous silicon island · · · Metal layer · · · · Gate electrode · · · Gate insulating layer · · Low concentration doped region · Intermediate insulating layer ·· Insulating film · · · Addressing TFT · · Pixel driving TFT Addressing TFT · · Pixel driving TFT Pixel area · · · Photoresistor ... Area of low energy and high concentration doped with Ni directly deposited 2P46802413579135 5255566677777888 .5 .. ............ Amorphous silicon islands. Insulating layers. Photoresist patterns. Capacitance electrodes. Dielectric material layers. Metal contact area contact electrodes. Pixel electrodes. Storage capacitors ·· Addressing TFT · Storage capacitor · · Pixel driving TFT driving circuit area a distance · · · High energy low concentration doping

D 7 6 5 7 2 7 4 7 6 7 8 8 0 8 2 8 4

Page 29

Claims (1)

1229943 VI. Scope of patent application 1 · A crystalline silicon thin film transistor (TFT) panel for a TFT LCD or OELD, comprising: a transparent substrate including a pixel region having a plurality of unit pixels and a driving circuit region, at least A pixel transistor is formed in each unit pixel of a pixel region on a substrate and includes a crystalline stone layer, a gate insulating layer, and a gate electrode, respectively. The active layer is metal-induced lateral crystallization (M I LC) crystal, a storage capacitor, formed in each unit pixel on the substrate; a plurality of driving transistors, formed in the driving circuit area on the substrate, and each including a crystalline silicon acting layer crystallized in M ILC, a gate An insulating layer and a gate electrode; wherein, a low-concentration doped region implanted with a low-concentration dopant, or a complementary contact surface without implanted dopants is formed around a channel of at least one pixel transistor. 2. The crystalline silicon thin-film transistor (T F T) panel according to item 1 of the application, wherein the low-concentration doped region is formed under a gate insulating layer of a pixel transistor. 3. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the patent application scope, wherein the concentration-doped region is in the range of 1,000 to 20,000. 4. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the scope of the patent application, wherein the dopant concentration implanted into the concentration doped region is 1 E 1 4 / c m2 or less. 5. The crystalline silicon thin film transistor (TFT) panel as described in the first patent application Page 30 1229943 6. Scope of patent application. One of the metal compensation areas that does not contain the metal material that induces MILC is formed around the channel of the pixel transistor. 6. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the patent application, wherein the low-concentration impurity-doped region is also formed in the driving transistor. 7. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the patent application, wherein two or more gate electrodes are formed in the pixel transistor. 8. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the application, wherein the transparent substrate is a glass substrate. 9. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the scope of patent application, wherein the storage capacitor comprises a crystalline silicon layer crystallized in ML LC and a dielectric layer and a dielectric layer subsequently formed on the crystalline silicon layer. Capacitive electrode, the crystalline silicon layer of the pixel transistor and the crystalline silicon layer of the storage capacitor are connected to each other. The gate insulating layer of the pixel transistor and the dielectric layer of the capacitor are formed of different materials at the same time. The electrodes are formed simultaneously from different materials. 10. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the application, wherein the pixel transistor is composed of N-MOS or P-MOS, and the driving transistor is composed of CMOS. 1 1. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the patent application scope, wherein the gate insulating layer of the pixel transistor is at least wider than a gate electrode, and a gate insulating layer is used in a low-concentration doped region It is formed as a photomask by low energy and high concentration doping, and by using a gate electrode as a photomask and high energy and low concentration doping. 1 2. If the crystalline silicon thin film transistor (TFT) surface of item 1 of the scope of the patent application is applied, page 31 1229943 6. The scope of the patent application board, in which the M ILC is applied to an amorphous stone layer through a metal that induces the M ILC The gate insulating layer of the pixel transistor and the driving transistor is wider than the gate electrode, and then the layer is annealed in a state where the gate electrode and the gate insulating layer are used as a photomask. 1 3. The crystalline silicon thin film transistor (TF T) panel according to item 12 of the scope of patent application, wherein the metal for inducing M ILC used for doping contains at least Ni, Pd, Ti, Ag, Au, A1, One of Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt, with a thickness of 1 to 200A, using a sputtering method, an evaporation method or a CVD method and an annealing step in a furnace at a temperature of 4 0 0 0.1 to 50 hours at 60 ° C. 1 4. The crystalline silicon thin film transistor (TFT) panel as described in the first item of the patent application, wherein a shielding layer to prevent the diffusion of dopants is formed on the transparent substrate. 0 5. The crystalline silicon as the first application of the patent application A thin film transistor (TFT) panel, wherein the pixel transistor includes at least one addressing transistor, at least one pixel driving transistor, and at least one addressing transistor having a plurality of gate electrodes capable of supplying current to a storage capacitor. 16 · The crystalline silicon thin film transistor (TFT) panel according to item 1 of the scope of patent application, wherein the active layer of the pixel transistor is crystallized by depositing a ML LC source metal, and simultaneously heating the substrate at a temperature of 200 to Heat treatment at 700 ° C and guide substrate. 1 7 · As in the crystalline silicon thin film transistor (TFT) panel of the first item of the patent application scope, the active layer of the pixel transistor is crystallized by depositing a nickel layer thereon; it is composed of iron trioxide, 1HC03 / 5HC1, 150CH3COOH / 50HNO3 / 3HCl Page 32 1229943 VI. Scope of patent application Select the remaining etching agent # to etch the deposited nickel layer; and heat-treat a substrate. 1 8. The crystalline silicon thin film transistor (TFT) panel according to item 1 of the patent application scope, wherein before the heat treatment is induced to induce the active layer to perform MI LC, the concentration of the stone layer injected into the active layer of the pixel transistor exceeds 1 X 1 013 / c m2. Page 33