TWI223455B - Crystalline silicon TFT panel having multi-gate structure used for LCD or OELD - Google Patents

Abstract

The present invention is related to a kind of crystalline silicon thin film transistor (TFT) for TFT-LCD or organic electroluminescent display (OELD). According to the present invention, in the pixel region of TFT panel, metal induced lateral crystallization (MILC) is used to form a pixel transistor and a storage capacitor containing a crystalline silicon thin film; and a driving transistor is formed in the driving circuit region of TFT panel. In addition, two or more than two gate electrodes are formed on the pixel transistor so as to effectively lower the turning-off current of the pixel transistor. Therefore, the invention has the required advantage of semiconductor device, in which the pixel transistor of TFT panel and the driving circuit can be manufactured at the same time through a relatively simple way of manufacturing, and the characteristics of turning-off current and turning-on current required for the pixel transistor and the driving circuit, respectively, can be satisfied simultaneously.

Description

1223455 _Case No. 92112018_ Revised in January_ V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a crystalline silicon thin film transistor (TF T) panel, which can be used in a TFT liquid crystal display (LCD) or Organic electroluminescent display (OELD). The present invention provides a crystalline silicon thin film transistor (TFT) panel that can be used in a TFT LCD or OELD. The pixel transistor located in the pixel region of the TFT panel and the driving transistor system located in the peripheral region are simultaneously induced by the use of metal to induce lateral crystallization (M). ILC) method can be formed of crystalline silicon, and can meet the characteristics of the transistor in the pixel region requires a low off-current (I 0ff) characteristics and the driving circuit formed in the peripheral region of the transistor needs a high on-current (I ο η) characteristic. [Prior technology] Traditional LCD and OELD amorphous stone TFTs are easily manufactured on glass substrates at temperatures below 350 ° C. However, amorphous silicon TFTs are produced due to their low electron mobility. Defects of circuits that cannot be used for high-speed operation. Furthermore, an amorphous silicon TFT is used in the LCD, and a tape carrier package (TCP) is used to drive the 1C. The pixel transistor can be formed in the substrate, and the glass substrate and the PCB can also be connected to each other around the substrate. Therefore, there will be other disadvantages such as the need for additional driver ICs and increased installation costs. In addition, there are other disadvantages because of mechanical and thermal shocks, so the connection between TCP driver 1C and PCB or TCP driver 1C and glass substrate. The connection part between them is separated, or the shrinkage resistance of the connection part will increase, and the pad pitch between the signal line (signa 1 1 ine) and the scan line (sca η ning 1 ine) will change. Short, as the resolution of the LCD panel increases, TCP joining becomes difficult.

1223455 ____ Case No. 92112018_ Month and Day __ V. Description of the invention (2) As for LCDs using crystalline silicon TFTs, crystalline silicon can be used for LCDs because the active layer of TFTs has good electronic mobility. The driving circuit of the switching element and the like, and the pixel transistor and the driving transistor can be formed on the TFT panel at the same time. In addition, due to the self-aligned structure of the crystalline silicon TFT, the level shift voltage of the crystalline broken TFT is lower than the level shift voltage of the amorphous silicon TFT. The N-channel and P-channel used in Shi Xi are formed, so a CMOS circuit can be formed. In addition, because it is similar to the standard CMOS process for silicon wafers, the crystalline silicon T F T process can be used in semiconductor production lines. FIG. 1 is a schematic diagram of a TFT panel of the LCD 10, forming a pixel region 11 and a peripheral region such as a driving circuit region 12. A multi-pixel array including a pixel transistor, a storage capacitor, and the like are all formed in the pixel region 11, and a driving device for driving these pixels is formed in the driving circuit region 12. In the TFT LCD, the analog circuit in the hybrid driving mode is like an operational amplifier (0 P amp 1 ifier) or a digital analog converter (DAC) that is difficult to manufacture for crystal TFT. A separate integrated circuit and switching unit, such as a multiplexer formed on a substrate, is usually used to replace all the driving devices formed on the substrate. FIG. 2 is an equivalent circuit diagram of a unit pixel formed in a pixel region of a TFT panel of the LCD 10. The parent unit pixel includes a data bus (non-composite) (V d), a gate bus (V g), and a pixel transistor with a gate connected to the intervening bus (Vg) 2 1. The source (source) and drain (drai η) connected to the information bus, the pixel electrode, and one to maintain the signal state of the pixel transistor 21 until the next _%

Page 7 1223455 p --- Case No. 92112018 ~ I May 5. Explanation of the invention (3) Ϊ, Immediately? The storage capacitor 22 (Cst) is connected to a storage capacitor 22 in parallel with the two-day-sun t t = 23 (CLC). At the same time, the storage capacitor 22 and the liquid crystal injection early TC23 are connected to the common electrode 24 (Vc0m), respectively. In the crystalline silicon TFT panel of LCD, the pixel region and the driving circuit region are formed on the common electrode at the same time. In order to effectively drive a driving device such as a switching device, the pixel region needs to have a low off current (丨 〇ff), such as when no gate voltage is used. The current that flows into the pixel transistor under the condition of a high voltage, and the driving circuit area needs to have a surface open current (I ο η) 'such as the current that flows into the thin film transistor under the state of using the gate voltage. Please refer to Figure 2. Especially, the off current of the pixel transistor 21 is very high. Due to the charge leakage accumulated in the storage capacitor 22, the driving voltage used to the liquid crystal injection unit 23 cannot be maintained until the next signal period. The stability and consistency of the display are significantly reduced. The thin-film transistor system of the TF T panel used for crystalline Shixi LCD is manufactured in the following manner: 'Amorphous Shixi layer is formed on a glass substrate, and then the amorphous Shixi is crystallized by solid phase (Solid Phase Crystallization), Laser crystallization (Laser Crystallization), direct deposition method (Direct Deposition Method), rapid thermal annealing (rapid therma 1 a η nea 1 ing) and other methods of crystallization. A feature of the present invention is that the crystalline layer of the thin film transistor uses a metal-induced lateral crystallization method (M I L C) instead of the existing crystallization method of amorphous stone. If the MI LC method is used, it has the advantage that crystalline silicon TF T can be simultaneously formed in the pixel region and the peripheral region in a simple step at a lower temperature than the existing crystallization method. However, similar to crystalline silicon crystallized by other methods, crystalline silicon has a higher off-current than amorphous silicon by crystallization using the M I L C method. Especially for non-selection in the pixel area

1223455 Case No. 9211 Revised on January 9, 2018 V. Description of the Invention (4) During the period, the radio wave signal accumulated in the pixel is not lost. At this time, the off current is usually lower than 1 E-1 1 A. However, the M ILC method is used. The formed crystalline silicon TF T shows a good current characteristic and a poor off-current characteristic (that is, the off-current is relatively high). Therefore, at this time, there is another disadvantage, which is that it cannot meet the characteristics required by the thin film transistor in the pixel area. To this end, a structure and manufacturing method of a crystalline silicon TFT panel are needed, so that the crystalline silicon TFT can be effectively formed at the same time. The pixel region and the driving circuit region of the TFT panel of the crystalline silicon LCD can simultaneously satisfy the conditions that the pixel region requires a low off current and the peripheral region needs a high on current.

[Summary of the Invention] As the defects of conventional technology need to be improved, the inventors have exhausted their mental research to overcome them, and have developed the crystalline silicon thin film transistor (TFT) panel and manufacturing method of the present invention.

Therefore, the main purpose of the present invention is to provide a thin film transistor (TFT) panel, which uses a metal induced lateral crystallization (M ILC) method to simultaneously make a pixel transistor and a driving transistor including a crystalline silicon active layer. The pixel region and the driving circuit region of the TFT panel of the LCD or the OELD are formed separately, and the characteristics of the off current and the on current in the pixel region and the driving circuit region can be satisfied separately and simultaneously. [Embodiment] Before the present invention is specifically described, a crystalline silicon thin film will be formed by ML LC.

Page 9 1223455 Case No. 9211 January, 2018 Revision V. Description of the Invention (5) The method for manufacturing a film transistor is described below.

Thin film transistors can be used in display devices such as LCDs. They are made in the following manner. First, silicon is deposited on a transparent substrate made of glass, quartz, etc., a gate electrode is formed thereon, and then a dopant or dopant (d 〇 Pants) are injected into the source and drain regions, and the tongue is annealed, and then an insulating layer is formed thereon. The function layer and the channel of the thin film transistor constituting the source and drain regions are generally made by depositing a silicon layer on a transparent substrate made of glass by a chemical vapor deposition (CVD) method, sputtering, or the like. However, the silicon layer directly deposited on the substrate by the above-mentioned method such as the C V D method is amorphous silicon, so the electron mobility is low. For example, a thin film transistor used in a display requires a fast operation speed and miniaturization, and the integration degree of the driving integrated circuit (ICs) increases and the aperture ratio (aperture r a t i) of the pixel region decreases. It is necessary to increase the electron mobility of the stone layer to form a driving circuit and a pixel transistor at the same time and increase the pixel aperture ratio. Therefore, the amorphous silicon layer is crystallized through annealing (annealing) to produce crystals with high electron mobility. Evening floor.

Therefore, various methods are proposed to crystallize the amorphous second layer into a polycrystalline silicon layer of a thin film transistor. The solid phase crystallization (SPC) method anneals an amorphous silicon layer at a temperature below about 600 ° C for several hours to tens of hours, and the temperature below about 600 ° C is the transition temperature (Tg) of the glass constituting the substrate. ). Since the silicon layer of the SPC method requires a long time thermal annealing, there is a problem of productivity, and if the substrate has a large area, a long time annealing treatment at a temperature below 600 ° C may cause deformation of the substrate. The excimer laser crystallization method (E LC) scans the silicon layer by using an excimer laser beam to locally generate a short-time high-temperature crystallizable silicon layer. However,

Page 10 1223455

The ELC method can not accurately control laser & &, ^ hh ^ v bh ^ m ι-L beam scanning and technical inquiry of manufacturing only one substrate at a time. Therefore, the manufacturing method of substrates is a defect method with low productivity. There are also a number of times in the furnace in order to overcome the disadvantages of traditionally injecting the silicon layer into a crystal layer = ° ^ nickel, gold, and infusion into the amorphous stone, so that the use of when the phase of a metal such as spar changes to polycrystalline Amorphous phenomena (MIC) are induced at low temperatures of about 200 ° C. Using this kind of MIC phenomenon, the phenomenon called metal-induced junctions will remain in the thin film transistor. The transistor ’s channel with a small amount of gold film transistor will have a leakage of 3 = i H, Ξΐί Use the metal-induced side Xiang Jing (Μ I LC) company a recently '& seeded *, Shi Xi was successfully induced to crystallize, the same; 2 f method: this is the law eW, person S & The continuous lateral increase of silicon (W ^ Ue) does not allow the metal to directly induce the phase change of Shi Xi (see S1 Lee & s K. J., IEEE Eiectr〇n

Device Letter ' 1U4) ' ρ · 160, 1 996, and known metals such as nickel and palladium can be used to induce MILC. The use of MILC to crystallize the stone layer is not used to induce the metal component of the stone layer to crystallize through the silicon layer crystallized by the Mc method. Since the metal-containing stone compound multiplies laterally, the stone layer crystal multiplies. Therefore, it has the advantage that metals such as Ni and Pd do not affect the characteristics of current leakage and other operating characteristics of the active layer of the thin film transistor. In addition, with M I L C, silicon can induce crystallization at a relatively low temperature of about 300 to 500 ° C, so another advantage is that several substrates can be crystallized simultaneously in the furnace without causing damage to the substrate. Moreover, through the M ILC phenomenon, silicon can induce crystallization at a relatively low temperature of about 300 to 600 ° C, so it has the advantage that several substrates can be crystallized simultaneously in the furnace without causing damage to the substrate. , Even with glass substrates

1223455 — Case No. 92112018_Year_Month_Revision__ 5. The invention description (7) is the same. Figures 3A to 3D show the customary steps of crystallizing a stone layer of a TFT using MIC and MILC phenomena. As shown in FIG. 3A, an amorphous stone is deposited on an insulating substrate 30 having a buffer layer (not shown). Amorphous silicon is patterned by ^ lithography (pho to 1 it hogr aphy) to form an active layer 3 1, and then a gate insulating layer 3 2 and a gate electrode 3 3 are sequentially formed on the active layer in a manner commonly used at present. 31 on. As shown in FIG. 3B, a source region 31S, a channel region 31C, and an electrodeless region 31D are formed on the active layer 31 by doping a dopant into the entire substrate of the gate electrode 33 as a mask. As shown in FIG. 3C, the photoresist 3 4 (PR) covers the gate electrode 3 3. Some portions of the source region 3 1 S and the portion of the drain region 3 1 D surround the gate electrode 3 3. Then, a A metal layer 35 is deposited on the entire surface of the photoresist and the substrate. As shown in FIG. 3D, the photoresist 34 is removed and the entire surface is annealed at a temperature of 300 to 600 ° C. Therefore, the source and drain regions 36 directly above the residual metal layer 35 are passed through the MIC This phenomenon is crystallized, but the metal offset portion of the source and drain regions and the channel region 37 on the gate electrode are crystallized by the M 1 LC phenomenon induced by the residual metal layer 35. As shown in FIGS. 3A to 3D, the source and drain regions 3 IS and 31D which are photoresistively covered at both ends of the gate electrode 33 are due to the metal components remaining in the channel region 31C and the channel region 31C and the source due to the MIC phenomenon. The boundary between the electrode / drain regions 3 1S and 31D. However, if a metal layer is deposited on the boundary, a leakage current is generated and the operating characteristics of the channel region are reduced. The source / drain region other than the channel region is not strongly affected by the residual metal composition, but considering the operation ’the source and drain regions are separated from the channel region by about 0. 〇 1 to 5 // m

Page 12 1223455 _Case No. 92112018_Year Month_iMz_ V. Description of the invention (8) Crystals are caused by the M I C phenomenon, and the crystals are induced by the M I L C phenomenon only in the channel region and the channel driving circuit region to reduce time. As shown in Table 1, as shown in FIGS. 3A to 3D, a single gate is used, and the thin film transistor includes a crystalline silicon active layer crystallized by the M ILC phenomenon according to the method shown in the figure, and has an on current of 3. 00Ε-4Α and an off current. 5. 00Ε-1 1 A, so the switching current ratio (Ion / Iof f) is 6.0 00E + 6. If the off current of the pixel transistor used in LCD is higher than 1 E- 1 1 A, there will be problems such as daytime flicker and crosstalk. Since the crystalline silicon layer crystallized in the MI LC uses only a gate crystalline silicon thin film transistor with a closed current greater than the aforementioned value of 1E-1 1 A, it is difficult to use the crystalline silicon thin film transistor as an LC CD transistor. As shown in Table 1, when only one gate is used, the open current is 3. 00 E-4A, which is larger than the open current 1 E-0 5 A required by the pixel transistor for LCD. Therefore, if the silicon crystal T F T formed with M I L C in the pixel region, the off current remains below 1 Ε-1 1 Α and the on current remains above 1 Ε-0 5 Α. For a crystalline silicon TFT made with M ILC, if the number of gates increases, the junction distance between the source and the drain increases, and the electric field strength applied to the junction area is relatively weakened, which can reduce the off current. Although the on-current decreases when the number of gates increases, the reduction in on-current is much smaller than the off-current. Table 1 shows the change in the ratio of the off current, on current and switching current according to the number of gates.

1223455 _Case No. 92112018_ Amendment Date V. Description of the invention (9) Table 1 Number of gates 1 2 4 Off current (A> 5.00E-11 8.00E-12 4.00E43 On current (A) 3.00E-04 2.00 E-04 1.00E-04 Switching current ratio 6.00E406 2.50E407 2.50E407 (The width of the transistor is W = 10 / zm, the length is L = 6 // m, VD = l0v, and the open current is at the gate voltage VG = 2 0 V, the off current is measured at the gate voltage VG =-5 V), Figure 4 shows the change in the off current and on current according to the number of gates. As shown in Table 1 and Figure 4, 'If The number of gates is increased to 2 and 4, and the turn-off current is changed to 8. 00E-1 2A and 4. 00E-1 3A respectively. It can be seen that if two or more gates are used on the TFT, the turn-off current is smaller than the LCD 1E-11A required by the pixel transistor, which is larger than the open current 1 E-5 A required by the pixel transistor of the LCD 1 · 〇〇E-0 4 A, can use four gates This is obtained because the ratio of the decrease in the on-current according to the increase in the number of gates is relatively low. Therefore, when the gate is increased, the ratio of the on-current to the off-current (I on / I ff) is continuous Increase. According to the above results, if two or more gates are used, the crystalline silicon TFT manufactured by M 丨 L c according to the present invention can simultaneously satisfy the characteristics of the current and the off current of the LCD pixel transistor, such as I 〇 n > 1E-5 and Ioff < lE-ll. According to the opening current of the number of gates shown in Tables 1 and 4, two or more gates have sufficient driving devices for the driving circuit area on the substrate to operate. The degree of current. Therefore, according to the present invention, the crystalline silicon TFT manufactured by M ILC can be driven on the pixel region and the LCE substrate simultaneously.

Page 14 1223455 — Case No. 92112018 V. Description of the invention (10) The Γ ^ field forms a pixel transistor and a driving transistor, and two or more gate electrodes are formed in the TFT of the pixel region. The following 5A to 5P diagrams are the preferred embodiments of the present invention using MILC2TFTs plates simultaneously, elementary transistors and driver transistors. Although the pixel region is formed in this embodiment, a pixel transistor and a storage capacitor are formed in the driving region, and the CMOS transistor is formed, but the present invention is not limited thereto. According to the present invention, two or more tfts may be formed in a pixel region and P-MOS, N-Mos, CMOS or a combination thereof may be formed in a driving region. Although it is described in this embodiment that the silicon layer of the pixel transistor and the storage capacitor will be connected to each other, those skilled in the art know that the silicon layer of the pixel transistor and the storage capacitor do not necessarily need to be physically connected to each other, but can form electrical properties. connection. Second, although this embodiment describes an electrode of a storage capacitor formed of a silicon layer, other layers such as a metal layer can be used as a substitute electrode, and those skilled in the art know that a layer made of a material different from the insulating layer such as The intermediate insulating layer forms a dielectric layer (Die 1 ectric Layer) of the storage capacitor. FIG. 5A is a cross-sectional view of a shielding layer 51 formed on the substrate 50 to prevent the diffusion of pollutants from the substrate 50. The substrate 50 is composed of transparent insulating material ^ no ^ glass, quartz, silicon dioxide, etc., and the shielding layer 5 丨 is composed of Shen ^ ## fossil evening (S i 02), nitride nitride (S i Nx), Nitrogen oxide stone (s 丨 〇 二 『22 plus temperature below about 600 ° C, the thickness can be 300 to 10, 〇〇〇Α or x more x better x 5 0 0 to 3 0 0 0 A composed of composite materials, can be used Deposition methods such as electro-assisted chemical vapor deposition system (PECVD), low-pressure chemical vapor deposition system (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), electron cyclotron resonance chemical vapor deposition (ECR-CVD) or sputtering method.

Page 15 1223455 __Case No. 92112018___Year_Month_Revision_ V. Description of the Invention (11) As shown in Fig. 5B, an amorphous silicon layer 52 (a-Si) constituting an active layer of a thin film transistor ) Is formed on the shielding layer 51. An amorphous silicon layer 52 formed by depositing amorphous silicon by pECVD, LPCVD, or sputtering is used, and has a thickness of 300 to 1000 A or more preferably 500 to 1000 A. In order to form an N-MOS or a P-MOS in a pixel region and a CMOS (as shown in FIG. 5C) used as a driving device in a driving circuit region, a pattern is formed by using photolithography, which is amorphous. The silicon is patterned by dry etching with a gas plasma in the remaining time. FIG. 5B shows that the pixel region and the driving circuit region are adjacent to each other. However, in an actual structure, an array of a plurality of unit pixels is formed in the pixel region and a driving circuit is formed at a distance from the unit pixel array. At the same time, it can be seen that a unit pixel region and a driving circuit region are interconnected 'to describe a manufacturing method in which a pixel transistor and a driving transistor are formed simultaneously. In this embodiment, in order to form an N-MOS or a P-MOS, an amorphous silicon island 52P is formed in the pixel region 79, and in order to form a CMOS, two amorphous silicon islands 52D are formed in the driving circuit region 80. Although it is described in the present embodiment that the C MOS is formed in the driving circuit area, if necessary, various driving circuits can be formed in the driving circuit area, such as NM 0S, P-MOS, CMOS, or a combination thereof. After the amorphous silicon layer 52 is patterned, a gate insulating layer is formed to form an insulating layer 53 thereon and a gate electrode is formed to form a metal layer 54 thereon (as shown in FIG. 5C). Depositing silicon dioxide (S i 02), silicon nitride (S i Nx), silicon oxynitride (S i 0 XNX) or a combination thereof by PECVD, LPCVD, APCVD, ECR CVD and other deposition methods to form an insulating layer 53, Thickness can be 300 to 3,000 A or better 500 to 1,000 A. Metal materials or conductive materials can be deposited by sputtering, evaporation, PECVD, LPCVD, A PC VD or ECR CVD. Such as

Page 16 1223455 _Case No. 92112018_ Month and Revise_ V. Description of the Invention (12) Doped polycrystalline silicon to form a gate metal layer 5 4 on the insulating layer 5 3, with a thickness of 1,000 to 8, 000 A or better is 2,000 to 4,000 A. Figures 5D and 5E are a process of forming a gate electrode 56 and a capacitor electrode 57 using a wet or dry etching step after the photoresist pattern 55 is formed. The photoresist pattern 55 is formed by photolithography. The operation is formed on the gate silicon layer 5 4 on the amorphous silicon island 5 2 P having a pixel transistor and the amorphous silicon island 5 2 D having a driving transistor. As shown in the figure, three electrodes are formed in the pixel region, a gate electrode is formed on the amorphous cut island 5 2 D on the left side of the driving circuit region, and the entire surface of the amorphous silicon island on the right side of the driving circuit region is photoresist (PR ) 8 1 covers to form other types of TFTs to form C M 0 S. Two of the three left electrodes 56 are formed in the pixel region to form a double gate electrode for the pixel transistor, and the other right electrode 57 is used as an electrode of a storage capacitor connected to the pixel transistor. In a preferred embodiment, the double-gate electrode formed in the pixel transistor can reduce the off current because the junction between the source and the drain region is enlarged, and when multiple gates are used, the electric field strength at the junction becomes weaker. . Although two gate electrodes are formed in the pixel transistor in this embodiment, a double gate electrode (Du a 1 G a t e) or two or more transistors is suitable for driving the transistor. As shown in Fig. 5E, the preferred embodiment of the present invention has an undercut structure that passes through the gate electrode 56 in the patterned photoresist through a predetermined a distance 8 2. As described above, the gate electrode layer is over-etched so that a low-concentration doped region such as an LDD (Lightly Doped Drain) region is formed around the channel region above the gate electrode of the transistor. Fig. 5F shows a state where a gate insulating layer 5 8 and a capacitor dielectric material layer 5 9 are formed by omnidirectionally etching the insulating layer 5 3, and a patterned photoresist is used.

Page 17 1223455 Case No. 92112011 Revision V. Description of Invention (13) As a photomask. As with the gate electrode for resisting over-etching as described above, the gate insulating layer 58 and the dielectric material layer 59 have wider widths than the gate electrode 59 and the capacitor electrode 57. Figure 5G shows a process for removing the photoresist and using the gate electrode as a photomask doped with dopants. First, the pixel transistor is doped with a high concentration of dopants at a low energy and the left driving transistor is not covered by photoresist. If the N-MOS TFT is manufactured as shown in the figure, PH3, P or AS is used as the dopant, the replacement agent is about 1E14 to 1E22 / cm3 (preferably 1E15 to 1E21 / cm3), energy It is 10 to 10OKeV (preferably 10 to 100KeV) and adopts a large amount of doping (shower doping) or ion implantation method; however, if p-MoS TFT is manufactured, B2H6 ,

B or B & as a dopant, the doping dose is about 1 e 1 3 to lE22 / cm3 (preferably 1E14 to lE21 / cm3) and the energy is 10 to 70 KeV (preferably 10 to 30 KeV). Figure 5G shows the right to implant N-type dopants. Because the high-concentration dopants are doped with low energy, the source and drain regions of the thin film transistor are not penetrated through the gate insulating layer ', and the dopants only enter the regions covered by the gate-free insulating layer. According to the present invention, since the gate insulating layer of the pixel transistor is wider than the gate electrode and prevents doped impurities from being implanted into the silicon layer at a high concentration and low energy, a low dopant with low dopants is formed around the channel. Dosage area. The gate insulation layer forms a metal offset area around the channel area, as described below. In the ancient place, the first-type replacement material was doped with low-energy high-concentration 8 3 and then doped with horse-energy low-concentration 84. The N-M0s TFT is doped with PY3, P, or AS as a dopant. The doping dose is about 丨 E 丨 丨 to 丨 E 2 0 / c m3, and the energy is 5 0 to

Page 18 1223455 Doped, doped, doped, doped, high-energy edge layer, active layer, high-concentration heterodyne series will form a highly concentrated doped region 'within a region, doped in the square layer and learn the impurities, The ambient energy is low to drive the electricity. In order to replace most of the channels, if the channel reaches a width of 1, keep the note. It can be useful to adjust the above-mentioned artist to form a low-energy high-doped low-doped low-energy dopant through the gate. Concentration can be reduced for this purpose 0 0 0 to 2

i No. 92ij2mR V. Description of the invention (14) 1 50KeV conditions Use high-energy and low-concentration B or BH3 as dopants in a large-scale method. Dopants of 20 to 100KeV pass through low-concentration dopants. The gate, covered with the gate insulating layer, the low energy can change the doped insulating layer into a low concentration doping process.

Doped region transistor is turned off, low concentration 0, 0 0 0 A degree doped region, low pixel crystal volume and doped ion implantation method or other separation, manufacturing P-MOS TFT in H implanted about 1E1 1 to 1E20 / Cm3,] 6, at s low "Chen degree of miscellaneous. The energy level of the combination is changed to a low concentration region to form a low concentration doped impurity.

(¾ 0 Q is mixed with the low concentration in b of the same month, and then Ranjiu. If high-energy implanted high-concentration g ^ dopants are injected into the Shixi layer, so the domain. If the high-supplement interface is deleted from the above process, The thin film transistor channel replaces the low-concentration doped region. In addition, the low-energy high-concentration doping method can be used to control the doping energy so that only a part of the dopants can be injected into the silicon layer or the contact surface is formed in the drain region. Adjacent to the current and the rest of the electrical characteristics are also very stable. For the degree of j, the impurity region or the contact surface is formed to have a domain of 5,000 to 20,000 to 20,000. Below 1 E 1 4 / cm2, from 1E to 11A, therefore, Li ~ Li will dope the low-concentration doped regions.

1223455 _Case No. 92112018_Year Month Amendment _ V. Description of the invention (15) The substance concentration is controlled to less than 1 E 1 4 / cm2. In this embodiment, a low-concentration doped region is formed in the pixel transistor and the driving transistor at the same time. However, since the off-state current of the driving transistor does not need to be limited as the compensation current in the pixel transistor, it is not necessary in the driving transistor. A low-concentration doped region must be formed. After the process of FIG. 5G, the gate insulating layer 5 8 and the gate electrode 56 are formed in the above-mentioned manner. Please refer to the graphs 5 D and 5 F in the entire pixel area and in the photoresist (PR) 8 A P-side is formed on the side of the CMOS transistor in the state of the transistor (the preferred embodiment is an N-type transistor) on the other side of the CMOS transistor in the driving area (shown in Figure 5). Type transistor. Although this embodiment describes that in order to form a CMOS transistor in the driving region, an N-type transistor is formed first and then a P-type transistor is formed, but the order in which the transistors are formed can be changed. Please refer to FIG. 5I, the photoresist located on the gate electrode is etched back so that the width of the photoresist is equal to the gate electrode. Please refer to Fig. 5J. After the gate insulating film and the CMOS transistor gate electrode are located on one side, the P-type transistor is patterned (as shown in Fig. 5I). The relative polarity (such as P-type) Dopants to other transistors that make up the CMOS transistor are first doped at a high concentration and low energy and then at a low concentration and high energy, referring to the conditions in Figure 5G. As described above, the low-concentration high-energy dopant is implanted into the silicon layer through the gate insulating layer. Therefore, the low-concentration doped region is formed around the P-type transistor channel region. The P-type dopants undergo low-energy high-concentration doping 83 and high-energy low-concentration doping 84 in order. In addition, a high-energy doping step is formed to replace the low-concentration doped region by forming an abutment surface around the channel. Although this embodiment is described in which both the pixel transistor and the driving transistor form a low-concentration doped region, the driving transistor is

Page 20 1223455 V. Description of the invention (16) ϋ 虎 J2U20jj

The degree of flow characteristics is not required to form low-concentration doped regions. "" Yueyue body ", therefore, the driving transistor will not refer to Figure 5K, removed from Figure 5L shows a photoresist used as a photomask in the substrate on the substrate; and then a metal induced M ILC will = Said, $ area removes the photoresist, followed by manufacturing steps. Can be embroidered: amorphous silicon crystals Nl, t (Pd) of the active layer of the body. The metals that cause M-like phenomena include nickel (Sb, Cu, Co, Cr, II, and R can also be used; ^, Ag, In Au, A1, Sn, for example, Ni is used to induce total Cd and Ptf, and metals such as Ni and Pd can be passed through the ore splashing method and steamed to 5 Å. The thickness of the induced MILC phenomenon is sufficient to induce amorphous silicon. Fj, and the metal layer used is, for example, 1 to IO'OOOOO, preferably in the range of 10 to 2000, please refer to FIG. 5L, due to p 卩 托 赵 & The metal helmet deposition of the M ILC covers all around the channel, so each transistor on the board has a wide area and a = metal offset area 61. It is formed around the channel area of the base = worker's electric sun. The compensation area 61 can prevent the current belonging to the family and the younger brothers from 31 to 31). The operating characteristics of the metal are not shown in the figure. This + I t ί is a leakage around the knife channel and reduces the Ni connection. As a metal that can induce the silicon layer to induce M 1 LC, such as Θ Fortunately, 8 5 produces M 1 C phenomenon. In this embodiment, the shape &: I metal K5 interlayer, the layer provides the formation of a low-concentration doped region and a metal compensation region around the channel region at the same time. Therefore, the low-concentration doped region 60 and the metal compensation region 61 Formed in the same area. Although this embodiment describes the use of a gate insulation layer with a pattern to form a low-concentration doped region and a metal compensation region, it is noted that before the use of the M I C metal is induced, the light is blocked by light.

Page 21 1223455 Case No. 92112018 _η Name Amendment 5. Description of the invention (17) The cover can form a metal offset area (as shown in Figure 3). Therefore, the low-concentration doped region and the metal compensation region do not necessarily overlap with each other in the same region, and the low-concentration doped region may be formed in a part of the metal compensation region, and vice versa. ) Tungsten lamp or xenon method will work, the silicon junction is better to be 0. Glass substrate, due to the large range, increase the field through the dedomain. By the invention, the implantation of the crop into a single pole and the formation of an annealed pixel transistor on the glass substrate. The pixel lies in the pixel row. The crystallization process is induced by the ML ILC phenomenon, such as a short time of 5 minutes to 1 2 0 0 0 C. A very short time of 6 0 0 ° C heating 0 · 1 Shi Xi crystallized in the furnace In order to prevent any annealing of the substrate, it can be directly deposited on the wafer, and under the annealing conditions without crystallizing the M ILC phenomenon, another feature of the active layer connected to the pixel storage capacitor region is the formation and phase region and driving crystal function. Layered amorphous silicon is thermally annealed by halogen one: or ELC. In the present invention, the temperature is lower than 50 hours when the temperature is lower than the deformation or damage. According to this article, the amorphous silicon layer, which is similar to the crystalline and doped transistors, also stores capacitors with the same structure. After applying to the transistor, proceed as shown in Figure 5M. According to the method of crystallization-annealing, the active layer is heated for a few seconds to several hours, and the temperature is for a layer of excimer laser to heat a crystal in the furnace at a temperature of 400 to 5 to 20 hours. Thanks to the amorphous glass transition temperature, preventable substrates can be produced simultaneously in the furnace. The induced metal fire step is performed by the M I C phenomenon, and the area spread using the metal is performed under the annealing strip step of inducing the amorphous silicon layer by the M I C. The steps outside the pixel transistor are simultaneously crystallized. The body of the present invention is a gate insulating layer phase of a transistor through the same steps at the same time.

Page 22 1223455 _ Case No. 92112018_ Month Revision | ___ V. Description of the Invention (18) Dielectric layer 5 9 made of the same material is fixed to the crystalline stone layer 5 2 P and Ezra with excellent electron mobility. Between the capacitor electrodes 57 made of the same material, the storage capacitor has good electrostatic capacitance and electrostatic characteristics. Referring to FIG. 5N, an intermediate insulating layer 62 is formed after crystallization of the pixels on the substrate and the transistor in the driving area. The intermediate insulating layer 62 is deposited by p ECVD, LPCVD, APCVD, ECR CVD, or sputtering. It is made of deposited fossils, silicon nitride, silicon oxynitride, or a mixture thereof, and has a thickness of 1,000 to 15,000, preferably 3,000 to 7,000. Referring to FIG. 50, a contact electrode 63 is formed, a pattern is formed by using photolithography as a photomask, and a contact hole (C ntact ho 1 e) is formed by wet or dry etching the intermediate insulating layer, and the contact electrode is formed. 6 3 The source, drain and transistor gates can be connected to an external circuit, while the contact electrode 6 3 is formed by depositing metal or conductive materials such as sputtering, evaporation, CVD, etc., such as doping polycrystalline silicon to On the entire intermediate insulating layer, the thickness is 50 to 10, 0 0 A, preferably 2, 0 to 6, 0 0 A, and the metal or conductive material is subsequently etched dry or wet Way to make the desired shape pattern. Subsequently, an insulating film 64 covering the contact electrode 63 is formed and then patterned in a general manner. A pixel electrode 65 for the electric field of the liquid crystal of the LCD unit pixel is formed in the pixel transistor region. Therefore, the TFT panel of the LCD is completed (as shown in FIG. 5P). According to the aforementioned manufacturing method, the crystalline pixel transistor having two gate electrodes and the storage capacitor connected to the pixel transistor are formed in a chip using MIC LC. The pixel region of the LCD substrate, and a crystal driving transistor such as CMOS, are simultaneously formed on the pixel region using a low temperature step. The present invention is an illustration of the T F T panel of L C D, but the principle of the present invention can also be

Page 23 1223455 Case No. 92lj2〇18 Description of the invention (19) The TFT panel used for 0! LD need not undergo any modification and change. Figure 6A is the gate and connection of the voltage-driven 〇ELd cable: to the information source g i j :: includes the connection to the gate bus u ^ 4 The source and sink of the pulsating bus line

T71. The address T ”71 is connected in parallel with the storage capacitor 72 that keeps the address of the TFT driver, and a pixel mu electrode is used to receive the reference voltage (㈣) to output organic electricity: the driving electricity of the material (Vc). Because After the TFT LCD is not self-generating, a pixel TFT that applies electricity to the pixel electrode is used for single operation. Ϊ 道 Ϊ = Because only the data signal voltage is used, 〇ELD cannot obtain a luminescence phenomenon due to the existence of electronic light emitting materials. The electronic ink I of One Plus is used as an addressing TFT 接受 that accepts gate signals, and the pixel drives TFT 73. The output element is referred to! ^ Figure 6 β, which is a current-driven 0 ELD TF τ surface handle 00 silly The equivalent circuit diagram of the current and current driving type 0ELD 2TFT panel-there are two addressing TFTs 74 7 R on a single pixel An / At irn early element line, (々1 来) Λ from the news and the number one Open to accept a new addressing TFT 75 addressing information from the confluence of information and information, and then open the signal from the second cake f Ψ:) to provide the first addressing TFT 74 ° sink pixel driver Gate and storage capacitor 76 of TFT 77 and 78. ST 74 and second fixed voltage Address TFT 75, the charge is accumulated in the storage capacitor 76 of the wheel voltage. Subsequently, the driving voltage is applied to the first and second generation

Page 24 1223455 ____ Case No. 92112018_ Month and Year: _ V. Description of the invention (20) The gate of the element-driven TFT 7 7, 7 8 is turned on, even if the second address τ F τ 7 5 is turned on, voltage application To the storage capacitor to keep the pixel driving TFTs 7 7 and 7 8 turned on until another signal period, so that the driving current can be continuously supplied to the unit pixels of the oELD. The pixel region and the peripheral region of the crystalline OLED panel of OELD are formed on a common substrate at the same time. In order to effectively drive a driving circuit such as a switching device, the pixel region needs to have a low off current (I 0ff), such as no gate voltage. State, current flows to the pixel transistor (hereinafter, the pixel transistor of OELD is considered to include the addressing TFT and the pixel driving TFT, unless they are opposite), and the surrounding area needs to have a high on-current (I ο η), such as a gate In the state where the polar voltage is used, a current flows to the thin film transistor. In the crystalline OLED panel of OELD, the off-current of the thin film transistor that directly supplies current to the storage capacitor is preferably lower than IE-11A, especially the addressing TFT 71 in FIG. 2A and the second addressing TFT in FIG. 2B. 75. If the off current of the addressing TFT is higher than 1E-1 1 A, even if the output of the addressing TFT 71 in FIG. 2A and the second addressing TFT 75 in FIG. 2B cause the individual potentials of the storage capacitors 7 2 and 7 6, they cannot be maintained. The charge is accumulated until the next signal period. Therefore, there is a problem that the gate potential of the pixel driving TTF cannot be maintained, and the on state of the pixel driving TFT cannot be maintained. Although it has good on-current characteristics, the crystalline polycrystalline silicon TFT with M I LC has a relatively high off-current. However, according to the present invention, this problem can be solved by forming a plurality of gate electrodes in the pixel transistor. The gate capacitors formed by addressing T F T can directly provide current to the storage capacitors in the pixel area, which can solve the off-current problem of the TFT panel of the OELD. Subsequently, the addressing TFTs can maintain the voltage created by the storage capacitors during the signal period. TFT side of OELD

Page 25 1223455 _Case No. 92112018_ Revised Month_ Five. Description of the Invention (21) The board is manufactured by the manufacturing method described in Figures 5 A to 50. Although only one pixel TFT is described, other pixel transistors can also be used. It is formed in a pixel area according to this condition. In the above manufacturing method, in order to induce crystallization of the amorphous silicon layer, Ni that induces low-temperature crystallization is applied to the amorphous silicon layer to guide the heat treatment. In the present invention, Ni is applied to amorphous silicon, and the substrate is heated at 2000 to 700 ° C. In the deposition step, Ni to amorphous silicon reacts with silicon to generate a silicide of the metal, and Ni is deposited. To the gate oxide layer and the gate metal remains in a metallic state. When or before the subsequent crystallization heat treatment, the silicide of the metal formed on the surface of the amorphous silicon is not oxidized when exposed to the atmosphere, and therefore the problem of deterioration of the crystalline quality of silicon due to oxidation of the metal that induces crystallization can be prevented. Since it remains in a metallic state, Ni deposited on other portions can be selectively removed by a conventional etching step. After the Ni layer is deposited, an etching step is immediately conducted to form a very thin and uniform Ni layer. While the Ni layer is being deposited on Shi Xi, a very thin nickel silicide layer is formed by reacting with Shi Xi, and During the etching step, excess Ni that does not form nickel silicide is removed, and at the same time, the Ni layer deposited on other parts, such as the gate electrode or the substrate, can be completely removed. A very thin nickel silicide with a thickness of about 1 A is sufficient to cause the M I L C of the amorphous silicon layer. The reagent in the etching step is selective between nickel silicide and metallic nickel. For example, ferric chloride, 1HC03 / 5HC1, 150CH3 C Ο Ο Ο / 5 0 Η N 03/3 HC 1 can be used as an etchant. Using this method, the residue of the M ILC source metal (such as Ni) in silicon Side effects can be minimized. A certain amount of boron is injected into the amorphous silicon to conduct the heat treatment in advance, and the crystallization speed and crystalline quality such as the grain size and crystalline consistency obtained by the MI LC

Page 26 1223455 _Case No. 92112018_ Revised Month_ V. Description of the Invention (22), a major improvement has been achieved. Therefore, when manufacturing N-type TFTs, before or after implanting the N-type dopants, the deletion is implanted to at least Part of the amorphous stone layer can effectively improve the speed and quality of crystallization through M ILC. In addition, the concentration of boron exceeds 1 X 1 013 / cm2. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of implementation of the present invention. Any person skilled in the art can make some modifications and decorations without departing from the spirit and scope of the present invention. And all equal changes and modifications made in accordance with the present invention shall be covered by the scope of patent application of the present invention, and the definition shall be subject to the scope of patent application. Although it is described in this embodiment that two gate electrodes are formed in a pixel transistor, more gate electrodes can be formed within the scope of the present invention, and although described as forming a CMOS in a driving region, the driving circuit includes various thin film transistors. For example, P-M0S, N-M0S, and CMOS or a combination thereof may be formed in the driving region. In addition, although a single gate electrode is formed in the driving transistor described in this embodiment, it may also include more than two gate electrodes. In addition, although it is described that the gate patterns of N-TFT and P-TFT are formed separately, and the replacement is also an injection of N-TFT and P-TFT, the gate patterns can be formed at the same time between N-TFT and P. -TFT, N-TFT and P-TFT can be formed under the condition that the N-TFT region uses a photoresist as a photomask when the N-TFT dopant is implanted, and the P-TFT region uses a photoresist as a photomask. However, if all TFTs such as pixel transistors and driver transistors are formed using only one type of TFT, these additional mask steps are not required. Therefore, although the electrode describing the storage capacitor is formed of crystalline silicon, the electrode may be replaced by another layer such as a metal layer. Those skilled in the art can use a material different from the gate insulating layer to make a layer, such as an intermediate insulating layer, to form a dielectric layer of a storage capacitor.

Page 27 1223455 _Case No. 92112018_Amended in January__ V. Description of the invention (23) According to the present invention, according to the present invention, a pixel transistor, a storage capacitor and a driving device can be provided by the M I LC in Simultaneously formed on the TFT panel at a low temperature, so that the substrate used as a display device such as an LCD or an OELD is not damaged. And another advantage of the present invention is that the TFT panel of the present invention achieves the required open current characteristics of the pixel transistor and the driving transistor of the LCD or OELD, and because two or more gate electrodes are formed in the pixel transistor, It can also effectively reduce the off current of the pixel transistor to a desired level. In addition, another advantage of the present invention is that a low-concentration doped region and a metal compensation region can be formed on the transistor of the TFT panel through a simple process, and the operating characteristics of the pixel transistor and the driving device can be further improved.

Page 28 1223455 _Case No. 92112018_ Month and Day __ Brief description of the diagram. The first diagram is a schematic diagram of the position of the TFT panel area of the LCD. The second diagram is a structure showing the unit pixels of the TFT panel formed on the LCD. The equivalent circuit diagrams 3A to 3D are cross-sectional views of a conventional method for manufacturing a thin film transistor using MILC. FIG. 4 is a graph of the drain current generated according to the number of gates injected into the TFT manufactured by M ILC. Figures 5A to 5P are cross-sectional views of a crystalline silicon TFT panel manufacturing process for manufacturing an LCD according to the present invention. Figure 6A is an equivalent circuit diagram of a TFT panel unit pixel structure of OELD. Figure 6B is an OELD diagram. The equivalent circuit diagram of the pixel structure of the TFT panel unit is clear, clear, clear, clear, clear, clear, clear ... Absolutely with the broken C dynamic storage with the pole-resistor plate crystal map L drive and storage as the drain light source base non-02241D24602 11223133355 3 · pixel area · · pixel transistor · liquid crystal injection early element insulation substrate · · channel area · · Source region · · Gate electrode · · · Residual metal layer · Track area ·· Shield ··· Amorphous silicon island ·· IX 0〇ο- c ST—I CXI CN3 00 Γ- · 1—I • · · · 3 3 00 7i 1 ± D 3 3 3 5 2 • .. 5

Chapter 1223455

Case No. 92112018_Year Month and Day Revised Schematic Brief Description of Amorphous Silicon Island Electrodes • • 5 7 Gate insulating layer • • 5 8 Layer of dielectric material • • 5 9 Low-concentration doped region • 6 0 Metal offset domain • 6 1 Intermediate insulating layer parameters • 6 2 Contact electrode • • • 6 3 Insulating film • • • 6 4 pixel electrodes • • • 6 5 addressing TFT • • 7 1 storage capacitor • • • 7 2 pixel driving TFT 7 3 addressing TFT • • 7 4 addressing TFT parameters • 7 5 storage capacitor • • • 7 6 pixel driving TFT 7 7 pixel driving TFT • 7 8 pixel area • • • 7 9 driving circuit area • 8 0 photoresist • 8 1 a distance • 8 2 low energy south concentration doping 8 3 south energy low concentration doping • 8 4 Directly deposited area 8 5

Page 30

Claims (1)

1223455 Case No. 9211 Amended in June 2018. Scope of patent application1. A thin film transistor (TFT) panel for a TFT LCD or OELD, which includes: a transparent substrate including a pixel area with several unit pixels and a driver Circuit area; at least one pixel transistor is formed in each unit pixel of the pixel area on the substrate and includes a crystalline silicon active layer, a gate insulating layer, and a gate electrode, respectively; the active layer is metal-induced lateral crystallization (Μ I LC) crystal, a storage capacitor, formed in each unit pixel on the substrate; A plurality of driving transistors are formed in a driving circuit region on the substrate and each include a crystalline silicon action layer, a gate insulating layer, and a gate electrode crystallized in M ILC; wherein at least one pixel transistor is formed with a plurality of gates. electrode. 2. For example, the thin film electric crystal (TFT) panel for TFT LCD or OELD applied for in item 1 of the patent scope, wherein the transparent substrate is a glass substrate. 3. For example, a thin film transistor (TFT) panel for a TFT LCD or an OELD, in which the pixel transistor is composed of N-M0S or P-M0S, and the driving transistor is composed of CMOS. . 4. As for the thin film transistor (T F T) panel for TFT LCD or OELD, the number of gate electrodes is formed in the driving transistor. 5. For the thin film transistor (TFT) panel used for TFT LCD or OELD in the first patent application, the gate insulating layer in the pixel transistor is at least wider than the gate electrode, and the gate insulating layer is used as the Photomask for low energy high Page 31 1223455 _Case No. 92112018_Amended in January_ Sixth, the patent application range of concentration doping, and then using the gate electrode as a photomask for high energy and low concentration doping, around the channel area of the pixel transistor, obtain a A low-concentration doped region having a dopant concentration of 1E1 4 / cm 2 or less. 6. For the thin film transistor (TFT) panel used for TFT LCD or OELD in the first patent application, the MILC step is to induce the use of MILC metal to the amorphous silicon layer, and then the pixel transistor and the driver The gate insulation layer of the crystal is wider than the gate electrode, and the layer is annealed with the gate electrode and the gate insulation layer as a photomask. 7. For a thin film transistor (TFT) panel for a TFT LCD or OELD, as claimed in item 6, the MILC-inducing metal used for doping includes at least Ni, Pd, Ti, Ag, Au, A1, Sn, One of Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, and Pt. The thickness is 1 to 200A. The sputtering method, evaporation method, or C VD method is used, and the annealing step is performed in a furnace at a temperature of 4 0 to 0. 0.1 to 50 hours at 60 ° C. 8. As for the thin film transistor (TFT) panel for TFT LCD or OELD under the scope of patent application, before the pixel transistor, the storage capacitor and the driving transistor are formed, a glass substrate is formed to prevent doping. Shielding layer for debris diffusion. 9. If the thin film transistor (TFT) panel for TFT LCD or OELD is applied for item 1 of the patent scope, it also includes an intermediate insulating layer and a patterned contact between the pixel transistor, the storage capacitor and the driving transistor. electrode. 10. For example, a thin film transistor (TFT) panel for a TFT LCD or OELD in the scope of patent application, wherein the storage capacitor includes a MILC crystal 1232455 on page 32 _Case No. 92112018_Amended in January_ Sixth, the patented crystalline silicon layer and a dielectric layer and a capacitor electrode formed subsequently on the crystalline silicon layer, the crystalline silicon layer and storage of the pixel transistor The crystalline silicon layers of the capacitor are connected to each other. The gate insulating layer of the pixel transistor and the dielectric layer of the capacitor are simultaneously formed of the same material, and the gate electrode and the capacitor electrode of the pixel transistor are simultaneously formed of the same material. 1 1 · The thin film transistor (TFT) panel for a TFT LCD or OELD as claimed in item 1 of the patent application scope, wherein the pixel transistor includes at least one addressing transistor, at least one pixel driving transistor, and at least one having a plurality of gates. Electrode, an addressing transistor that supplies current to a storage capacitor. 1 2. The thin film transistor (TFT) panel for a TFT LCD or OELD as claimed in item 1 of the scope of the patent application, wherein the active layer of the pixel transistor is crystallized by depositing a source of M ILC source metal, and simultaneously heating the substrate at a temperature Heat treatment of the substrate between 2 0 and 7 0 ° C. 1 3. The thin film transistor (TFT) panel for a TFT LCD or OELD as claimed in item 1 of the patent application scope, wherein the active layer of the pixel transistor is crystallized by depositing a nickel layer thereon; made of ferric chloride, 1HC03 / 5HC1, 150CH3 COOH / 50HNO3 / 3HCl selective etchant is used to etch the deposited nickel layer; and a substrate is heat-treated. 14. The thin film transistor (TFT) panel for a TFT LCD or OELD as claimed in item 1 of the patent application scope, wherein before the heat treatment is induced to induce the active layer to perform MILC, the boron concentration of the active layer injected into the pixel transistor exceeds 1 X 1 013 / cm2 〇 Page 33