JP3455721B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for obtaining a crystalline semiconductor used in a thin film device such as a thin film insulating gate type field effect transistor (thin film transistor or TFT).

[0002]

2. Description of the Related Art Conventionally, crystalline silicon semiconductor thin films used for thin film devices such as thin film insulating gate type field effect transistors (TFTs) are plasma CVD or thermal CV.
The amorphous silicon film formed by the method D was crystallized in a device such as an electric furnace at a temperature of 600 ° C. or higher for a long time of 24 hours or more. In particular, a longer heat treatment was required in order to obtain sufficient characteristics (high field effect mobility and high reliability).

[0003]

However, such a conventional method has many problems. One is low throughput and therefore high cost. For example, if it takes 24 hours for this crystallization step, 720 substrates must be processed at the same time if the processing time per substrate is 2 minutes. However, for example, in a commonly used tubular furnace, the number of substrates that can be processed at one time is 50 at most, and when only one apparatus (reaction tube) is used, it takes as long as 30 minutes per substrate. I got it. Ie 1
To achieve a processing time of 2 minutes per sheet, 15 reaction tubes had to be used. This meant that the scale of the investment increased and that the depreciation of the investment was large, and that it was reflected in the cost of the product.

Another problem was the temperature of the heat treatment. In general, substrates used for manufacturing TFTs are roughly classified into those made of pure silicon oxide such as quartz glass, and non-alkali borosilicate glass such as Corning No. 7059 (hereinafter, Corning 7059). Of these, the former has excellent heat resistance and can be handled in the same manner as a normal semiconductor integrated circuit wafer process, and therefore has no problem with temperature. However, its cost is high, and it exponentially increases exponentially as the substrate area increases. Therefore, at present, T
Used only in FT integrated circuits.

On the other hand, alkali-free glass has a sufficiently low cost as compared with quartz, but has a problem in heat resistance, and generally has a strain point of about 550 to 650 ° C., and particularly easily available materials at 600 ° C. or lower. Therefore, the heat treatment at 600 ° C. causes irreversible shrinkage and warpage of the substrate. In particular, it was remarkable in a large substrate having a diagonal of more than 10 inches. For the above reasons, regarding the crystallization of the silicon semiconductor film, the heat treatment condition of 550 ° C. or lower and within 4 hours has been indispensable for cost reduction. An object of the present invention is to provide a method for manufacturing a semiconductor that satisfies such conditions and a method for manufacturing a semiconductor device using such a semiconductor.

[0006]

The structure of the present invention is provided on a substrate selectively with nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese,
A first step of forming an object containing at least one of copper, zinc, gold and silver; a second step of forming a silicon film in a substantially amorphous state after the step; and a second step of It is characterized by including a third step of annealing the substrate later and a fourth step of patterning the silicon film in an island shape.

Further, in the above structure, after the third step, there is a fourth step of treating the substrate with an acid containing hydrofluoric acid or hydrochloric acid.

In the above structure, the substrate is annealed to selectively grow crystallization in a width of 20 to 200 μm in a lateral direction from a region where an object exists.

According to another structure of the present invention, the first step of forming a silicon film in a substantially amorphous state on the substrate and, after the step, nickel, iron, cobalt,
Second step of forming an object containing at least one of ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, silver, and second step After that, a third step of annealing the substrate and a fourth step of patterning the silicon film into an island shape are included.

In the above structure, after the third step, there is a fourth step of treating the substrate with an acid containing hydrofluoric acid, nitric acid or hydrochloric acid.

The above structure is characterized in that by annealing the substrate, crystallization is selectively grown laterally from the region where the object is present to a width of 20 to 200 μm.

Another structure of the present invention is: 0.01 atomic% or more and 5 atomic% or less of hydrogen; and 0.0005 atomic% or more and 1 atomic% or less of nickel, iron, cobalt, ruthenium,
A gate electrode is provided on a silicon film containing rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, and silver via an insulating film. To do.

Another structure of the present invention is: 0.01 atomic% to 5 atomic% of hydrogen; 0.0005 atomic% to 1 atomic% of nickel, iron, cobalt, ruthenium,
It is characterized by having a source and / or a drain composed of a silicon semiconductor containing rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold and silver.

Further, according to another structure of the present invention, a first step of forming a substantially amorphous silicon film on a substrate and a second step of forming a mask film having a thickness exhibiting a masking action. A third step of patterning the mask coating to expose the surface of the silicon film, nickel,
Iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium,
A fourth step of forming a film containing at least one of vanadium, chromium, manganese, copper, zinc, gold and silver;
A fifth step of forming a silicide layer by reacting the film formed in the fourth step with the silicon film by thermally annealing the substrate after the fourth step, and the film formed in the fourth step And a seventh step of crystallizing the silicon film adjacent to the silicide layer in the lateral direction by annealing.

Further, according to another structure of the present invention, nickel, iron, cobalt, ruthenium, rhodium,
A first step of selectively forming an object containing at least one of palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, silver; A second step of forming a silicon film in an amorphous state, a third step of annealing the substrate after the second step, and a first step of the silicon film in which the object is selectively formed A fourth step of etching away a portion on the exposed region.

The above structure is characterized in that a region including a growth point of crystal growth is etched at the same time as or after the fourth step.

Further, according to another structure of the present invention, a first step of forming a silicon film in a substantially amorphous state on a substrate, and after the step, nickel, iron, cobalt,
A second step of selectively forming an object containing at least one of ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, silver; After the step 2, there is a third step of annealing the substrate, and a fourth step of etching and removing a portion of the silicon film on the region where the object is selectively formed in the second step. It is characterized by

Further, in the above structure, a region including a growth point of crystal growth is etched at the same time as, or before and after the fourth step.

According to the present invention, a silicon film in an amorphous state or a disordered crystalline state that can be said to be substantially amorphous (for example, a state where a portion having good crystallinity and an amorphous portion are mixed) is used. Above and below nickel, iron, cobalt, ruthenium, rhodium,
Palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, silver island-shaped films or dots, particles, clusters, lines, etc. are formed, and these are formed into ordinary amorphous materials. At a temperature lower than the crystallization temperature of mere heat treatment of silicon,
Further, it is characterized in that a crystalline silicon film is obtained by annealing for a shorter time.

Regarding conventional crystallization of a silicon film, a method of performing solid phase epitaxial growth using a crystalline island-shaped film as a nucleus and using this as a seed crystal (for example, JP-A 1-21).
4110) has been proposed. However, with such a method, crystal growth hardly proceeded at a temperature of 600 ° C. or lower. In a silicon system, in general, in order to shift from an amorphous state to a crystalline state, the molecular chain in the amorphous state is divided, and the divided molecule is made into a state in which it does not bond with other molecules again, It goes through the process of recombining a molecule with a part of the crystal according to some crystalline molecule. However, in this process, the energy for breaking the first molecular chain and holding it in a state where it does not bind to other molecules is large,
This is a barrier in the crystallization reaction. To give this energy, at a temperature of about 1000 ° C for a few minutes,
Alternatively, at a temperature of about 600 ° C., several tens of hours are required, and the time exponentially depends on the temperature (= energy). Therefore, at 600 ° C. or lower, for example, 550 ° C., the crystallization reaction hardly progresses. I could not observe it. The conventional idea of solid phase epitaxial crystallization did not give a solution to this problem.

The present inventor has considered that the barrier energy of the above process is lowered by some catalytic action, in addition to the conventional idea of solid phase crystallization. The present inventor has found that nickel (elemental symbol Ni), iron (Fe), cobalt (C
o), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (I
r), platinum (Pt), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), copper (Cu), zinc (Zn), gold (Au),
Silver (Ag) easily bonds with silicon.

For example, in the case of nickel, it has been noted that nickel silicide is easily obtained (chemical formula NiSi _x , 0.4 ≦ x ≦ 2.5), and the lattice constant of nickel silicide is close to that of silicon crystal. Therefore, as a result of simulating the energy of the ternary system of crystalline silicon-nickel silicide-amorphous silicon, amorphous silicon easily reacts at the interface with nickel silicide, and amorphous silicon (silicon A) + nickel silicide (silicon B) → It became clear that the reaction of nickel silicide (silicon A) + crystalline silicon (silicon B) (silicon A and B indicate the position of silicon) occurs. The potential barrier of this reaction is sufficiently low and the reaction temperature is also low. This reaction formula shows that nickel proceeds while converting amorphous silicon into crystalline silicon. Actually, at 580 ° C. or lower, the reaction starts and
It became clear that the reaction was observed even at 0 ° C. As a matter of course, the higher the temperature, the faster the reaction proceeds. Similar effects were also observed with the other metal elements shown above.

In the present invention, islands, stripes, lines,
Dot-shaped and film-shaped nickel and other metal elements and their silicides, such as Ni, Fe, Co, Ru, Rh,
Pd, Os, Ir, Pt, Sc, Ti, V, Cr, M
Starting from a film, particles, clusters, etc. containing at least one of n, Cu, Zn, Au, and Ag, these metal elements develop from here to the surroundings with the above-mentioned reaction, whereby crystals are obtained. Expand the silicon area. Note that oxide is not preferable as the material containing these metal elements. This is because the oxide is a stable compound and cannot initiate the above reaction.

The crystalline silicon thus spread from a specific place has a structure close to a single crystal with good continuity of crystallinity, which is different from the conventional solid phase epitaxial growth. It is convenient for use in devices. However, when a material containing nickel or another metal that promotes crystallization is uniformly provided on the substrate, there are innumerable starting points for crystallization, so that a film with good crystallinity cannot be obtained. was difficult.

Further, the amorphous silicon film as the starting material for this crystallization had better results as the hydrogen concentration was lower. However, since hydrogen is released as the crystallization progresses, the hydrogen concentration in the obtained silicon film was not so clearly correlated with the hydrogen concentration in the starting amorphous silicon film. The hydrogen concentration in crystalline silicon according to the present invention is typically 0.01 atomic%.
It was 5 atomic% or less.

In the present invention, Ni, Fe, Co, Ru, R
h, Pd, Os, Ir, Pt, Sc, Ti, V, Cr,
Mn, Cu, Zn, Au and Ag are used, which are generally used.
These materials are preferred for silicon as a semiconductor material.
Not good. So it is necessary to remove this
However, regarding nickel, as a result of the above reaction,
When the nickel silicide reaches the end, hydrofluoric acid or hydrochloric acid or
It dissolves easily in these diluents, so
Processing can reduce nickel from the substrate
It Furthermore, in order to actively reduce these metal elements,
After completion of the crystallization process, hydrogen chloride, various methane chlorides
(CH₃ Cl, CH₂ Cl₂ , CHCl₃ ), Various chlorides
Ethane (C₂ H_Five Cl, C₂ H_Four Cl₂ , C₂ H₃ Cl
₃ , C₂ H₂ Cl _Four , C₂ HCl_Five ) Or various chlorides
Ethylene (C₂ H₃ Cl, C₂ H₂ Cl₂, C₂ HCl₃
 ) In a chlorine-containing atmosphere at 400 to 600 ° C.
Just make sense. In particular, trichlorethylene (C₂ HCl
₃ ) Is a material that is easy to use. Silicon according to the invention
Ni, Fe, Co, Ru, Rh, Pd, Os, I in the film
r, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn,
The concentration of Au and Ag is typically 0.0005 atomic% or less.
The upper limit was 1 atomic% or less.

When the crystalline silicon film produced according to the present invention is used in a semiconductor element such as a TFT, as is apparent from the above description, the end of crystallization (here, the crystallization started from a plurality of starting points is used). Is the part where
There are large grain boundaries (discontinuous portions of crystallinity), and
It is not preferable to provide a semiconductor element because the concentration of nickel and other metal elements that promote crystallization is high. Therefore, in forming a semiconductor device using the present invention, the pattern of the metal element-containing material coating film that promotes crystallization such as nickel, which is the starting point of crystallization, and the pattern of the semiconductor device must be optimized. .

In the present invention, there are roughly two methods for patterning a metal element that promotes crystallization. The first method is a method of selectively forming these metal films and the like before forming the amorphous silicon film. Second
The above method is a method of selectively forming these metal films and the like after forming the amorphous silicon film.

In the first method, ordinary photolithography means or lift-off means may be used. The second method is rather complicated. In this case, if a metal film or the like that promotes crystallization is formed in close contact with the amorphous silicon film, the metal partially reacts with the amorphous silicon during the film formation to form a silicide. Therefore,
When patterning is performed after forming a metal film or the like, it is necessary to sufficiently etch such a silicide layer.

In the second method, the lift-off method is relatively easy. In this case, an organic material such as photoresist or an inorganic material such as silicon oxide or silicon nitride may be used as the mask material. Process temperature must be taken into account when selecting the mask material. In addition, the masking action differs depending on the material, so care must be taken. In particular, a film of silicon oxide, silicon nitride, or the like formed by various CVD methods has many pinholes, and if the film thickness is not sufficient, crystallization may proceed from an unintended portion. Generally, after using these mask materials to form a film, patterning is performed to selectively expose the surface of the amorphous silicon. Then, a metal film or the like that promotes crystallization is formed.

In the present invention, what must be noted is the concentration of the metal element in the silicon film. It is good to have a small amount, but more importantly, it is important to always keep the amount constant. That is, if there is a large variation in the amount of metal element, the degree of crystallization will vary greatly from lot to lot at the manufacturing site. In particular, when a small amount of metal element is required, it becomes more and more difficult to reduce the fluctuation of the amount.

In the first method, since the selectively formed metal film or the like is covered with the amorphous silicon film, it is not possible to take out the metal film and adjust its amount later. In particular, when calculated from the amount of the metal element required in the present invention, the thickness of the metal film or the like is as small as several to several 10Å, and it is difficult to form the film with good reproducibility.

The same applies to the second method. However, in the second method, since the metal film or the like that promotes crystallization exists on the surface, there is still room for improvement as compared with the first method. That is, a sufficiently thick metal film is formed,
Before annealing, heat treatment (pre-annealing) is performed at a temperature lower than the annealing temperature to react a part of the amorphous silicon film with the metal film to form a silicide. After that, the metal film that has not reacted is etched.
Depending on the type of metal used, especially Ni, Fe, Co, T
Since i and Cr have an etchant having a sufficiently high etching rate for the metal film and the silicide, there is no problem.

In this case, the thickness of the silicide layer obtained is determined by the temperature and time of the heat treatment (pre-annealing). The thickness of the metal film is almost irrelevant. Therefore, it is possible to control the amount of a very small amount of metal element introduced into the amorphous silicon film.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Examples and reference examples are shown below,
The present invention will be described in more detail.

[0036]

EXAMPLES Reference Example 1 This reference example is Corning 70
59 forming a plurality of island-shaped nickel films on a glass substrate,
A method of crystallizing an amorphous silicon film using these as a starting point and using the obtained crystalline silicon film to manufacture a TFT will be described. There are two methods for forming the island-shaped nickel film, depending on whether it is provided on the amorphous silicon film or below it.
FIG. 2A-1 shows a method provided below, and FIG.
2) is a method provided above. Especially, regarding the latter, it is necessary to pay attention to the step of selectively etching nickel after the nickel is formed on the entire surface of the amorphous silicon film. Nickel is formed. If this is left as it is, a good crystalline silicon film intended by the present invention cannot be obtained, so it is required to sufficiently remove the nickel silicide with hydrochloric acid, hydrofluoric acid or the like. . Also, because of this, the amorphous silicon becomes thinner than it was initially.

On the other hand, in the former case, such a problem does not occur, but in this case as well, the island portion 2 is formed by etching.
It is desired that the nickel film other than the above is completely removed.
Further, in order to suppress the influence of residual nickel, the substrate may be treated with oxygen plasma, ozone or the like to oxidize nickel other than the island region.

In either case, the substrate (Corning 705
9) On top of 1A, a base silicon oxide film 1B having a thickness of 2000Å
Was formed by the plasma CVD method. The amorphous silicon film 1 has a thickness of 200 to 3000 Å, preferably 500 to 1500 Å, and was produced by a plasma CVD method or a low pressure CVD method. The amorphous silicon film is annealed at 350 to 450 ° C. for 0.1 to 2 hours to release hydrogen, and the hydrogen concentration in the film is adjusted to 5
It was easy to crystallize when the atomic percentage was kept below. Figure 2 (A
In the case of -1), a nickel film having a thickness of 50 to 100 is formed by sputtering before the formation of the amorphous silicon film 1.
0 Å, preferably 100 to 500 Å was deposited and patterned to form the island-shaped nickel region 2.

On the other hand, in the case of FIG. 2A-2, a nickel film having a thickness of 50 to 1000 Å, preferably 100 to 100, is formed by sputtering after the formation of the amorphous silicon film 1.
500 Å was deposited and patterned to form island-shaped nickel regions 2. A drawing of this situation viewed from above is shown in FIG.
It shows in (A).

The island-shaped nickel is a square having a side length of 2 μm, and its interval is 5 to 50 μm, for example, 20 μm. The same effect can be obtained by using nickel silicide instead of nickel. Also, the substrate is 100 to 5 when the nickel film is formed.
Good results were obtained by heating to 00 ° C, preferably 180 to 250 ° C. This is because the adhesion between the underlying silicon oxide film and the nickel film is improved, and the reaction between silicon oxide and nickel produces nickel silicide. Similar effects can be obtained by using silicon nitride, silicon carbide, or silicon instead of silicon oxide.

Next, this is heated at 450 to 580 ° C., for example, 5
Annealing was performed at 50 ° C. for 8 hours in a nitrogen atmosphere. Figure 2
2B is an intermediate state thereof, in FIG. 2A, nickel proceeds from the island-shaped nickel film near the end to the central portion as nickel silicide 3A, and the portion 3 through which nickel has passed is crystallized. It is silicon. Eventually, Figure 2
As shown in (C), the crystallization starting from two island-shaped nickel films collides with each other, leaving nickel silicide 3A in the middle, and the crystallization is completed.

FIG. 1 (B) shows a state of the substrate in this state viewed from above. The nickel silicide 3 shown in FIG. 2 (C) is used.
A is the grain boundary 4. If annealing is further continued, nickel moves along the grain boundaries 4 and collects in the intermediate region 5 of these island-shaped nickel regions (although the original shape is not fixed at this stage).

Although crystalline silicon can be obtained by the above steps, it is not preferable that nickel diffuses into the semiconductor film from the nickel silicide 3A produced at this time. Therefore, it is desired to remove the high concentration region where nickel is concentrated by etching with hydrofluoric acid or hydrochloric acid. Note that etching with hydrofluoric acid or hydrochloric acid does not affect the silicon film because the etching rates of nickel and nickel silicide are sufficiently high. At the same time, the region where the nickel growth point was present was also removed. The state of etching is shown in FIG. Groove 4 was the part where there was a grain boundary
It becomes A. It is not preferable to form the semiconductor region (active layer or the like) of the TFT so as to sandwich this groove. An example of the arrangement of the TFTs is shown in FIG. 1C, but the semiconductor region 6 is arranged so as not to cross the grain boundaries 4. That is, the TFT is formed in the lateral crystal growth region in the direction parallel to the substrate, not in the thickness direction of the film, due to the left and right sides of nickel. Then, the crystal growth directions are also uniform,
Further, the amount of residual nickel can be extremely reduced. As a result, high TFT characteristics can be obtained. On the other hand, the gate wiring 7 may cross the grain boundary 4.

An example of manufacturing a TFT using the crystalline silicon obtained in the above steps is shown in FIGS. Figure 3
In (A), the X at the center means the place where the groove 4A in FIG. 2 was. As shown in the drawing, the semiconductor region of the TFT was arranged so as not to cross the X portion. That is, the crystalline silicon film 3 obtained in the step shown in FIG. 2 was patterned to form the island-shaped semiconductor regions 11a and 11b. Then, the silicon oxide film 12 functioning as a gate insulating film was formed by a method such as an RF plasma CVD method, an ECR plasma CVD method, and a sputtering method.

Further, phosphorus was added to 1 × by the low pressure CVD method.
10 ²⁰ -5 × 10 ²⁰ cm ^-3 Doped thickness 3000-
A 6000 Å polycrystalline silicon film was formed and patterned to form gate electrodes 13a and 13b.
(Fig. 3 (A))

Next, impurity doping was performed by the plasma doping method. As the doping gas, for example, phosphine (PH ₃ ) was used for the N type and diborane (B ₂ H ₆ ) was used for the P type. In the figure, an N-type TFT is shown.
The acceleration voltage is 80 keV for phosphine and 6 for diborane.
It was set to 5 keV. Further, annealing was performed at 550 ° C. for 4 hours to activate the impurities and form the impurity regions 14a to 14d. A method using light energy such as laser annealing or flash lamp annealing can also be used for activation. (Fig. 3
(B))

Finally, a silicon oxide film having a thickness of 5000 Å is deposited as an inter-layer insulator 15 and contact holes are formed in the film to form wirings / electrodes 16a to 16d in the source region and the drain region in the same manner as in normal TFT fabrication. Was formed.
(FIG. 3 (C)) A TFT (N-channel type in the figure) was manufactured through the above steps. The field effect mobility of the obtained TFT is 40 to 60 cm ² / Vs for N-channel type and 30 to 30 for P-channel type.
It was 50 cm ² / Vs.

FIG. 4 shows a case where an aluminum gate TFT is manufactured. In FIG. 4A, the X in the center means the place where the groove 4A in FIG. 2 was. As shown in the drawing, the semiconductor region of the TFT was arranged so as not to cross the X portion. That is, the crystalline silicon film 3 obtained in the step shown in FIG. 2 was patterned to form the island-shaped semiconductor regions 21a and 21b. And RF
A silicon oxide film 22 functioning as a gate insulating film was formed by a method such as plasma CVD method, ECR plasma CVD method, or sputtering method. When the plasma CVD method is adopted, the source gas is TEOS (tetra-ethoxy-
Preferred results have been obtained with (silane) and oxygen. Then, an aluminum film (thickness 50
00Å) was deposited by a sputtering method and patterned to form the gate wiring / electrodes 23a and 23b.

Next, the substrate was immersed in a 3% ethylene glycol solution of tartaric acid, platinum was used as a cathode, and aluminum wiring was used as an anode. A current was passed through this to carry out anodization. The current was initially applied so that the voltage was increased at 2 V / min, the voltage was kept constant when 220 V was reached, and the current was stopped when the current became 10 μA / m ² or less. As a result, the thickness of the anodic oxide 24a of 2000 Å, 2
4b was formed. (Fig. 4 (A))

Next, the impurities are impure by the plasma doping method.
The thing dope was done. N-type doping gas
Phosphine (PH₃ ), And P-type for diborane (B
₂ H ₆ ) Was used. The figure shows an N-channel TFT.
The acceleration voltage is 80 keV for phosphine and 6 for diborane.
It was set to 5 keV. This may be laser annealed.
By the activation of impurities, the impurity region 2
5a-25d were formed. The laser used is KrF
Laser (wavelength 248nm), 250-300mJ /
cm² 5 shots of laser light with energy density
did. (Fig. 4 (B))

Finally, a silicon oxide film having a thickness of 5000 Å is deposited as an inter-layer insulator 26, and contact holes are formed in it to form wirings / electrodes 27a to 27d in the source region and the drain region, as in the normal TFT fabrication. Was formed.
(FIG. 4C) The field-effect mobility of the obtained TFT is 60 for the N-channel type.
~ 120cm ² / Vs, P-channel type 50 ~ 90cm
It was ² / Vs. In addition, a shift register manufactured using this TFT has a drain voltage of 17 V and 6 MHz,
Operation at 11 V at 20 V was confirmed.

Reference Example 2 FIG. 5 shows a case in which an aluminum gate TFT is manufactured similarly to FIG. However, here, amorphous silicon was used as the active layer. As shown in FIG. 5A, a base silicon oxide film 32 is deposited on the substrate 31, and the thickness of 2000 to 30 is further increased.
A 00Å amorphous silicon film 33 was deposited. An appropriate amount of P-type or N-type impurities may be mixed in the amorphous silicon film. Then, as described above, the island-shaped nickel or nickel silicide coating 34 is formed.
A and 34B were formed and an amorphous silicon film was crystallized by lateral growth by annealing in this state at 550 ° C. for 8 hours or 600 ° C. for 4 hours.

Next, the crystalline silicon film thus obtained was patterned as shown in FIG. 5 (B). At this time, since a large amount of nickel is contained in the silicon film in the center portion (intermediate portion of nickel or nickel silicide coatings 34A, 34B) in the drawing, patterning is performed so as to remove it, and the island-shaped silicon region 35A, 35B was formed.
Furthermore, a substantially intrinsic amorphous silicon film 3 is formed thereon.
6 was deposited. After that, as shown in FIG. 5C, a film is formed as the gate insulating film 37 with a material such as silicon nitride or silicon oxide, and the gate electrode 38 is formed with aluminum, and anodization is performed as in the case of FIG. The impurity region 39 by diffusing the impurities by the ion doping method.
A and 39B are formed. Further, an interlayer insulator 40 is deposited, contact holes are formed, and metal electrodes 41A, 41
The TFT is completed by forming B on the source and drain. This TFT is characterized in that the semiconductor film in the source and drain portions is thicker and the resistivity is smaller than the thickness of the active layer. As a result, the resistance in the source and drain regions is reduced, and the TFT characteristics Is improved. Moreover, the formation of contacts is easy.

Reference Example 3 FIG. 6 shows a CMOS type T
The case where FT fabrication is performed is shown. As shown in FIG. 6A, a base silicon oxide film 52 was deposited on a substrate 51, and an amorphous silicon film 53 having a thickness of 1000 to 1500Å was further deposited. Then, as described above, the island-shaped nickel or nickel silicide film 54 is formed and annealed at 550 ° C. in this state. By this step, the silicon silicide region 55 moves not in the thickness direction of the film but in the plane direction, and crystallization proceeds. By the annealing for 4 hours, the amorphous silicon film is changed to crystalline silicon as shown in FIG. Further, the silicon silicides 59A and 59B are driven to the edge due to the progress of crystallization.

Next, the crystalline silicon film thus obtained was patterned as shown in FIG. 6B to form island-shaped silicon regions 56. At this time, it should be noted that both ends of the island region have a high nickel concentration. After forming the island-shaped silicon region, the gate insulating film 57 and the gate electrodes 58A and 58B were formed.

After that, as shown in FIG. 5C, impurities are diffused by an ion doping method to form N-type impurity regions 60A and P-type impurity regions 60B. At this time, for example, phosphorus (doping gas is phosphine PH ₃ ) is used as an N-type impurity, the entire surface is doped with an accelerating voltage of 60 to 110 kV, and then a photoresist is used to cover the N-channel TFT region. P-type impurities such as boron (the doping gas is diborane B ₂ H
₆ ) may be used for doping with an acceleration voltage of 40 to 80 kV.

After the doping is completed, the source and drain are activated by laser beam irradiation as in the case of FIG. 4, and further an interlayer insulator 61 is deposited, contact holes are formed, and metal electrodes 62A and 62B are formed. , 62C are formed on the source and drain to complete the TFT.

[Embodiment ] This embodiment is shown in FIG. In this embodiment, the nickel film and a part of the amorphous silicon film are reacted by the first heat treatment (pre-annealing) to obtain a silicide, and the unreacted nickel film is removed.
The present invention relates to a method of crystallizing by annealing.

An underlying silicon oxide film (thickness 2000Å) was formed on a substrate (Corning No. 7059) 701 by a sputtering method. Then, a silicon film 703 having a thickness of 300 to 800 Å, for example, 500 Å was formed by the plasma CVD method. Further, a silicon oxide film 704 was formed by the plasma CVD method. This silicon oxide film 704
Is a mask material. The preferred thickness is 500-2000Å. If it is too thin, crystallization will proceed from unintended locations due to pinholes, and if it is too thick, film formation will take time, which is not suitable for mass production. Here, it is set to 1000Å.

After that, the silicon oxide film 704 was patterned by a known photolithography process. Then, a nickel film (thickness 500Å) 7 is formed by the sputtering method.
05 was formed. The thickness of the nickel film was preferably 100Å or more. (FIG. 7 (A)) and 2 in a nitrogen atmosphere.
Annealing was performed at 50 to 450 ° C. for 10 to 60 minutes (pre-annealing step). For example, it was annealed at 450 ° C. for 20 minutes.
As a result, the nickel silicide layer 7 is formed in the amorphous silicon.
06 was formed. The thickness of this layer was determined by the temperature and time of the pre-annealing, and the thickness of the nickel film 705 had almost no influence. (Fig. 7 (B))

After that, the nickel film was etched. A nitric acid-based or hydrochloric acid-based solution was suitable for etching. With these etchants, the nickel silicide layer was barely etched during the etching of the nickel film. In this example, an etchant obtained by adding acetic acid as a buffer to nitric acid was used. Ratio is nitric acid: acetic acid: water = 1: 1
It was set to 0:10. After removing the nickel film,
Annealed for 4 to 8 hours (crystallization annealing step).

Several methods were tried in the crystallization annealing process. The first method is a method in which the mask material 704 is left as shown in FIG. 7C. Crystallization proceeds as shown by the arrow in FIG. The second is a method in which all the mask material is removed, the silicon film is exposed, and annealing is performed. Third, after removing the mask material as shown in FIG. 7D, a new film 7 of silicon oxide or silicon nitride is newly formed.
This is a method of performing annealing after forming 07 as a protective film on the surface of the silicon film.

The first method is a simple method, but the surface of the mask material 704 reacts with nickel in the pre-annealing step, and this becomes silicate in the crystallization annealing step at a higher temperature, which makes etching difficult. . That is, since the etching rates of the silicon film and the mask material 704 are almost the same, the exposed portion of the silicon film is also largely etched when the mask material is subsequently removed, and a step is formed on the substrate.

The second method is extremely simple, and etching is easy before the crystallization annealing step because the reaction between nickel and the mask material is gradual. However, since the silicon surface is entirely exposed during the crystallization annealing, the characteristics when a TFT or the like is manufactured later are deteriorated.

In the third step, a good quality crystalline silicon film can be surely obtained, but the number of steps is increased and it is complicated. Third
As a fourth improved method of the above method, the silicon surface is exposed to the furnace and exposed to the furnace at 500-550 ° C. for 1 hour.
By heating in an oxygen stream for about 2 hours, 2
A method of forming a thin silicon oxide film having a thickness of 0 to 60 Å, and then switching to a nitrogen stream and setting the crystallization annealing condition as it was was examined. In this method, an oxide film is formed in the initial stage of crystallization, and moreover, only the vicinity of the nickel silicide layer is crystallized in this stage of oxidation, the area used later for the TFT (the right part of the figure). ), Crystallization did not occur. For this reason, the surface of the silicon film was very flat, especially in the region far from the nickel silicide layer 706. The characteristics are
It was improved over the second method and was almost the same as the third method.

Thus, a crystalline silicon film was obtained. Then, the silicon film 703 was patterned. Thus, the high-concentration value portion of nickel (the area where the growth was made) and the growth point (the hatched portion at the tip of the arrow in the figure) were removed to leave only the low-concentration nickel area. Thus, the island-shaped silicon region 708 used for the active layer of the TFT is formed.
Was formed. Then, a gate insulating film 709 of silicon oxide having a thickness of 1200 Å was formed so as to cover this by a plasma CVD method. Furthermore, a phosphorus-doped silicon film (thickness 60
00 Å) the gate electrode 710 and the wiring 71 of the first layer
1 was formed and impurities were self-alignedly injected into the active layer 708 using the gate electrode 710 as a mask to form source / drain regions 712. After that, it is effective to irradiate visible / near-infrared strong light to further enhance the crystallinity. Further, a silicon oxide film (having a thickness of 6000 Å) was formed by a plasma CVD method to form an interlayer insulator 713. Finally, a contact hole was formed in this interlayer insulator, and a second layer wiring 714 and a source / drain electrode / wiring 715 were formed with an aluminum film (thickness 6000Å). The TFT was completed by the above steps. (Fig. 7 (E))

[0067]

INDUSTRIAL APPLICABILITY As described above, the present invention is epoch-making in the sense that it accelerates the crystallization of amorphous silicon at a low temperature and in a short time.
Since the devices and methods are extremely general and are excellent in mass productivity, the benefits to the industry are immeasurable. Although the description has been made mainly about nickel in the examples, similar steps are performed in the same manner as in other crystallization promoting metal elements, that is, Fe, Co, Ru, Rh, Pd, Os, Ir and P.
t, Sc, Ti, V, Cr, Mn, Cu, Zn, Au,
It can be applied to any of Ag.

For example, since the conventional solid phase growth method requires annealing for at least 24 hours,
If the substrate processing time per sheet was 2 minutes, 15 annealing furnaces were required.
Since it can be shortened within the time, the number of annealing furnaces can be reduced to 1/6 or less. The improvement in productivity and the reduction in capital investment resulting from this result in a reduction in the substrate processing cost, which in turn leads to a reduction in the TFT price and thereby a new demand. As described above, the present invention is industrially useful and is suitable for patent.

[Brief description of drawings]

FIG. 1 shows a top view of a process of a reference example. (Crystallization and placement of TFT)

FIG. 2 is a sectional view of a process of a reference example. (Step of selectively crystallizing)

FIG. 3 shows a cross-sectional view of steps of a reference example. ( Reference example 1
reference)

FIG. 4 shows a cross-sectional view of steps of a reference example. ( Reference example 1
reference)

5A to 5C are sectional views showing steps of a reference example. ( Reference example 2
reference)

FIG. 6 shows a cross-sectional view of steps of a reference example. ( Reference example 3
reference)

FIG. 7 shows a cross-sectional view of a process of an example. (See Examples )

[Explanation of symbols]

1 ... Amorphous silicon 2 ... Island nickel film 3 ... Crystalline silicon 4 ... Grain boundary 5: Area where crystallization has not progressed 6 ... Semiconductor area 7: Gate wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/786 (72) Inventor Kenji Fukunaga 398 Hase, Atsugi, Kanagawa Semiconductor Energy Laboratory Co., Ltd. (72) Inventor Yasuhiko Takemura Kanagawa 398, Hase, Atsugi, Japan (56) References: Semiconductor Energy Laboratory Co., Ltd. (56) Reference JP-A-63-142807 (JP, A) JP-A-63-56912 (JP, A) JP-A-2-228043 (JP, A) JP-A-2-140915 (JP, A) JP-A-2-27320 (JP, A) JP-B-45-22173 (JP, B1) JP3186621 (JP, B2) Gang Liu and Stephen J. Fonash, Poly crystalline silicon thin film transistors on Corning 7059 glass substrates using short time ,, Appl. Phys. Let t. , USA, May 17, 1993, 62 (20), 2554-2556 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (5)

(57) [Claims] 1. A metal element that forms a semiconductor film made of amorphous silicon, forms a mask having an opening on the semiconductor film, and promotes crystallization of silicon on the mask and the semiconductor film in the opening. A film containing a metal element is formed in the opening of the mask by reacting silicon of the semiconductor film with the metal element to form a silicide of the metal element, the mask is removed, and oxidation is performed on the semiconductor film. Forming a protective film made of silicon or silicon nitride, heating the semiconductor film with the protective film left to crystallize, and after the crystallization, heating the semiconductor film in an atmosphere containing chlorine, A method for manufacturing a semiconductor device, which comprises reducing the concentration of the metal element in a semiconductor film. 2. A metal element for forming a semiconductor film made of amorphous silicon, forming a mask having an opening on the semiconductor film, and promoting crystallization of silicon on the mask and the semiconductor film in the opening. And forming a film containing, reacting silicon of the semiconductor film with the metal element in the opening of the mask to form a silicide of the metal element, removing the mask, and oxidizing the surface of the semiconductor film. Then, the semiconductor film whose surface is oxidized is heated to be crystallized, and after the crystallization, the semiconductor film is heated in an atmosphere containing chlorine to reduce the concentration of the metal element in the semiconductor film. A method for manufacturing a semiconductor device, comprising: 3. The metal element for promoting the crystallization of silicon is nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese,
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is made of copper, zinc, gold, or silver. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the atmosphere containing chlorine is an atmosphere using hydrogen chloride, methane chloride, ethane chloride, or ethylene chloride. 5. The concentration of the metal element in the semiconductor film after the concentration reduction is 1 atomic% or less.
5. The method for manufacturing a semiconductor device according to any one of items 4 to 4.