JPS5840820A - Formation of silicon single crystal film - Google Patents

Formation of silicon single crystal film

Info

Publication number
JPS5840820A
JPS5840820A JP13894381A JP13894381A JPS5840820A JP S5840820 A JPS5840820 A JP S5840820A JP 13894381 A JP13894381 A JP 13894381A JP 13894381 A JP13894381 A JP 13894381A JP S5840820 A JPS5840820 A JP S5840820A
Authority
JP
Japan
Prior art keywords
single crystal
silicon
films
film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13894381A
Other languages
Japanese (ja)
Inventor
Koji Egami
江上 浩二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13894381A priority Critical patent/JPS5840820A/en
Publication of JPS5840820A publication Critical patent/JPS5840820A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain uniform and high-quality single crystal films by a method wherein amorphous or polycrystalline Si films are firstly accumulated in insular shape on a substrate when Si single crystal films are formed on a single crystal insulating substrate and after providing a film of Au, Ag, Al, Pt or the like on the films, heating treatment is applied under inactive gas atmosphere or under vacuum. CONSTITUTION:A plurality of amorphous or polycrystalline films 2 are deposited in insular shape on a single crystal insulator substrate 1 of sapphire, spinel, silicon carbide or the like, and a metal film 3 of Au, Ag, Al, Pt or the like acting eutectic reaction with Si is covered on the whole surfaces including the substrate 1 and films 2. Next, heating treatment is applied under inactive gas atmosphere such as N2, HC or the like or under vacuum of 10<-3> Torr and the films 2 are changed to single crystal film 4. This permits single crystalization at low temperatures to decrease a defect reducing crystallization and high-quality single crystal films can be obtained.

Description

【発明の詳細な説明】 本発明は単結晶縁絶体基板上にシリコン単結晶膜を形成
する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a silicon single crystal film on a single crystal insulating substrate.

単結晶縁絶体基板上にシリコン単結晶膜を形成したシリ
コン半導体基板の実例として5O8(Silicon 
on 5apphire )基板が知られている。
5O8 (Silicon
on 5apphire) substrates are known.

以下、SO8を例にとり説明する。SO8は所望の温度
に加熱されたサファイア基板を含む成長炉にシラン(S
ll14)等の原料ガスを送り込み、その熱分解に」:
す、サファイア基板上にシリコン単結晶膜を形成したも
のである。
Hereinafter, SO8 will be explained as an example. SO8 is a growth furnace containing a sapphire substrate heated to a desired temperature.
ll14) and other raw material gases for thermal decomposition.
A silicon single crystal film is formed on a sapphire substrate.

しかし、このような成長法においては成長温度として9
50℃〜1000℃の範囲が用いられており、サファイ
ア基板とシリコン単結晶の格子定数及び熱膨張係数の違
いにより、得られるシリコン膜には多数の転位、面欠陥
、圧縮歪等が導入されてしまうことは公知である。これ
らの結晶性を低下させている欠陥はMOSデバイス製作
上、問題点の1つに数えられている。
However, in this growth method, the growth temperature is 9.
A temperature range of 50°C to 1000°C is used, and due to the difference in lattice constant and coefficient of thermal expansion between the sapphire substrate and the silicon single crystal, many dislocations, planar defects, compressive strain, etc. are introduced into the resulting silicon film. It is known to put it away. These defects that reduce crystallinity are considered one of the problems in manufacturing MOS devices.

一方では、このような問題点を改善する目的で成長俵に
結晶性を数夜させようとする試みがいくつかなされてい
るが、本発明の目的とするところは基本的な単結晶膜形
成法に関わるものである。
On the other hand, some attempts have been made to improve the crystallinity of the growth bales for several nights in order to improve these problems, but the purpose of the present invention is to improve the basic single-crystal film formation method. It is related to.

そこで、上記欠点を改善する目的で、本発明者は単結晶
絶縁体基板上に結晶欠陥の少ないシリコン単結晶膜をエ
ピタキシャル成長させる方法を見い出した。
Therefore, in order to improve the above drawbacks, the present inventors have discovered a method of epitaxially growing a silicon single crystal film with few crystal defects on a single crystal insulator substrate.

本発明は金属−シリコンが比較的低温度で共晶反応を起
こし、この反応によってシリコン単結晶が析出するとい
う現象を利用したものである。
The present invention utilizes the phenomenon that metal-silicon causes a eutectic reaction at a relatively low temperature, and a silicon single crystal is precipitated by this reaction.

従来より、この金属−シリコンの共晶反応を利用したエ
ピタキシャル成長法(J、E、Davey : App
l。
Conventionally, an epitaxial growth method utilizing this metal-silicon eutectic reaction (J.E., Davey: App.
l.

Phya、Lett、、28.365(1976))は
知られていたが、この場合、用いた基板はシリコン単結
晶であった。
Phya, Lett, 28.365 (1976)) was known, but in this case, the substrate used was a silicon single crystal.

本発明は基板として、シリコン単結晶では74、く単結
晶絶縁体を用いたところが全く異っている。
The present invention is completely different in that a single crystal insulator is used as the substrate, rather than a silicon single crystal.

従来のSO8形式においてはシランガスの熱分解により
サファイア基板上にシリコン単結晶を成長させていたが
、この場合成長温度を900tJ、下にして行うと、得
られるシリコンの膜質は劣化し、MOSデバイス製作に
向かないものであることは公知である。
In the conventional SO8 format, a silicon single crystal was grown on a sapphire substrate by thermal decomposition of silane gas, but in this case, if the growth temperature was lowered to 900 tJ, the quality of the resulting silicon film would deteriorate, making it difficult to manufacture MOS devices. It is well known that it is not suitable for

本発明は適当な金属により、金属−シリコンの共晶温度
が従来のSO8形成温度よりも低い組み合せを選び、低
温にもかかわらず、単結晶絶縁体基板上にシリコン1)
1結晶膜を形成し、残留歪が小さく、かつ結晶欠陥の少
ないシリコン単結晶膜を提供することを目的としたもの
である。
The present invention uses an appropriate metal to select a combination in which the metal-silicon eutectic temperature is lower than the conventional SO8 formation temperature, and forms silicon 1) on a single crystal insulator substrate despite the low temperature.
The purpose of the present invention is to form a silicon single crystal film, and to provide a silicon single crystal film with small residual strain and few crystal defects.

従来のS OS形式温度より低い共晶温度を持つ金属−
シリコンの組み合せが存在し【いることを金属−シリコ
ン固溶体の相図(Phase Diagrmn )から
容易に見い出すことが可能であるが、良好なシリコン単
結晶膜を得るためには共晶温度が低いということだけで
は本発明の目的は容易に達せられるものではない。金(
Au) 、銀(Ag)、アルミニウム(Al) +白金
(Pt) 等がシリコンと良好な中間層を形成し、共晶
反応を起こすこと(G、’0ttaviari、 et
 al。
A metal with a eutectic temperature lower than the conventional SOS formal temperature.
The existence of a combination of silicon can be easily found from the metal-silicon solid solution phase diagram, but in order to obtain a good silicon single crystal film, the eutectic temperature must be low. The object of the present invention cannot be easily achieved only by this method. Money(
Au), silver (Ag), aluminum (Al) + platinum (Pt), etc. form a good intermediate layer with silicon and cause a eutectic reaction (G, '0ttaviari, et
al.

:Phys、1lev、I、att、 、 44284
(1980))が示されているが本発明者を1金、銀、
アルミニウム、白金がシリコンど共晶反応を起こす場合
の共晶温度が、従来のSO8形成温度よりも低いことを
確認し、上記金属を本発明の特許請求の範囲で言う金属
として選択した。
:Phys, 1lev, I, att, , 44284
(1980)), but the present inventors are 1 gold, silver,
It was confirmed that the eutectic temperature when aluminum and platinum undergo a eutectic reaction with silicon is lower than the conventional SO8 formation temperature, and the above metals were selected as the metals referred to in the claims of the present invention.

また、特許55−84752によれば金属−シリコン共
晶反応を用いたシリコン単結晶膜形成法において良好な
結晶性を有するシリコン膜を得るためには析出核の制御
が重要であると述べられている。特許55−84752
は単結晶絶縁体基板上に先ずシリコンと共晶反応を起こ
す金属を島状に蒸着し後に、所望の成長温度でシリコン
を堆積させ、シリコン単結晶膜を得る形成法である。
Furthermore, according to Patent No. 55-84752, it is stated that control of precipitation nuclei is important in order to obtain a silicon film with good crystallinity in a silicon single crystal film formation method using a metal-silicon eutectic reaction. There is. Patent 55-84752
This is a formation method in which a metal that causes a eutectic reaction with silicon is first vapor-deposited in the form of islands on a single-crystal insulator substrate, and then silicon is deposited at a desired growth temperature to obtain a silicon single-crystal film.

本発明は単結晶絶縁体基板上に、先ず非晶質もしくは多
結晶シリコン膜を島状に、堆積し、次いでシリコンと共
晶反応を起こす金属を基板上に蒸着し、しかる後、所望
の温度で加熱処理を行う方法であり、特許55−847
52に比べ、シリコン午結晶形の形成において制御性が
優れ、かつ結晶性の良好なシリコン単結晶膜を提供でき
ることがわかった。単結晶絶縁体基板上に非晶質もしく
は多結晶シリコンを全面に堆積し、次いで共晶反応を起
こす金属を蒸着し、その後加熱処理を行っても、析出核
の制御がなされていないので、得られるシリコン膜は粒
径が増大するだけで膜質の劣ったものである。
The present invention first deposits an amorphous or polycrystalline silicon film in the form of islands on a single-crystal insulator substrate, then evaporates a metal that causes a eutectic reaction with silicon onto the substrate, and then heats it to a desired temperature. This is a method of heat treatment, and is disclosed in Patent No. 55-847.
It was found that the controllability in the formation of a silicon iris crystal shape was superior to that of No. 52, and a silicon single crystal film with good crystallinity could be provided. Even if amorphous or polycrystalline silicon is deposited on the entire surface of a single-crystal insulator substrate, a metal that causes a eutectic reaction is then vapor-deposited, and then a heat treatment is performed, the precipitation nuclei are not controlled, so there is no gain. The resulting silicon film only has an increased grain size and is of poor quality.

本発明者は単結晶絶縁体基板上にシリコンを島状に堆積
させ、金属−シリコンの共晶反応の結果生成される析出
核の制御を行うことにより、均一かつ良質なシリコン単
結晶膜を得ることが可能であることを見い出し、本発明
に到った。
The present inventor deposits silicon in the form of islands on a single-crystal insulator substrate and controls the precipitation nuclei generated as a result of the metal-silicon eutectic reaction, thereby obtaining a uniform and high-quality silicon single-crystal film. We have discovered that this is possible, and have arrived at the present invention.

以下実施例を示し、本発明の詳細を図面を用いて説明す
る。z躾:に用いる単結晶絶縁体基板としては、サファ
イア、スピネル、ベリリウムオキサイド、シリコンカー
バイト、シリコンナイトライド等があるが、ここでは(
lio2)面サファイア単結晶基板を例にとって説明す
る。
Hereinafter, the details of the present invention will be explained by showing examples and referring to the drawings. Examples of single-crystal insulator substrates used for
An explanation will be given by taking a sapphire single-crystal substrate having a 2) plane as an example.

第1図は(1ro2)面サファイア基板l上に非晶質も
しくはシリコン膜2を島状に堆積させた時の基板の断面
図の模式図である。(IToz)面サファイア基板の表
面は鏡面状に加工されていて、トリクロルエチレン、7
セトン、エチルアルコールを用いて脱脂洗浄を施し、さ
らに過酸化水素水、アンモニア水、純水からなる混液で
、その表面を洗浄化した。しかる後、市販のCV D 
(Chemical VaporDeposition
 )装置を用いて、非晶質もしくは多結晶シリコンを堆
積させ、従来のマスク技術を用いて島状に加工した。シ
リコン膜の堆積法については他の蒸着法でも可能で、本
発明はシリコン膜の堆積法においては何らの制約も受け
ない。
FIG. 1 is a schematic cross-sectional view of a (1ro2)-plane sapphire substrate l on which an amorphous or silicon film 2 is deposited in the form of an island. The surface of the (IToz)-plane sapphire substrate is mirror-finished, and the
Degreasing was performed using setone and ethyl alcohol, and the surface was further cleaned with a mixture of hydrogen peroxide, aqueous ammonia, and pure water. After that, commercially available CVD
(Chemical Vapor Deposition
) equipment to deposit amorphous or polycrystalline silicon and fabricate it into islands using conventional masking techniques. Other vapor deposition methods can be used for depositing the silicon film, and the present invention is not subject to any restrictions on the method of depositing the silicon film.

シリコン膜2は長方形のもので、その幅Wは5゜10 
、20 、50μmの4種類のものを選んだ。また、隣
り合うシリコン膜の間隔りはW=Lとした。
The silicon film 2 is rectangular, and its width W is 5°10
, 20 and 50 μm were selected. Further, the interval between adjacent silicon films was set to W=L.

第2図は第1図の平面図を模式的に表わした図である。FIG. 2 is a diagram schematically representing the plan view of FIG. 1.

第2図において、シリコン膜2の幅WはW/Wの値とし
て0.5,1.2の値を選んだ。なお、シリコン膜2の
膜厚tは0.4μmとした。
In FIG. 2, for the width W of the silicon film 2, values of 0.5 and 1.2 were selected as the value of W/W. Note that the thickness t of the silicon film 2 was 0.4 μm.

第3図は金属膜蒸着後の基板断面図を模式的に表わした
図である。シリコン膜2を有するサファイア基板1上に
シリコンと共晶反応を起こす金属膜3を市販の金属蒸着
装置を用い、圧力10〜10’l’orr 、室温にお
いて蒸着した。
FIG. 3 is a diagram schematically showing a cross-sectional view of the substrate after metal film deposition. A metal film 3 that causes a eutectic reaction with silicon was deposited on a sapphire substrate 1 having a silicon film 2 using a commercially available metal deposition apparatus at a pressure of 10 to 10'orr and at room temperature.

蒸着した金属膜3の膜厚dはその後の加熱処理及び用い
る金属種に依存し、シリコンと共晶反応を起こす組成比
を満足する量を蒸着する必要がある。次に、前記基板を
アルゴン(Ar)ガスの不活性雰囲気において、抵抗加
熱炉に挿入し、加熱処理を施した。
The thickness d of the deposited metal film 3 depends on the subsequent heat treatment and the metal species used, and it is necessary to deposit an amount that satisfies a composition ratio that causes a eutectic reaction with silicon. Next, the substrate was inserted into a resistance heating furnace in an inert atmosphere of argon (Ar) gas and subjected to heat treatment.

第4図に共晶反応により移行した金属膜を選択エッチし
て取り除いた基板の断面図を模式的に示した。
FIG. 4 schematically shows a cross-sectional view of a substrate from which the metal film transferred by the eutectic reaction was removed by selective etching.

本実施例によると、W=W=L=10μmとして金(A
LLす用い、金属膜厚を5ooA 、加熱処理温度とし
て共晶点温度とした場合、シリコン膜4を7マルスキー
干渉顕微鏡? S E M (Scmnning El
eetronMioroseope ) 、 T E 
M (Trarusmismion Electron
Microscope ) 、X 線回折を用いて調べ
たところ、単結晶シリコンであることが明らかとなった
According to this example, gold (A
LL, the metal film thickness is 5ooA, and the heat treatment temperature is the eutectic point temperature. S E M (Scmnning El
eetronMioroseope), T E
M (Trarusmision Electron
When examined using a microscope) and X-ray diffraction, it was revealed that it was single crystal silicon.

(1丁02)面サファイア基板1上に成長したシリコン
単結晶膜4の結晶学的方位は〈100〉で、従来のSO
8と同様に(1r02)面サファイア基板上に(100
)面シリコン単結晶が成長し【いることがわかった。
The crystallographic orientation of the silicon single crystal film 4 grown on the (1-02)-plane sapphire substrate 1 is <100>, which is similar to the conventional SO
Similarly to 8, (100
)-plane silicon single crystals were found to grow.

本実施例によると、Wが5.20.50μmの場合でも
良好な結晶性を有するシリコン単結晶膜が成長している
ことが、SEM、TEM、X線回折の結果から明らかと
なった。また、金属として、銀(AgLアルミニウム(
AAり、白金(PL)を用いてもシリコン単結晶膜が成
長していることが明らかとなった。
According to this example, it became clear from the results of SEM, TEM, and X-ray diffraction that a silicon single crystal film with good crystallinity was grown even when W was 5.20.50 μm. In addition, as a metal, silver (AgL aluminum (
It has become clear that a silicon single crystal film can be grown even when using AA or platinum (PL).

以上の説明では、用いた単結晶絶縁体基板として(1丁
02)面サファイア基板の例を示l−たが、(0001
)面サファイア基板を用いた場合には(10)面シリコ
ン単結晶膜が成長した。またスピネル基板を用いてもシ
リコン単結晶膜が成長した。
In the above explanation, an example of a (1-02) plane sapphire substrate was shown as the single-crystal insulator substrate used, but the (0001
When a )-plane sapphire substrate was used, a (10)-plane silicon single crystal film was grown. A silicon single crystal film was also grown using a spinel substrate.

本実施例においては、加熱処理法として抵抗加熱炉を用
いたが、他の高周波誘導加熱炉を用いても良く、また炉
内加熱に限らず、基板裏面からのレーザビームによる加
熱、及び赤外光加熱を用いても良く、本実施例と同様な
結果が得られた。
In this example, a resistance heating furnace was used as the heat treatment method, but other high frequency induction heating furnaces may be used. Optical heating may also be used, and results similar to those of this example were obtained.

加熱処理時の雰囲気としてアルゴン(Ar )以外の官
素(1%)tヘリウム(He)ガスを用いても同様な結
果が得られた。また、市販のロータリーポンプを用い、
 10 Torr程度の真空中において加熱処理を施し
ても同様な結果が得られた。
Similar results were obtained when a gas other than argon (Ar 2 ) and t-helium (1%) was used as the atmosphere during the heat treatment. In addition, using a commercially available rotary pump,
Similar results were obtained even when heat treatment was performed in a vacuum of about 10 Torr.

以上、述べたように、シリコンと共晶反応を起こす金属
を用いて、従来のSO8形成温度よりも低温で、単結晶
絶縁体基板上に結晶性を低下させている欠陥の少ない単
結晶シリコン膜を得る方法を示した。
As mentioned above, by using a metal that causes a eutectic reaction with silicon, a single-crystal silicon film with few defects that reduce crystallinity is formed on a single-crystal insulator substrate at a temperature lower than the conventional SO8 formation temperature. showed how to obtain

本発明はSO8を門OSデ)(イス製作に用いる場合、
必ずしも基板全面にシリコン膜が堆積している必要がな
いということを有効に活用したもので、共晶反応過程に
おいてシリコンを島状に堆積させることにより、析出核
を制御し、均一かつ良質な島状単結晶シリコン膜を形成
する新しい方法を提供するものである。
The present invention uses SO8 as gate OS de) (when using it for chair production,
This method takes advantage of the fact that the silicon film does not necessarily need to be deposited on the entire surface of the substrate. By depositing silicon in the form of islands during the eutectic reaction process, the precipitation nuclei are controlled and uniform, high-quality islands are formed. The present invention provides a new method for forming monocrystalline silicon films.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は(IrO2)面サファイア基板上にシリコン膜
を島状に堆積した様子を説明する断面の模式図。 第2図は(I TO2)面す7アイ゛ア基板上にシリコ
ン膜を島状に堆積した様子を説明する平面図の模式図。 第3図はサファイア基板上に金属膜を蒸着した様子を説
明する断面図の模式図。第4図はサファイア基板上に島
状に成長させた単結晶シリコン膜の断面を模式的に表わ
した図。 1・・・・・・(xro2)面サファイア基板2・・・
・・・島状シリコン膜 3・・・・・・蒸着金属膜 4・・・・・・島状単結晶シリコン膜
FIG. 1 is a schematic cross-sectional view illustrating how a silicon film is deposited in an island shape on an (IrO2) plane sapphire substrate. FIG. 2 is a schematic plan view illustrating how a silicon film is deposited in an island shape on a (ITO2) facing 7-iron substrate. FIG. 3 is a schematic cross-sectional view illustrating how a metal film is deposited on a sapphire substrate. FIG. 4 is a diagram schematically showing a cross section of a single crystal silicon film grown in an island shape on a sapphire substrate. 1... (xro2) plane sapphire substrate 2...
... Island-like silicon film 3 ... Vapor-deposited metal film 4 ... Island-like single crystal silicon film

Claims (1)

【特許請求の範囲】[Claims] 単結晶縁絶体基板上にシリコン単結晶膜を形成する方法
において、単結晶絶縁基板上面に、先ず、非晶質もしく
は多結晶シリコン膜を島状に堆積させ、次いで金、銀、
アルミニウム、白金のうち少なくとも1つからなる金属
膜を堆積させ、しかる後、不活性ガス雰囲気中、または
真空中で前記基板に加熱処理を施し、島状のシリコン単
結晶膜を形成することを特徴とするシリコン単結晶膜形
成法。
In a method of forming a silicon single crystal film on a single crystal insulating substrate, an amorphous or polycrystalline silicon film is first deposited in the form of islands on the top surface of a single crystal insulating substrate, and then gold, silver,
A metal film made of at least one of aluminum and platinum is deposited, and then the substrate is subjected to heat treatment in an inert gas atmosphere or in vacuum to form an island-shaped silicon single crystal film. Silicon single crystal film formation method.
JP13894381A 1981-09-03 1981-09-03 Formation of silicon single crystal film Pending JPS5840820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13894381A JPS5840820A (en) 1981-09-03 1981-09-03 Formation of silicon single crystal film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13894381A JPS5840820A (en) 1981-09-03 1981-09-03 Formation of silicon single crystal film

Publications (1)

Publication Number Publication Date
JPS5840820A true JPS5840820A (en) 1983-03-09

Family

ID=15233771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13894381A Pending JPS5840820A (en) 1981-09-03 1981-09-03 Formation of silicon single crystal film

Country Status (1)

Country Link
JP (1) JPS5840820A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745519A (en) * 1993-07-27 1995-02-14 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
US5888857A (en) * 1992-12-04 1999-03-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US6319761B1 (en) 1993-06-22 2001-11-20 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
US6323071B1 (en) 1992-12-04 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for forming a semiconductor device
US6479331B1 (en) 1993-06-30 2002-11-12 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device
US6713330B1 (en) 1993-06-22 2004-03-30 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
JP2006319361A (en) * 2006-07-19 2006-11-24 Semiconductor Energy Lab Co Ltd Method for manufacturing crystalline silicon film, and semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5888857A (en) * 1992-12-04 1999-03-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US6323071B1 (en) 1992-12-04 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for forming a semiconductor device
US6319761B1 (en) 1993-06-22 2001-11-20 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
US6713330B1 (en) 1993-06-22 2004-03-30 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
US6479331B1 (en) 1993-06-30 2002-11-12 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device
JPH0745519A (en) * 1993-07-27 1995-02-14 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
JP2006319361A (en) * 2006-07-19 2006-11-24 Semiconductor Energy Lab Co Ltd Method for manufacturing crystalline silicon film, and semiconductor device
JP4675294B2 (en) * 2006-07-19 2011-04-20 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device

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