JP2765893B2 - Loop control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for an information processing apparatus.

The present invention relates to a control unit of an information processing apparatus that executes a loop instruction for repeatedly executing the same instruction until a specified condition is detected.

〔Overview〕

According to the present invention, in a control means of a processing device for executing a looping instruction, instructions repeatedly executed in this loop are continuously executed until a condition for escape from the loop is detected. By starting the execution of the instruction, it is possible to prevent a hole from being generated during the execution cycle of the instruction and to suppress the performance degradation.

[Conventional technology]

The conventional apparatus repeatedly fetches and executes an instruction including a condition to be detected, an execution content, and an address of an instruction to be executed after detecting the condition until the condition is detected, and executes the instruction when the condition is detected. And the next instruction is fetched and executed. Figure 3 is an example of a pipeline operation of the conventional example, taken out of the instruction, it has become a pipeline structure of three stages of decoding and instruction execution, by to no cycle e ₁ e ₃ Cycle f ₁ to f ₃ The execution cycle in which the same instruction is repeatedly fetched, and the cycle e ₃
In perform extraction of the next instruction cycle f _N are discontinued cycles f _5, d ₄ if a match condition is detected, subsequently decoding and instruction execution are performed.

[Problems to be solved by the invention]

In such a conventional example, the same instruction is repeatedly fetched and executed until a condition that exits the loop is detected.
When the condition is detected, the next instruction is fetched and executed, so that the information processing device that performs control has a multi-stage pipeline configuration, and the cycle for detecting the condition and executing the instruction is performed in a multi-stage pipeline. In the lower stage (later stage), there is a disadvantage that a hole is formed between the execution cycle in which the condition is detected and the execution cycle of the next instruction, and the performance is reduced. This disadvantage becomes more pronounced as the execution cycle is in the lower pipeline. In the example of FIG. 3, there is a hole with two execution cycles.

An object of the present invention is to eliminate such a drawback and to provide a loop control device in which a hole is not generated in an execution cycle.

[Means for solving the problem]

The present invention provides an instruction executing means for executing an instruction in response to a clock, a first holding means for holding a decoded first instruction repeatedly executed by the instruction executing means, and a means for repeatedly executing the first instruction. Second holding means for holding a blocking condition to be blocked, detection means for detecting establishment of the blocking condition held by the second holding means, and execution by the instruction execution means after the detection means detects that the blocking condition is satisfied. And a third holding means for holding a decoded second instruction to be executed, wherein the execution of the first instruction is performed until the clock immediately before the clock at which the execution of the second instruction is started. It is characterized by having timing control means for continuing.

[Action]

The same instruction is repeatedly executed until a specified condition is detected, and when this condition is detected, the process exits the loop and moves to the next instruction. By the way, the present invention continuously executes the same instruction until immediately before the execution of the next instruction is started, prevents a hole between two instruction cycles from occurring, and prevents performance degradation.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment.

As shown in FIG. 1, this embodiment includes a first register 1 for holding a decoded instruction repeatedly executed until a condition is detected and a condition to be detected, and a next decoded instruction to be executed after the condition is detected. Second register 2 holding the instruction of
Condition detecting means 3 for detecting a held condition;
Instruction execution means 4 for executing the held instruction; a loop counter 5 for counting the number of loops;
And a timing control circuit 6 for extending the start of execution of the instruction stored in the memory. That is, in this embodiment, an instruction executing means 4 for executing an instruction in accordance with a clock, a first holding means for holding a decoded first instruction repeatedly executed by the instruction executing means 4, and a first instruction A first register 1 having a second holding means for holding a blocking condition for preventing the repetitive execution of the above, and a condition detecting means 3 as a detecting means for detecting establishment of the blocking condition held by the second holding means.
A second register 2 serving as a third holding unit for holding a decoded second instruction executed by the instruction execution unit after the detection unit detects the establishment of a blocking condition; and executing the second instruction. Control circuit 6 for continuing the execution of the first instruction until the clock immediately before the clock at which
And

Next, the operation of this embodiment will be described. When the same instruction is repeatedly executed until the loop counter 5 reaches the count value “0”, the condition that the condition of the count value “0” of the loop counter 5 from the first register 1 and the current count value of the loop counter 5 are detected. It is input to the means 3 and checks whether or not the conditions are matched, and outputs the result to the instruction execution means 4. Further, the instruction executing means 4 executes the decoded instruction given from the first register 1 when the matching result inputted from the condition detecting means 3 is not matched, and updates the loop counter 5 at the same time. Here, this update content is given by an instruction in the first register 1. Thus, the instruction execution means 4
Keeps executing the instruction in the first register 1 until the condition detecting means 3 detects that the condition is matched. Then, when the count value of the loop counter 5 becomes "0", the condition detecting means 3 detects that the condition has been matched, masks the execution of the instruction, and eliminates the operation. At the same time, the timing control circuit 6 detects a condition match from the condition detecting means 3 and loads the next decoded instruction in the second register 2 into the first register 1. When the instruction in the second register 2 is loaded into the first register 1, the next instruction held in the second register 2 is executed.

Figure 2 is an example of a pipeline operation in the present invention, instruction fetching, it has become a pipeline structure of three stages of decoding and instruction execution, the cycle e ₁₁ and e ₁₂ loops because the condition is mismatched and a run cycle is the cycle e ₁₃ is a cycle that NOP of detecting a match condition. Then, at the next timing, the execution cycle e _N of the next instruction is performed. The pipeline operation between the conventional example and this embodiment has a performance difference of two clocks.

〔The invention's effect〕

As described above, the present invention repeatedly executes the same instruction until a designated condition is detected to extend the start of execution of the next instruction, thereby executing the execution cycle in which the condition is detected and the execution cycle of the next instruction. Has the effect of being able to execute continuously.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a time chart showing the operation of the embodiment of the present invention. FIG. 3 is a time chart showing the operation of the conventional example. 1 ... first register, 2 ... second register, 3 ... condition detecting means, 4 ... instruction executing means, 5 ... loop counter, 6 ... timing control circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/38 G06F 9/32

Claims (1)

(57) [Claims] 1. An instruction executing means for executing an instruction according to a clock, a first holding means for holding a decoded first instruction repeatedly executed by the instruction executing means, and a repetitive execution of the first instruction Second holding means for holding a blocking condition for blocking, detecting means for detecting establishment of the blocking condition held by the second holding means, and detecting the satisfaction of the blocking condition by the detecting means. And a third holding means for holding a decoded second instruction to be executed, wherein the execution of the first instruction is executed until a clock immediately before a clock at which the execution of the second instruction is started. A loop control device comprising timing control means for continuing the control.