JPH05143321A - Performance adjusting circuit - Google Patents

Abstract

PURPOSE:To obtain a system capable of constituting a data processor performance adjusting mechanism constituted of an instruction issue control part and an arithmetic circuit part only by the addition of a few hardware. CONSTITUTION:This performance adjusting circuit is characterized by having a NOP instruction frequency specifying register 15 for specifying the number of NOP instructions to be issued so as to be inserted before a normal microinstruction, a counter register 16 for counting up a period specified by the contents of the register 15 from microprogram issue starting timing for soft instruction processing, a decrement circuit 17, and a microinstruction issue control circuit 14 for identifying the NOP instruction issuing period based upon the value of the register 16 and inserting a NOP instruction before the issue of a normal processing microinstruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a performance adjusting circuit based on microinstruction issue control.

[0002]

2. Description of the Related Art Conventionally, in this type of performance adjusting method, a number of NOP instructions are incorporated in a microprogram in advance, or an execution inhibiting signal is generated to hold all flip-flops and registers. The performance was adjusted accordingly.

[0003]

Among the above-mentioned conventional performance adjustment methods, in the former method of incorporating a NOP instruction in advance, it is necessary to rewrite a microprogram every time adjustment is made, and many performance adjustment methods are required for performance adjustment. There is a problem in that time is spent, and there is a drawback in that the number of microprogram steps is increased and the microprogram storage area is expanded to increase hardware.

Further, in the latter method in which the performance is adjusted by holding the registers by the execution inhibiting signal, all the registers and flip-flops have to have a holding function, which causes a problem that the amount of hardware becomes large. ..

[0005]

A performance adjusting circuit according to the present invention is a performance adjusting circuit in a data processing device which has a micro-instruction issue control corresponding to a soft instruction and has an operation unit controlled by the micro instruction. NO that specifies the number of times a no-operation command is issued
A P instruction number designating register, a counter that counts the period indicated by the NOP instruction number designating register from the processing start time for the soft instruction, and a counter value to determine the NOP instruction issuing period, A micro instruction issue control circuit for inserting and issuing a NOP instruction is also provided.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a data processing device including a performance adjusting circuit of the present invention.

In FIG. 1, a soft instruction fetch circuit 1
Reference numeral 0 is a circuit for fetching a soft instruction from the main memory or cache, and the fetched soft instruction 20 is stored in the soft instruction register 11 by the soft instruction interval display signal 24 sent from the micro instruction issue control circuit 14.
The soft instruction interval display signal 24 indicates that the execution of the soft instruction stored in the soft instruction register 11 is started from the next cycle by this signal, and indicates a break of the soft instruction.

The soft instruction 21 stored in the soft instruction register 11 is input to the micro instruction issue control circuit 14, whereby the micro instruction issue control circuit 14 fetches the micro program corresponding to the soft instruction 21.
When the counter register output 26 is zero, the microinstruction fetch control signal 22 instructs the microprogram storage memory 12 to instruct
From the microinstruction data 23. The fetched microinstruction 23 is supplied to the arithmetic pipeline 13 as a pipeline command 25 for operating the arithmetic pipeline 13 to control the operation.

The microinstruction issue control circuit 14 sequentially fetches microprograms necessary for processing the soft instruction 21 by the microinstruction fetch control signal 22 and repeats the operation of issuing as a pipeline command 25 until the final microprogram step is issued. , Final microprogram step to pipeline command 25
At the same time, the soft command interval display signal 25 is transmitted. As a result, the next soft instruction is stored in the soft instruction register 11, and the next soft instruction processing is performed.

No operation (hereinafter referred to as NOP)
The instruction number designation register 15 is a register for designating how many NOP instructions are inserted for one software instruction, and is set when the data processing device is initialized before the software instruction is executed. ..

The NOP instruction number 27, which is the output of the NOP instruction number specifying register 15, is fetched into the counter register 16 by the soft instruction interval display signal 24 sent from the micro instruction issue control circuit 14. The output 26 of the counter register is input to the micro instruction issue control circuit 14.

The microinstruction issue control circuit 14 determines whether the output 26 of the counter register is zero, and if it is not zero, the microprogram fetch of the soft instruction 21 is suppressed and the NOP instruction is issued to the pipeline command 25. If it is zero, as described above, the microprogram of the soft instruction 21 is fetched from the microprogram storage memory 12 and the pipeline command 25 is issued.

The counter register 16 is a decrement circuit that decrements the value of the counter register 16 except when the soft instruction interval display signal 24 sent by the micro instruction issue control circuit 14 is valid, that is, during execution of the micro program of the soft instruction 20. The output 28 of 17 is stored, and when the value becomes zero, the hold state is controlled.

At the timing when the soft command interval display signal 24 sent by the micro command issue control circuit 14 is valid, the next soft command is stored in the soft command register 11, and at the same time, the contents of the NOP command number designating register 15 are counted. It is stored in the register 16. If the NOP instruction count 27 is not zero at the execution timing of the soft instruction 21, the microinstruction issue control circuit 14 issues the NOP instruction as the pipeline command 25, and the counter register 16 is decremented during that time.

This operation is repeated until the output of the counter register 16 becomes zero, and when it becomes zero, the counter register 16 is held at zero until the next soft command issuance control display signal becomes valid. At this time, the microinstruction issue control circuit 14 issues the microprogram corresponding to the soft instruction 21 as the pipeline command 25 because the output 26 of the counter register is zero. This is repeated until the final microprogram step is issued.

At the same time when the final microprogram step is issued, the soft command interval display signal 24 becomes valid,
The same control is performed for the next soft instruction, and the NOP instruction is inserted for each soft instruction.

[0017]

As described above, the present invention has a NOP instruction number designation register, means for counting up to the designated number of times, and a NOP instruction to the arithmetic unit until the counting result reaches the designated number. By providing the micro-instruction issue control circuit for issuing, it is possible to easily adjust the execution performance of the soft instruction without rewriting the microprogram and without increasing the hardware of the arithmetic unit. Therefore, the system performance range of the data processing device can be easily expanded.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 10 soft instruction fetch circuit 11 soft instruction register 12 micro program storage memory 13 arithmetic pipeline 14 micro instruction issue control circuit 15 NOP instruction number designation register 16 counter register 17 decrement circuit 20 soft instruction 21 soft instruction 22 micro instruction fetch control signal 23 micro Instruction data 24 Display signal between software instructions 25 Pipeline command 26 Counter register output 27 NOP instruction count 28 Decrement circuit output

Claims (1)

[Claims] 1. A number of NOP instructions for designating the number of issuances of no-operation instructions in a performance adjustment circuit in a data processing device having a calculation unit for executing execution control of micro-instructions corresponding to a soft instruction and having an execution unit controlled by the micro instruction. A designated register, a counter that counts the period indicated by the NOP instruction number designated register from the start of processing of the software instruction, and a NOP instruction issuance period based on the counter value, and the NOP instruction is issued to the arithmetic unit. A performance adjustment circuit having a micro instruction issue control circuit for inserting and issuing an instruction.