JPH0540621A - Microprocessor - Google Patents

Abstract

PURPOSE:To easily and accurately secure the recovery time with a microprocessor independent of the type and the operating frequency of the microprocessor and the presence or absence of an instruction CACHE. CONSTITUTION:When a freeze instruction is carried out, the immediate value included in the freeze instruction and stored in an immediate value register 1 is transferred to a counter value register 3. Then, with the start of a count- down operation of a subtraction counter 6 with the immediate value as the initial value in an executing cycle of the freeze instruction, a O-deciding block 7 decides a fact that the value of the counter 6 is not equal to O any more and then outputs the freeze signals to the control blocks 8 and 9. Both blocks 8 and 9 freeze their operations and hold the internal operations. At the same time, the blocks 8 and 9 output the signals to inhibit the start of the new bus accesses. Therefore the recovery time is easily and accurately secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor capable of ensuring a recovery time easily and accurately.

[0002]

2. Description of the Related Art In a system using a microprocessor, when I / O access is continuously performed, it is necessary to secure a certain time called a recovery time between the accesses. JUMP
This is handled by inserting a required number of commands and the like, and when it is necessary to earn a certain amount of time for various reasons such as performance adjustment, the same means is used.

[0003]

In the system using the above-mentioned conventional microprocessor, a required number of NOP instructions, JUMP instructions, etc. are executed to secure a recovery time of a fixed time. The execution time of an instruction varies depending on the type of microprocessor, operating frequency, the presence or absence of the instruction CACHE, etc., and it is quite difficult to know exactly how much to execute, and the program must be changed when the system changes. There was a problem that it had to be.

The present invention has been made in view of the above problems, and provides a microprocessor that can easily and accurately secure a recovery time without depending on the type, operating frequency, presence or absence of a command CACHE, and the like. With the goal.

[0005]

In order to achieve the above object, the microprocessor of the present invention operates by interpreting and executing an instruction given from the outside, and instructs the freeze of the operation for a designated time. A freeze instruction, an immediate value register that stores the immediate value included in the freeze instruction, a timer that operates with a basic clock given from the outside, a timer value register that stores the value given to the timer, and a fixed time interval from the timer. Of the subtraction counter that operates when the freeze instruction is issued using the signal given to the clock as a clock, a counter value register that stores the value read in the immediate value register as a count value to be given to the subtraction counter, and the subtraction counter A 0 decision block for determining whether the value is 0,
While the 0 determination block determines that it is not 0, it has a control block that holds the internal operation and prohibits bus access.

[0006]

When the freeze instruction is executed, the immediate value in the freeze instruction stored in the immediate value register is transferred to the counter value register. Then, in the execution cycle of the freeze instruction, the countdown of the subtraction counter with the immediate value as the initial value starts, and the 0 determination block determines that the value of the subtraction counter is not 0 and outputs the freeze signal to the control block. .. The control block which received the signal freezes the operation, puts the internal operation in the hold state, and outputs a signal for inhibiting the start of the new bus access.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention. In the figure, 1 is an immediate register that stores an immediate value included in an instruction, 2 is a timer register that stores a value to be set in a timer, 3 is a count value register that stores the count value stored in the immediate register 1, and 4 is The subtraction counter 5 which performs subtraction with the basic clock determines whether the value of the subtraction counter 4 is 0, and when it is determined to be 0, initializes the subtraction counter 4 (sets the contents of the timer value register 2 to the counter). , A subtraction counter 6 performs subtraction using the 0 determination signal issued from the 0 determination block 5 at a fixed time as a clock when a freeze instruction is issued, and 7 indicates whether the value of the subtraction counter 6 is 0. A 0 decision block for determining whether or not 0 is a block for controlling pipeline execution of this microprocessor. It has a function to perform normal control while receiving a signal indicating that the signal is “0”, and freeze the pipeline until it becomes 0 when a signal indicating that it is not 0, and temporarily hold the internal operation of the microprocessor. A pipeline control block 9 is a block for performing bus access control of the present microprocessor, and is a bus access control block having a function of inhibiting the start of a new bus access by a bus access freeze signal from the pipeline control block 8. is there.

FIG. 2 is a flow chart showing the flow of instructions in this embodiment. Instruction 1 is an IN instruction for address A0F0, and instruction 2 is a freeze instruction which is a feature of the present invention and specifies a freeze of 3 msec. Further, the instruction 3 is an OUT instruction for outputting the data DD to the address A0F2. FIG. 3 is a timing chart showing a pipeline operation, a bus access signal, and a pipeline freeze signal in this embodiment. Pipeline operations are f (instruction fetch), d (instruction decoder), A
The state of the 5-stage pipeline of (address calculation), B (bus access), and E (instruction execution) is shown.

Next, the operation of this embodiment will be described.
As shown in FIG. 3, the operating frequency of this microprocessor is 2 MHz, and a basic clock with a cycle of 500 nsec is given. First, when the system using this microprocessor starts up, the internal timer is set to 1 m.
The timer value register 2, the subtraction counter 4, and the 0 decision block 5 are initialized for setting as a sec timer. That is, "2" (500 nsec x 2 = 1 msec) may be set as the timer value in order to configure the 1 msec timer using the 500 nsec basic clock. Therefore, the timer is passed via the immediate value register 1 by the immediate value transfer instruction. The value "2" is set in the value register 2.
As a result, from the 0 determination block 5, 2 of the basic clock
A signal is output every cycle, that is, every 1 msec, and the subtraction counter 6 can perform an operation of counting down every 1 msec. Further, the counter value register 3 and the 0 determination block 5 are initialized so as to be “0”, and wait for a freeze instruction.

Next, the operation after the system starts up will be described. At some point, instruction 1, instruction 2,
It is assumed that the instruction 3 is instructed to be executed. This is because when I / O commands are issued continuously, it is based on the specification that a recovery timer is provided with a period of 3 msec or more.
The instruction 2 which sets the bus access prohibition time of 3 msec is inserted between the instruction 3 and the instruction 3.

As shown in FIG. 3, first, in order to execute the instruction 1 (IN instruction), the processing of f1-d1-a1 and the pipeline is advanced, and the bus access, that is, I / I is performed in the B1 cycle.
Execute O read. Then, the obtained data is set in the storage location designated in the e1 cycle.

Instruction 2 subsequently instructed (freeze instruction)
F2-d2-a2-B2 (however,
Since the instruction 2 does not access the bus, the B2 cycle advances to no-operation), but the immediate value "3" in the instruction 2 stored in the immediate value register 1 is transferred to the counter value register 3 in the a2 cycle. .. Then, in the e2 cycle, that is, in the execution cycle of the freeze instruction, the countdown of the subtraction counter 6 with "3" as the initial value starts, and the 0 determination block 7 determines that the value of the subtraction counter 6 is not 0, The pipeline freeze signal is output to the pipeline control block 8.

The pipeline control block 8 receiving the signal freezes the pipeline operation, puts the internal operation in a hold state, and prohibits the bus access control block 9 from starting a new bus access. Output a signal. The subtraction counter 6 is 1 msec
Since it is decremented every time, the time until the initial value "3" of the subtraction counter 6 becomes "0" is 3 msec, during which the pipeline operation is frozen.

The instruction 3 (OUT
The B3 cycle is attempted to be executed immediately after advancing the processing with f3-d3-a3 for execution of (instruction), but at that time, the e2 cycle has already started, the pipeline is frozen, and the start of bus access is prohibited. B3 cycle, that is, I / O write operation (OUT)
Execution is suspended. When the pipeline freeze is released after 3 msec, the bus access for the B3 cycle is started for the first time.

That is, the IN instruction of instruction 1 and the O instruction of instruction 3
This means that the interval between UT commands is opened for 3 msec or more, and the recovery time specified can be secured. Moreover, since the execution cycle (e2 cycle) of the freeze instruction itself spends the specified time, the time interval can be set with high accuracy not only when adjusting the time for bus access but also when a certain amount of time is required for performance adjustment. It can be secured, and there is no difference depending on the presence or absence of the instruction CACHE. Furthermore, if microprocessors with different operating frequencies are used, the value of the timer value to be changed at the time of rising is changed and the 0 decision block 5
If you adjust the output from 1msec,
The program shown in can be used as it is without any modification.

[0016]

As described above, the microprocessor of the present invention is provided with the instruction and the function for freezing the pipeline so that the program is changed without depending on the presence or absence of the instruction CACHE and the operating frequency. The recovery time can be secured easily and accurately without any need.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the flow of instructions in this embodiment.

FIG. 3 is a timing chart showing a pipeline operation, a bus access signal, and a pipeline freeze signal in this embodiment.

[Explanation of symbols]

 1 ... Immediate value register 2 ... Timer value register 3 ... Counter value register 4 ... Subtraction counter 5 ... 0 decision block 6 ... Subtraction counter 7 ... 0 decision block 8 ... Pipeline control block 9 ... Bus access control block

Claims (1)

[Claims] 1. A microprocessor that operates by interpreting and executing an instruction given from the outside, and a freeze instruction for instructing freeze of the operation for a specified time, and an immediate value register for storing an immediate value included in the freeze instruction. , A timer which operates by a basic clock given from the outside, a timer value register which stores a value given to the timer, and which operates when the freeze instruction is issued using a signal given from the timer at constant intervals as a clock A subtraction counter, a counter value register that stores the value read in the immediate value register as a count value to be given to the subtraction counter, a 0 determination block that determines whether the value of the subtraction counter is 0, and a 0 determination block While judging that it is not 0, the internal operation is held and the bus access is A microprocessor having a control block for inhibiting a memory.