AU617904B2 - Information processing system operable without useless time - Google Patents

Description

4*44 4i 4 4 4 4a 4 C 4e i 4 4 S F Ref: 115571 FORM COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 6 1 7 9 0 4 COMPLETE SPECIFICATION

(ORIGINAL)

FOR OFFICE USE: Class Int Class Complete Specification Lodged: Accepted: Published: Priority: Related Art: Name and Address of Applicant: Address for Service: NEC Corporation 33-1, Shiba Minato-ku Tokyo

JAPAN

Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia Complete Specification for the invention entitled: Information Processing System Operable Without Useless Time The following statement is a full description of this invention, including the best method of performing it known to me/us t 4 4 4 4 5845/6 -L j 1-- I L 1' 1 Abstract of the Disclosure: When an instruction executing unit executes, as a current instruction, a particular instruction which should be repeatedly executed a predetermined number of times by the instruction executing unit until a terminating condition is satisfied, a timing control circuit stops production of clock pulses to make a register continuously hold the current instruction. The register is herein called an IE register and supplies 0000 the current-instruction to the instruction executing 00oo o 0 0 a 10 unit to make the instruction executing unit execute the Sa current instruction. When a loop counter counts up the 4 predetermined number, a comparing circuit produces a condition satisfaction signal. Responsive to the condition satisfaction signal, the timing control j 15 circuit restarts production of the clock pulses to make the IE register hold a next subsequent instruction which next follows the particular instruction.

6 aa 00 000 r INFORMATION PROCESSING SYSTEM OPERABLE WITHOUT USELESS TIME 41;; 11 1 4, 1 1 44 I 1 4

III;

14444 4144 t 1 I 4 4 1 4114441 41 1 1 4 Background of the Invention: ThiS invention relates to an information processing system and, in particular, to an information processing system operable under pipeline control.

5 An information processing system usually includes an instruction processing unit. Among others, the instruction processing unit processes, as a current instruction, each of program instructions which are fetched successively from a memory device. The current 10 instruction is executed by an instruction executing unit.

The instruction processing unit may be operable under three-stage pipeline control in the manner which will later be described. The three-stages of the pipeline control are an instruction fetch (IF) stage, a decode stage, and an instruction execution (IE) stage. In the instruction fetch stage, each of the program instruction fetched from the memory device is liiii.i iii-I~_.

held in an IF register as a fetched instruction. In the decode stage, the fetched instruction is held in a D register as a decoded instruction. In the instruction execution stage, the decoded instruction is held in an IE register as the current instruction which is executed by the instruction executing unit.

The program instructions include a loop and a next subsequent instruction. The loop comprises a particular instruction which should be repeatedly executed a predetermined number of times by the instruction executing unit until a terminating condition 0 is satisfied. The next subsequent instruction is an S instruction which should be executed by the instruction executing unit after the terminating condition is faa.

satisfied.

It will now be assumed that the information processing system carries out the program instructions which include the loop and the next subsequent instruction. In this event, a conventional instruction ,20 processing unit repeatedly fetches and decodes the particular instruction. The instruction executing unit repeatedly executes the particular instruction the a4 i predetermined number of times until the terminating condition is satisfied. After the terminating condition is satisfied, execution of the particular instruction is not carried out. Simultaneously, the next subsequent instruction is fetched and decoded by the conventional instruction processing unit and executed by the 3 instruction executing unit. Accordingly, the instruction executing unit carries out no instruction while the next subsequent instruction is fetched and decoded, namely, during two machine cycles. Such a duration until which the instruction executing unit carries out no instruction is called a "no execution" duration. The "no execution" duration becomes longer when the pipeline control is implemented by a lot of stages. As a result, it takes useless time.

Summary of the Invention: It is an object of this invention to provide an 4414 information processing system operable without useless time.

It is another object of this invention to 44Ir fill 15 provide an information processing system of the type described, which is operable without a "no execution" duration.

Other objects of this invention will become clear as the description proceeds.

20 On describing the gist of this invention, it is 4 44 possible to understand that an information processing system comprises an instruction processing unit for processing, as a current instruction, each of program 44444' 1 instructions fetched successively from a memory device and an instruction executing unit for executing the current instruction. The program instructions include a loop and a next subsequent instruction. The loop comprises a particular instruction which should be 4 repeatedly executed a predetermined number of times by the instruction executing unit until a terminating condition is satisfied. The next subsequent instruction is an instruction which should be executed by the instruction executing unit after the terminating condition is satisfied.

According to this invention, the instruction processing unit of the above-understood information processing system comprises: next instruction holding means for holding, as a first held instruction, a next following instruction which next follows the 0 04 A current instruction; current instruction holding o o means connected to the instruction executing unit for 0 0 0 holding the current instruction as a second held oo,0 o 15 instruction, the current instruction holding means 0 o0 supplying the second held instruction to the instruction executing unit to make the instruction executing unit o°O execute the second held instruction; transferring means between the current and the next instruction 0 o 20 holding means for transferring the first held C0 0 instruction from the next instruction holding means to the current instruction holding means as the current instruction; loop judging means connected to the 1a 0 next instruction holding means for judging whether or not the current instruction is the particular instruction, the loop judging means producing a loop detection signal when the current instruction is the particular instruction; suspending means connected 1..

li- i to the loop judging means and the transferring means for suspending transfer of the second held instruction from the next instruction holding means to the current instruction holding means in response to the loop detection signal; condition judging means for judging whether or not the terminating condition is satisfied, the condition judging means producing a condition satisfaction signal when the terminating condition is satisfied; and releasing means connected to the condition judging means for releasing the suspending means in response to the condition satisfaction signal to make the transferring means restart the transfer.

Brief Description of the Drawing: 15 Fig. 1 is a block diagram of an information processing system according to a preferred embodiment of the instant invention; Fig. 2 is a time chart for use in describing operation in the information processing system shown in Fig. 1; and Fig. 3 is another time chart for use in describing operation in a conventional information a processing system.

4 4 A Description of the Preferred Embodiment: Referring to Fig. 1, an information processing system according to a preferred embodiment of this invention includes an instruction processing unit The instruction processing unit 10 accesses a main i i memory unit 20 to successively fetch program instructions as fetched instructions. The instruction processing unit 10 processes each of the fetched instructions as a current instruction. The information processing system further comprises an instruction executing unit 30 for executing the current instruction.

The instruction processing unit 10 is operable under three-stage pipeline control in the manner which will later be described. The three stages of the pipeline control are an instruction fetch (IF) stage, a decode stage, and an instruction execution (IE) o S0 stage.

0 0 0 e a 0 The instruction processing unit 10 comprises 0 0 first through third instruction registers 11, 12, and 0400 15 13. The first through the third instruction registers 11 to 13 correspond to IF, D, and IE stages described heretobefore. Therefore, the first through the third o 0 Q instruction registers 11 to'13 will hereafter be called 04 0 o00 IF, D, and IE registers.

So 20 The IF register 11 is connected to the main memory 20. The IF register 11 holds, as a fetched instruction, each of the program instructions that is fetched from the main memory 20. The fetched instruction is supplied to the D register 12. The D register 11 holds the fetched instruction as a decoded instruction. The decoded instruction is supplied to the IE register 13 through a transfer line 14. The IE register 13 holds the decoded instruction as the current 7 instruction. The current instruction is supplied to the instruction executing unit In this manner, the D register 12 serves as a next instruction holding arrangement for holding, as a first held instruction, a next following instruction which nex' follows the current instruction. The IE register 13 acts as a current instruction holding arrangement for holding the current instruction as a second held instruction and for supplying the second held instruction to the instruction executing unit 30 to make the instruction executing unit 30 execute the second held'instruction. The transfer line 14 is o os operable as a transferring arrangement between the o0 current and the next instruction holding arrangements 15 for transferring the first held instruction from the oonext instruction holding arrangement to the current next instruction holding arrangement to the current instruction holding arrangement as the current o 00 instruction. o 00 n :The program instructions may or may not include a loop and a next subsequent instruction. The loop comprises a particular instructio v4h should be co 00 0 1 repeatedly executed a predetermin aumber of times by S the instruction executing unit 3. Lil a terminating o condition is satisfied. The next subsequent instruction is an instruction which should be executed by the instruction executing unit 30 after the terminating condition is satisfied.

L- ~i I r -L W- -I ;i i 8 The D register 12 is connected to a loop judging circuit 15. The loop judging circuit 15 is for judging whether or not the current instruction is the particular instruction.

It will now be assumed that the IE register 13 holds, as the current instruction, the particular instruction together with the predetermined number which represents the terminating condition. In other words, the IE register 13 serves also as a number holding arrangement for holding the predetermined number as a held number HN. In this event, the loop judging circuit 15 produces-a loop detection signal LD. The loop 0o 44 detection signal LD is supplied to a timing control ro o 0ro circuit 16. The IE register 13 supplies the particular 4004 15 instruction to the instruction executing unit Simultaneously, the IE register 13 supplies the held number HN to a comparing circuit 17.

EIn the manner which will later become clear, the 0 IE register 13 continuously holds the particular instruction and the predetermined number during a plurality of machine cycles which are equal in number to the predetermined number. The instruction executing 0 unit 30 repeatedly executes the particular instruction SI 004 4&1 the predetermined number of timi3s.

During execution of the particular instruction, the instruction executing unit 30 supplies a count indication signal CI to a loop counter 18. The loop counter 18 counts up a count in successive machine t I i i i i~ CII .9 cycles during reception of the count indication signal CI. The loop counter 18 produces a counted number CN indicated by the count. At any rate, the loop counter 18 acts as a counting arrangement for counting a repeat count of execution of the particular instruction to produce the counted number CN. The counted number CN is supplied to the comparing circuit 17.

The comparing circuit 17 compares the counted number CN with the held number HN. When the counted number CN becomes equal to the held number HN, the terminating condition is satisfied. The comparing circuit 17 produces a condition satisfaction signal CS 04 .0 00 0 Swhen the terminating condition is satisfied. That is to 0 0 o say, the comparing circuit 17 serves in cooperation with 15 the IE register 13 and the loop counter 18 as a condition judging arrangement for judging whether or not the terminating condition is satisfied. The condition oo ~satisfaction signal CS is supplied to the timing control circuit 16 and the instruction executing unit 0 o 20 Responsive to the condition satisfaction signal CS, the instruction executing unit 30 stops execution during one machine cycle.

"0 The timing control circuit 16 is supplied with an original clock sequence OC from a clock oscillator (not shown). The original clock sequence OC comprises clock pulses which appear at a clock interval equal to one machine cycle. The timing control circuit 16 modifies the original clock sequence OC into a modified clock sequence MC in response to the loop detection signal LD and the condition satisfaction signal CS. The modified clock sequence MC is supplied to the main memory unit 20, the IF register 11, the D register 12, and the IE register 13. The timing control circuit 16 supplies the original clock sequence OC as the modified clock seqrence MC to the main memory unit 20 and the IF, the D, and the IE registers 11, 12, and 13 as long as the timing control circuit 16 does not receive the loop detection signal LD. Each of the program instructions is transferred from the main memory unit 20 successively oe gea to the IF register 11, the D register 12, and the IE go 64 register 13 in synchronism with the clock pulses of the 04. 0~ 0 o04 modified clock sequence MC.

15 Responsive to the loop detection signal LD, the timing control circuit 16 produces the modified clock sequence MC with production of the clock pulses being o 0 stopped. In this event, the IF, the D, and the IE 0 00 registers 11 to '3 continuously hold their contents 020 during at least two machine cycles. That is, the timing S control circuit 16 is operable as a suspending 0 0 arrangement for suspending transfer of the decoded instruction from the D register 12 to the IE register 13 in response to the loop detection signal LD. It should be understood in this connection that the suspending arrangement is connected through the D register 12 to the transfer line 14, namely, to the transferring arrangement in effect.

satisfaction signal when said terminating condition is satisfied; and releasing means connected to said condition /3 11 Responsive to the condition satisfaction signal CS, the timing control circuit 16 produces the original clock sequence OC as the modified clock sequence MC to make the IE register 13 hold the decoded instruction as the current instruction. Accordingly, the timing control circuit 16 acts as a releasing arrangement for releasing the suspending arrangement in response to the condition satisfaction signal CS to restart the transfer. In the manner in which the suspending arrangement is connected to the transfer arrangement, the releasing arrangement is connected to the transfer .444 rtr arrangement'in effect. At any rate, the modified clock sequence MC is equal to the original clock sequence OC (O except that production of the clock pulses stops during a time interval between the loop detection signal LD and the condition satisfaction signal CS.

Referring to Fig. 2, operation of the instruction processing unit 10 will be described.

Attention will be directed to the loop (LP) and the next subsequent instruction It will be assumed that the loop comprises the particular instruction and that the predetermined number is equal to two. Zeroth 44 4Q through fifth machine cycles are indicated by numerals 0 through 5 along a first or top line in Fig. 2. The original and the modified clock sequences OC and MC are depicted along second and third lines from the top in Fig. 2, respectively.

12 In the zeroth machine cycle indicated by 0, the loop is set into the IF register 11 from the main memory unit 20 in the manner depicted along a fourth line from the top in Fig. 2.

In the first machine cycle 1, the loop is set into the D register 12 from the IF register 11 in the manner depicted along a fifth line from the top in Fig.

2. At the same time, the next subsequent instruction is set into the IF register 11 from the main memory unit in the manner depicted along the fourth line in Fig. 2.

In the first machine cycle 1, the loop is supplied to 0 the loop judging circuit 15 from the D register 12.

In the second machine cycle 2, the loop is set moo into the IE register 13 from the D register 12 in the IS manner depicted along a sixth line from the top in Fig.

2. At the same time, the next subsequent instruction is set into the D register 12 from the IF register 11 in I 1 the manner depicted along the fifth line in Fig. 2. In the second machine cycle 2, the IE register 13 supplies o 20 the particular instruction and the held number to the instruction executing unit 30 and the comparing circuit 17, respectively. The loop judging circuit 15 supplies 0 a the loop detection signal LD to the timing control circuit 16. Responsive to the loop detection signal LD, the timing control circuit 16 stops production of the clock pulses of the modified clock sequence MC. The instruction executing unit 30 supplies the count indication signal CI to the loop counter 18.

5845/6 13 o00 0000 00 00 0 P a o 000 00 0 a 0 00 0 0 0 0000 0000 0 0~ 0 00 0 0 a 0 0 0 01 0 0) 0 0 000 00 0 0 In the third and fourth machine cycles 3 and 4, the IE register 13 and the D register 12 continuously hold the loop and the next subsequent instruction. In the fourth machine cycle 4, the loop counter 18 produces the counted number of two. Therefore, the comparing circuit 17 supplies the condition satisfaction signal CS to the timing control circuit 16.

In the fifth machine cycle 5, the timing control circuit 16 produces the original clock sequence OC as the modified clock sequence MC after reception of the condition satisfaction signal CS. Therefore, the next subsequent instruction is set in the IE register 13 from the D register 12 in the manner depicted along the sixth line in Fig. 2. The IE register 13 supplies the next 15 subsequent instruction to the instruction executing unit to make the instruction executing unit 3C0 execute the next subsequent instruction.

Turning to Fig, 3, operation of a conventional processing unit will be described for comparison with 20 the operation described in connection with Fig. 2.

Attention will be directed to the loop (LP) and the next subsequent instruction (NS).

In the zeroth through the fourth machine cycles 0 to 4, the loop is repeatedly fetched, decoded, and executed. In the fourth machine cycle 4, the terminating condition is satisfied.

The next subsequent instruction is fetched, decoded, and executed in the fifth, the sixth, and the F. 14 seventh machine cycles 5 to 7, respectively. It is now clearly understood in conjunction with Fig. 3 that the instruction executing unit carries out no instruction during a "no execution" duration equal to two machine cycles (2T).

While this invention has thus far been described in conjunction with only one preferred embodiment thereof, it will now readily be possible for those skilled in the art to develop various other embodiments of this invention. For example, the loop counter may hold the predetermined number as an initial number when a e t the instruction executing unit executes a particular instruction of a loop. In this event, the loop counter counts down a count in each machine cycle and a 6 15 comparing circuit produces a condition satisfaction *4 a signal when the count becomes zero.

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Claims (2)

1. In an information processing system comprising an instruction processing unit for processing, as a current instruction, each of program instructions fetched successively from a memory device and an instruction executing unit for executing said current instruction, said program instructions including a loop and a next subsequent instruction, said loop comprising a particular instruction which should be repeatedly executed a predetermined number of times by 10 said instruction executing unit until a terminating condition is satisfied, said next subsequent instruction A being an instruction which should be executed by said instruction executing unit after said terminating condition is satisfied, the improvement wherein said instruction processing unit comprises: next instruction holding means for holding, as a first held instruction, a next following instruction which next follows said current instruction; current instruction holding means connected to said instruction executing unit for holding said current a i instruction as a second held instruction, said current instruction holding means supplying said second held instruction to said instruction executing unit to make said instruction executing unit execute said second held instruction; _A loop and a next subsequent instruction. The loop comprises a particular instruction which should be 16 (Claim 1 continued) transferring means between said current and said next instruction holding means for transferring said first held instruction from said next instruction holding means to said current instruction holding means as said current instruction; loop judging means connected to said next instruction holding means for judging whether or not said current instruction is said particular instruction, said loop judging means producing a loop detection signal when said current instruction is said particular instruction; suspending means connected to said loop judging means and said transferring means for suspending transfer of said second held instruction from said next instruction holding means to said current instruction holding means in response to said loop detection signal; condition judging means for judging whether or A not said terminating condition is satisfied, said condition judging means producing a condition a G 45 satisfaction signal when said terminating condition is satisfied; and releasing means connected to said condition judging means for releasing said suspending means in response to said condition satisfaction signal to make said transferring means restart said transfer. detection signal when the current instruction is the particular instruction; suspending means connected 17

2. An information processing system as claimed in Claim 1, said instruction executing unit producing a count indication signal during execution of said particular instruction, wherein said condition judging means comprises: number holding means connected to said next instruction holding means for holding said predetermined number as a held number when said eurrent instruction holding means holds said particular instruction as said current instruction; counting means connected to said instruction n executing unit for counting a repeat count of said a execution of the particular instruction during reception of said count indication signal, said counting means 15 producing a counted number indicated by said repeat count; and comparing means connected to said number holding means and to said counting means for comparing said counted number with said held number, said comparing means producing said condition satisfaction signal when said counted number is equal to said held number. o :DATED this TWELFTH day of DECEMBER 1989 1 ~NEC Corporation Patent Attorneys for the Applicant SPRUSON FERGUSON IJ