JP2696103B2 - Manufacturing method of semiconductor nonvolatile memory - Google Patents
Manufacturing method of semiconductor nonvolatile memoryInfo
- Publication number
- JP2696103B2 JP2696103B2 JP63138728A JP13872888A JP2696103B2 JP 2696103 B2 JP2696103 B2 JP 2696103B2 JP 63138728 A JP63138728 A JP 63138728A JP 13872888 A JP13872888 A JP 13872888A JP 2696103 B2 JP2696103 B2 JP 2696103B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- film
- silicon nitride
- gate electrode
- tunnel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 title claims description 18
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 46
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ICカードなどの記憶用デバイスとして用
いられている半導体不揮発性メモリの製造方法に関す
る。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor nonvolatile memory used as a storage device such as an IC card.
この発明は、電気的消去可能な浮遊ゲート型半導体不
揮発性メモリにおいて、トンネル絶縁膜を酸化チッ化膜
を用いることにより、書換え回数の向上をはかったもの
である。The present invention is intended to improve the number of times of rewriting in an electrically erasable floating gate type semiconductor nonvolatile memory by using a nitride oxide film as a tunnel insulating film.
〔従来の技術〕 従来、第２図に示すように、プログラム端子であるト
ンネルドレイン領域２の上に約100Åのシリコン熱酸化
膜から成るトンネル酸化膜16を設けた電気的書換え可能
な浮遊ゲート型半導体不揮発性メモリが知られていた。
例えば、W.S.Johnson et al “16−K EEPROM relies on
tunneling for byte−erasable program storage"Elec
tronics/February 28（1980）pp113に開示されている。2. Description of the Related Art Conventionally, as shown in FIG. 2, an electrically rewritable floating gate type in which a tunnel oxide film 16 made of a silicon thermal oxide film of about 100 ° is provided on a tunnel drain region 2 which is a program terminal. Semiconductor non-volatile memories have been known.
For example, WS Johnson et al “16-K EEPROM relies on
tunneling for byte-erasable program storage "Elec
tronics / February 28 (1980) pp113.
しかし、従来の半導体不揮発性メモリは、トンネル絶
縁膜として約100Å程度の熱酸化膜が用いられているた
めに、トンネルドレイン領域２と浮遊ゲート電極７との
間で、電荷のやりとり（即ち、プログラム動作）をする
と、トンネル酸化膜16が強電界ストレスにより偶発的に
破壊しやすいという欠点が有していた、 そこで、この発明は、従来のこのような欠点を解決す
るために、プログラム動作により偶発破壊しない電気的
書換え可能な半導体不揮発性メモリを得ることを目的と
している。However, in the conventional semiconductor non-volatile memory, since a thermal oxide film of about 100 ° is used as a tunnel insulating film, charges are transferred between the tunnel drain region 2 and the floating gate electrode 7 (that is, a program is performed). Operation), the tunnel oxide film 16 has a disadvantage that it is easily broken accidentally due to a strong electric field stress. Therefore, the present invention solves such a disadvantage in the prior art by using a program operation. An object of the present invention is to obtain an electrically rewritable semiconductor non-volatile memory that is not destroyed.
上記課題を解決するために、この発明は、トンネル絶
縁膜を、高温熱チッ化により形成したチッ化シリコン膜
を熱酸化した酸化チッ化膜を用いることにより、高電界
ストレスに強く、書換えによる偶発破壊を防止した。In order to solve the above-mentioned problems, the present invention provides a tunnel insulating film which is resistant to high electric field stress by using a thermal oxidation of a silicon nitride film formed by high-temperature thermal nitriding, and Prevented destruction.
以下に、この発明の実施例を図面にもとづいて説明す
る。Ｎ型のメモリの場合について説明する。第１図
（ｇ）が最終断面図であるが、Ｐ型シリコン基板１の表
面にお互いに間隔をおいてN+型のソース領域10とドレイ
ン領域11及びトンネルドレイン領域２が形成されてい
る。トンネルドレイン領域２の上には、部分的にトンネ
ル酸化チッ化膜６が設けられている。また、ソース領域
２とトンネルドレイン領域２との間の半導体基板１の表
面であるチャネル領域の上には、酸化膜３が設けられ、
さらに、その上にCVDシリコンチッ化膜４が設けられて
いる。浮遊ゲート電極７は、トンネル酸化チッ化膜５と
CVDシリコンチッ化膜４の上に設けられ、さらに、浮遊
ゲート電極７の上には、制御ゲート電極９が制御ゲート
酸化膜８を介して設けられている。Hereinafter, embodiments of the present invention will be described with reference to the drawings. The case of an N-type memory will be described. FIG. 1 (g) is a final sectional view, in which an N + type source region 10, a drain region 11 and a tunnel drain region 2 are formed on the surface of a P type silicon substrate 1 at intervals. A tunnel oxide nitride film 6 is partially provided on tunnel drain region 2. An oxide film 3 is provided on a channel region which is a surface of the semiconductor substrate 1 between the source region 2 and the tunnel drain region 2,
Further, a CVD silicon nitride film 4 is provided thereon. The floating gate electrode 7 is connected to the tunnel oxide nitride film 5.
A control gate electrode 9 is provided on the CVD silicon nitride film 4, and a control gate electrode 9 is provided on the floating gate electrode 7 via a control gate oxide film 8.
本発明のメモリの読み出し動作は、ソース領域10とト
ンネルドレイン領域２との間のチャネル領域のコンダク
タンスが、浮遊ゲート電極７に含まれている電荷量によ
って変化することによって行なわれる。The read operation of the memory of the present invention is performed by changing the conductance of the channel region between the source region 10 and the tunnel drain region 2 depending on the amount of charge contained in the floating gate electrode 7.
また、情報のプログラムは、制御ゲート電極９とドレ
イン領域11との間に高電圧を印加することにより、トン
ネル酸化チッ化膜６に高電界を集中させトンネル電流を
トンネルドレイン領域２と浮遊ゲート電極７との間に流
すことにより行うことができる。The information program is performed by applying a high voltage between the control gate electrode 9 and the drain region 11 to concentrate a high electric field on the tunnel oxide nitride film 6 and apply a tunnel current to the tunnel drain region 2 and the floating gate electrode. 7 can be performed.
本発明のトンネル絶縁膜である酸化チッ化膜の製造方
法について説明する。The method for manufacturing the nitrided oxide film as the tunnel insulating film of the present invention will be described.
まず、第１図（ａ）に示すように、基板１の全面に酸
化膜３及びCVDシリコンチッ化膜４を形成し、トンネル
領域になる領域を、フォトリソ工程により第１図（ｂ）
のように、酸化膜３及びCVDシリコンチッ化膜をエッチ
ングして基板１まで穴あけする。次に100Å以下の熱シ
リコンチッ化膜５を形成して、第１図（ｃ）のようにす
る。次に、この熱シリコンチッ化膜５を900℃以上の温
度で、熱酸化して、その上に、多結晶シリコン薄膜から
なる浮遊ゲート電極７を形成して、第１図（ｄ）のよう
にする。次に、1000℃以上の高温で浮遊ゲート電極７を
酸化して制御ゲート酸化膜８を形成し第１図（ｅ）のよ
うにする。その上に、制御ゲート電極９を形成し、第１
図（ｆ）のように形成する。さらに、ソース領域10及び
ドレイン領域11を浮遊ゲート電極７をマスクにしてドー
ピングすることにより、第１図（ｇ）のメモリが完成す
る。First, as shown in FIG. 1 (a), an oxide film 3 and a CVD silicon nitride film 4 are formed on the entire surface of a substrate 1, and a region to be a tunnel region is formed by a photolithography process in FIG. 1 (b).
As described above, the oxide film 3 and the CVD silicon nitride film are etched to form a hole up to the substrate 1. Next, a thermal silicon nitride film 5 of 100 ° or less is formed, as shown in FIG. 1 (c). Next, the thermal silicon nitride film 5 is thermally oxidized at a temperature of 900 ° C. or higher, and a floating gate electrode 7 made of a polycrystalline silicon thin film is formed thereon, as shown in FIG. To Next, the control gate oxide film 8 is formed by oxidizing the floating gate electrode 7 at a high temperature of 1000 ° C. or more, as shown in FIG. A control gate electrode 9 is formed thereon, and the first
It is formed as shown in FIG. Further, by doping the source region 10 and the drain region 11 using the floating gate electrode 7 as a mask, the memory shown in FIG. 1 (g) is completed.
本発明のトンネル絶縁膜である酸化チッ化膜６は、非
常に酸化速度の遅い、熱シリコンチッ化膜５を高温で長
時間で酸化して形成するために、その品質は、従来のシ
リコン酸化膜に比べ優れている。その結果、書換えによ
るトンネル絶縁膜の破壊がきわめて少ないメモリが実現
できる。また、電気的書換え可能な半導体メモリの場
合、プログラム時に、ドレイン領域11、あるいは、制御
ゲート電極８に約10V以上の高電圧を印加する。この電
圧を制御する回路が、同一基板上に形成されている。本
発明のメモリにおいては、その高電圧制御用トランジス
タのゲート絶縁膜として、チャネル領域上の酸化膜３と
CVDシリコンチッ化膜４との複合膜を用いることによ
り、ゲート耐圧の高いトランジスタを形成できる。Since the thermal oxidation silicon nitride film 6, which is a tunnel insulating film of the present invention, is formed by oxidizing the thermal silicon nitride film 5 at a very high temperature for a long time at a very low oxidation rate, the quality thereof is the same as that of the conventional silicon oxide film. Superior to membrane. As a result, a memory in which destruction of the tunnel insulating film by rewriting is extremely small can be realized. In the case of an electrically rewritable semiconductor memory, a high voltage of about 10 V or more is applied to the drain region 11 or the control gate electrode 8 during programming. A circuit for controlling this voltage is formed on the same substrate. In the memory of the present invention, the oxide film 3 on the channel region serves as a gate insulating film of the high voltage control transistor.
By using a composite film with the CVD silicon nitride film 4, a transistor having a high gate breakdown voltage can be formed.
また、制御ゲート酸化膜８は、1000℃以上の高温で、
浮遊ゲート電極７の熱酸化により形成する。この工程
は、浮遊ゲート電極７が多結晶シリコンであるため、そ
の上の膜の品質を保つように高温熱酸化工程で製造せざ
るをえない。本発明のメモリでは、トンネル絶縁膜が酸
化チッ化膜であるために、このような高温熱処理工程で
あっても、トンネル絶縁膜の品質は劣化しない。従来
は、トンネル絶縁膜が、100Å程度のシリコン酸化膜で
形成されていたために、この制御ゲート酸化工程により
品質が低下するという問題があった。本発明のメモリ
は、制御ゲート電極９を浮遊ゲート電極７の上に形成し
た例で説明したが、制御ゲート電極９は、基板１の表面
に形成してもよい。しかし、第１図のような構造のメモ
リに、特に適している。即ち、酸化チッ化膜が高温工程
に強いからである。Further, the control gate oxide film 8 is formed at a high temperature of 1000 ° C. or more,
The floating gate electrode 7 is formed by thermal oxidation. In this step, since the floating gate electrode 7 is made of polycrystalline silicon, it must be manufactured by a high-temperature thermal oxidation step so as to maintain the quality of the film thereon. In the memory of the present invention, the quality of the tunnel insulating film does not deteriorate even in such a high-temperature heat treatment step because the tunnel insulating film is an oxide nitride film. Conventionally, since the tunnel insulating film is formed of a silicon oxide film having a thickness of about 100 °, there is a problem that the quality is deteriorated by the control gate oxidation step. Although the memory of the present invention has been described with an example in which the control gate electrode 9 is formed on the floating gate electrode 7, the control gate electrode 9 may be formed on the surface of the substrate 1. However, it is particularly suitable for a memory having a structure as shown in FIG. That is, the oxide silicon nitride film is resistant to the high temperature process.
この発明は、以上説明したように、トンネル絶縁膜と
して、酸化チッ化膜を用いているために、後工程の制御
ゲート酸化の高温プロセスによる品質低下を防ぎ、書換
え回数の向上をする効果がある。According to the present invention, as described above, since the nitrided oxide film is used as the tunnel insulating film, it is possible to prevent the quality deterioration due to the high-temperature process of the control gate oxidation in the later process and to improve the number of rewrites. .
第１図（ａ）〜（ｇ）は、この発明にかかる半導体不揮
発性メモリの製造方法の工程順断面図であり、第２図
は、従来の半導体不揮発性メモリの断面図である。 ６……トンネル酸化チッ化膜 ７……浮遊ゲート電極 16……トンネル酸化膜1A to 1G are cross-sectional views in the order of steps of a method for manufacturing a semiconductor non-volatile memory according to the present invention, and FIG. 2 is a cross-sectional view of a conventional semiconductor non-volatile memory. 6 tunnel oxide film 7 floating gate electrode 16 tunnel oxide film
Claims (3)
縁膜を形成する工程と、トンネル領域となる領域の前記
ゲート絶縁膜をエッチングすることによりトンネル領域
を形成する工程と、前記トンネル領域に100Å以下の熱
シリコン窒化膜を形成する工程と、前記熱シリコン窒化
膜を900℃以上の温度で熱酸化する工程と、前記ゲート
絶縁膜および前記熱シリコン窒化膜を熱酸化した酸化窒
化膜の上に浮遊ゲート電極を形成する工程よりなること
を特徴とする半導体不揮発性メモリの製造方法。A step of forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type; a step of forming a tunnel region by etching the gate insulating film in a region to be a tunnel region; Forming a thermal silicon nitride film having a thickness of 100 ° or less; thermally oxidizing the thermal silicon nitride film at a temperature of 900 ° C. or higher; and forming an oxide oxynitride film obtained by thermally oxidizing the gate insulating film and the thermal silicon nitride film. A method for manufacturing a semiconductor nonvolatile memory, comprising a step of forming a floating gate electrode thereon.
熱酸化することにより制御ゲート酸化膜を形成する工程
と、前記制御ゲート酸化膜の上に制御電極を形成する工
程を更に含む請求項１記載の半導体不揮発性メモリの製
造方法。2. The method according to claim 1, further comprising the steps of: forming a control gate oxide film by thermally oxidizing the floating gate electrode at a high temperature of 1000 ° C. or more; and forming a control electrode on the control gate oxide film. 2. A method for manufacturing a semiconductor nonvolatile memory according to item 1.
膜を形成する工程と、CVDシリコン窒化膜を形成する工
程より成る請求項１記載の半導体不揮発性メモリの製造
方法。3. The method according to claim 1, wherein the step of forming the gate insulating film comprises the steps of forming an oxide film and forming a CVD silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63138728A JP2696103B2 (en) | 1988-06-06 | 1988-06-06 | Manufacturing method of semiconductor nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63138728A JP2696103B2 (en) | 1988-06-06 | 1988-06-06 | Manufacturing method of semiconductor nonvolatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01307272A JPH01307272A (en) | 1989-12-12 |
| JP2696103B2 true JP2696103B2 (en) | 1998-01-14 |
Family
ID=15228770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63138728A Expired - Lifetime JP2696103B2 (en) | 1988-06-06 | 1988-06-06 | Manufacturing method of semiconductor nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2696103B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4296128B2 (en) | 2004-06-23 | 2009-07-15 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
| JP5032056B2 (en) | 2005-07-25 | 2012-09-26 | 株式会社東芝 | Method for manufacturing nonvolatile semiconductor memory device |
-
1988
- 1988-06-06 JP JP63138728A patent/JP2696103B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01307272A (en) | 1989-12-12 |
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