JP2670651B2 - 出力装置 - Google Patents

出力装置

Info

Publication number
JP2670651B2
JP2670651B2 JP3264635A JP26463591A JP2670651B2 JP 2670651 B2 JP2670651 B2 JP 2670651B2 JP 3264635 A JP3264635 A JP 3264635A JP 26463591 A JP26463591 A JP 26463591A JP 2670651 B2 JP2670651 B2 JP 2670651B2
Authority
JP
Japan
Prior art keywords
output
channel transistor
level
output device
switching means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3264635A
Other languages
English (en)
Japanese (ja)
Other versions
JPH05110402A (ja
Inventor
大助 七戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3264635A priority Critical patent/JP2670651B2/ja
Priority to NL9201779A priority patent/NL9201779A/nl
Priority to US07/959,910 priority patent/US5343099A/en
Publication of JPH05110402A publication Critical patent/JPH05110402A/ja
Application granted granted Critical
Publication of JP2670651B2 publication Critical patent/JP2670651B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/817—Combinations of field-effect devices and resistors only

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
JP3264635A 1991-10-14 1991-10-14 出力装置 Expired - Fee Related JP2670651B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP3264635A JP2670651B2 (ja) 1991-10-14 1991-10-14 出力装置
NL9201779A NL9201779A (nl) 1991-10-14 1992-10-13 Werkwijze en inrichting voor een met hoge snelheid werkend uitgangsorgaan.
US07/959,910 US5343099A (en) 1991-10-14 1992-10-13 Output device capable of high speed operation and operating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3264635A JP2670651B2 (ja) 1991-10-14 1991-10-14 出力装置

Publications (2)

Publication Number Publication Date
JPH05110402A JPH05110402A (ja) 1993-04-30
JP2670651B2 true JP2670651B2 (ja) 1997-10-29

Family

ID=17406091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3264635A Expired - Fee Related JP2670651B2 (ja) 1991-10-14 1991-10-14 出力装置

Country Status (3)

Country Link
US (1) US5343099A (enExample)
JP (1) JP2670651B2 (enExample)
NL (1) NL9201779A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100261962B1 (ko) * 1993-12-31 2000-07-15 김영환 데이타 출력버퍼
JP3229164B2 (ja) * 1994-07-28 2001-11-12 インターナショナル・ビジネス・マシーンズ・コーポレーション ラッチ回路
US5418476A (en) * 1994-07-28 1995-05-23 At&T Corp. Low voltage output buffer with improved speed
US5892383A (en) * 1995-06-13 1999-04-06 Intel Corporation Parallel voltage controlled resistance elements
TW372101U (en) * 1996-10-11 1999-10-11 United Microelectronics Corp Input buffer
US6100743A (en) * 1998-08-25 2000-08-08 Lucent Technologies Inc. Circuit arrangement for adding functionality to a circuit with reduced propagation delays
JP3950120B2 (ja) * 2004-03-31 2007-07-25 株式会社東芝 ドライバ回路及びドライバ回路を有するシステム
US7518424B2 (en) * 2004-11-08 2009-04-14 Elite Semiconductor Memory Technology Inc. Slew rate controlled output circuit
JP2008219249A (ja) * 2007-03-01 2008-09-18 Nec Corp Ｃｍｏｓ回路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1938468C3 (de) * 1969-07-29 1974-04-25 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Dynamische Schaltungsanordnung
JPS5696532A (en) * 1979-12-29 1981-08-04 Citizen Watch Co Ltd Frequency divider
JPS5772429A (en) * 1980-10-22 1982-05-06 Toshiba Corp Semiconductor integrated circuit device
JPS61292412A (ja) * 1985-06-20 1986-12-23 Fujitsu Ltd 出力回路
US4736117A (en) * 1986-11-14 1988-04-05 National Semiconductor Corporation VDS clamp for limiting impact ionization in high density CMOS devices
JPH01305616A (ja) * 1988-06-02 1989-12-08 Toshiba Corp 半導体集積回路の出力回路
JPH02162824A (ja) * 1988-12-16 1990-06-22 Hitachi Ltd 半導体集積回路装置
US5089728A (en) * 1989-09-06 1992-02-18 National Semiconductor Corporation Spike current reduction in cmos switch drivers
JPH0793565B2 (ja) * 1989-11-09 1995-10-09 日本電気株式会社 レベル変換回路
JPH03217118A (ja) * 1990-01-23 1991-09-24 Matsushita Electric Ind Co Ltd 論理増幅器
JPH04114511A (ja) * 1990-09-05 1992-04-15 Nec Corp Ｃｍｏｓインバータ

Also Published As

Publication number Publication date
NL194383C (enExample) 2002-02-04
NL194383B (enExample) 2001-10-01
JPH05110402A (ja) 1993-04-30
NL9201779A (nl) 1993-05-03
US5343099A (en) 1994-08-30

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Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19970603

LAPS Cancellation because of no payment of annual fees