JP2591141B2 - One-way communication control circuit between 2 cpu - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention controls data communication between microcomputers when performing one-way data communication between the microcomputers in a circuit using two or more microcomputers. The present invention relates to a circuit for performing the operation and a mobile control device using the circuit.

2. Description of the Related Art Conventionally, in a distributed processing system using a plurality of microcomputers, information exchange (communication) between microcomputers has been performed by serial transmission as shown in FIG. In FIG. 3, 1 and 2 are microcomputers, 29 and 30 are serial transmission converters, and 31 and
32 is a parallel transmission line, and 33 is a serial transmission line. Also,
34 is a transmission control line. In the serial transmission, as shown in FIG. 3, serial transmission is performed between the serial transmission converters 29 and 30 provided between the microcomputers 1 and 2, and control relating to the transmission is performed using the transmission control line 34. I do. For example, as shown in FIG. 4, the transmitting side of the information issues a transmission request signal by lowering the transmission request signal to L, and the receiving side that has received the transmission request signal lowers the transmission enable signal to L, for example. Reply signal. The transmitting side that has received the returned transmission enable signal issues a transmission start signal, for example, an L pulse signal, and starts information transmission. Then, upon receiving a reception completion signal, for example, a pulse of L, indicating that the unit information amount (for example, 1 byte) has been received from the reception side, the transmission side clears the transmission request signal, and the reception side clears the transmission enable signal. I do. One transmission is completed by the above steps.

As another method, FIG. 5 shows a method of directly connecting the ports of the microcomputers 1 and 2 and performing parallel transmission using the parallel transmission line 31 and the transmission control line 34. FIG. 6 also shows that each microcomputer has a common memory location by using a shared memory 35 between the two microcomputers 1 and 2 to write and read data to and from each other, and to connect the data buses 7 and 9 to each other. It shows a method of transmitting information by using the method.

The serial transmission means according to the above-described conventional configuration requires a serial transmission conversion unit for each microcomputer,
Therefore, there are problems that the circuit configuration becomes large and that the amount of information that can be transmitted per unit time due to serial transmission is small. To solve this, there are methods of directly connecting microcomputers or performing parallel transmission using a shared memory, but each has the following problems. The method of directly connecting microcomputers is that when data is transmitted between microcomputers, both microcomputers perform the processing for transmission at the same time, so each processing is interrupted and the processing capacity is reduced. It is connected. Further, in the configuration using the shared memory, when writing or reading from two microcomputers is performed at the same time, a circuit for arbitrating the writing or reading is required, which complicates the circuit configuration and increases the circuit space. Things. There is also a shared memory with such a circuit built in, but using it in a system with only a large capacity and communicating with a small amount of information is not very efficient due to the time spent on communication and its circuit space. Is not good.

The present invention solves such a conventional problem,
With a simple configuration that requires a small circuit space, communication with a small amount of information can be performed with as little interruption time as possible.
An object of the present invention is to provide a communication control circuit capable of efficiently transmitting information in one direction.

Means for Solving the Problems The means for achieving the object of the present invention include a master microcomputer and a slave microcomputer, a register file having both a read-only address port and a write-only address port, and a master side. When a microcomputer reads the data of the register file, a read signal generator that sends a read signal to the register file by an address signal and a read signal output from the master microcomputer, and a slave microcomputer. When writing data to the register file, a write signal to the register file is generated based on an address signal, a write signal, and an output signal from the read signal generator output from the microcomputer on the slave side. And a write signal generating unit for sending the two-way communication signal between the two CPUs.

Operation With the configuration of the present invention, one-way communication with a small amount of information between two microcomputers can be efficiently performed in a small circuit space without interruption of each processing.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a one-way communication control circuit between two CPUs according to an embodiment of the first means. 1 is a microcomputer on the master side, and 2 is a microcomputer on the slave side. In the present embodiment, the microcomputer 1 on the master side is a multichip of 8 bits or the like (a microcomputer in which data lines and address lines are output to the outside), and the microcomputer 2 on the slave side is a 4-bit one chip. Microcomputer (a type of microcomputer with many I / O ports without data lines and address lines being output to the outside). 3a and 3b are register files (for example, TTL LS670) having both a read-only address port and a write-only address port, and 4 is used when the microcomputer 1 on the master side reads data in the register files 3a and 3b. , An address signal (signal on the address bus 6) output from the microcomputer 1 on the master side and a read signal (/ RD signal 1).
0), and a read signal generation unit for sending a read signal to the register files 3a and 3b by taking a logical product with the register files 3a and 3b.
When writing data to 3b, the address signal (signal on the address bus 8) and the write signal (/ WR signal 11) output from the microcomputer 2 on the slave side and the output signal from the read signal generator 4 are output. This is a write signal generation unit that takes a logical product of the inverted signals and sends a write signal to the register files 3a and 3b. Reference numeral 6 denotes an address bus of the microcomputer 1 on the master side, and reference numeral 7 denotes a data bus of the microcomputer 1 on the master side. 8 is a register file of the microcomputer 2 on the slave side.
An address bus 9 is used when writing data to 3a and 3b, and 9 is a data bus of the microcomputer 2 on the slave side.

The operation and operation of the one-way communication control circuit between the two CPUs configured as described above will be described below. First, as shown in FIG. 1, the communication direction is from the microcomputer 2 on the slave side to the microcomputer 1 on the master side.
And the register files 3a and 3b have two configurations, so that the information amount of communication performed between the microcomputer 1 on the master side and the microcomputer 2 on the slave side is 4 bytes. (Because the TTL LS670 is used for the register file.) In order for the microcomputer 1 on the master side to read the data of the register files 3a and 3b written by the microcomputer 2 on the slave side, it is necessary to use the register file.
The addresses of 3a and 3b are output onto the address bus 6, and the read signal (/ RD signal 10) is dropped from H to L.
Is output to ) Data on the data bus 7 is input. At the time of this reading operation, the read signal generation unit 4 performs an AND operation on an address signal (signal on the address bus 6) output from the microcomputer 1 on the master side and a read signal (/ RD signal 10). Register file
Output to read permission terminals (not shown) of 3a and 3b. As a result, the data of the register files 3a and 3b is output on the data bus 7 and input to the microcomputer 1 on the master side. When transmitting data from the microcomputer 2 on the slave side to the microcomputer 1 on the master side, the microcomputer 2 on the slave side wants to transmit data to the register files 3a and 3b.
The byte data is output on the data bus 9, the addresses of the register files 3a and 3b are output on the address bus 8, and the write signal (/ WR signal 11) is lowered from H to L.
At this time, the write signal generator 5 outputs the write signal (/ WR signal 11), the addresses of the register files 3a and 3b, and the read signal output from the read signal generator 4. Logical product with inverted output, register file
Output to write enable terminals (not shown) of 3a and 3b. This is because when the master microcomputer 1 is not performing the read operation of the data of the register files 3a and 3b written by the slave microcomputer 2, the slave microcomputer 2
This means that the data is actually written to the register files 3a and 3b only when the data is written into the register files 3a and 3b. This is more than the time that the slave microcomputer 2 drops the write signal (/ WR signal 11) to L, and the time that the master microcomputer 1 spends reading the data in the register files 3a and 3b. By setting, data is surely written to the register files 3a and 3b. That is, the microcomputer 1 on the master side can read the data in the register files 3a and 3b at any time regardless of the microcomputer 2 on the slave side.

FIG. 2 is a system block diagram of a moving object control device according to an embodiment of the second means. Reference numeral 12 denotes a motor for running the main body, reference numeral 13 denotes a drive circuit thereof, and reference numeral 14 denotes a travel encoder that detects the rotation speed of the travel motor 12. Above, the microcomputer 2 on the slave side, the traveling encoder 14,
The driving means 13 comprises the driving circuit 13, the traveling motor 12, and the microcomputer 2 on the slave side. Likewise
16 is a main body steering motor, 17 is its drive circuit,
Reference numeral 18 denotes a steering encoder that detects the rotation speed of the steering motor 16. The steering encoder 18, drive circuit 17, steering motor 16 and microcomputer 2 on the slave side
Together, the steering means 19 is constituted. Reference numeral 20 denotes a direction detection sensor attached to the main body. In this embodiment, a rate gyro is used. The traveling encoder 14 and the direction detecting sensor 20 constitute a position recognizing means 21 for recognizing the position of the main body. That is, the position of the main body is recognized by detecting the rotation speed detected by the traveling encoder 14 and the running direction of the main body detected by the direction detection sensor 20. Reference numeral 22 denotes a distance measuring sensor such as an ultrasonic sensor or a photo sensor provided around the main body, and measures a distance to an obstacle. 23 is a contact sensor attached to the outer periphery of the main body, which detects that the main body has contacted an obstacle. The distance measuring sensor 22, the contact sensor 23, and the microcomputer 2 on the slave side constitute an obstacle detecting means 24. Reference numeral 1 denotes a master microcomputer having a storage device 25 and constituting a judgment processing section for outputting signals to the traveling and steering means. Reference numeral 26 denotes a one-way communication control circuit which constitutes the first means (excluding the microcomputer on the master side). Reference numeral 27 denotes an operation switch for instructing a start / stop operation of the main body. As shown in the figure, information on the operation switches is input to the microcomputer 1 through the data bus 7 through the input port 28.

In the moving object control device configured as described above, the microcomputer 1 on the master side and the obstacle detection means 24
In the communication with the microcomputer 2 on the slave side, the data of the microcomputer 2 on the slave side can be input efficiently without any stop time of the processing when viewed from the microcomputer 1 on the master side.

As described above, according to the present invention, the information acquisition side can read the information in the register file at any time without requiring any special processing for the acquisition. In addition, by providing a register file of the amount of information required for communication, waste of time spent for writing and reading data can be reduced, and the circuit space required can be minimized, so that waste is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a one-way communication control circuit between 2 CPUs according to an embodiment of the first means of the present invention, FIG. 2 is a system block diagram of a mobile control apparatus according to an embodiment of the second means, FIG. 3 is a diagram showing a state of communication by conventional serial transmission, FIG. 4 is a detailed explanatory diagram thereof, and FIG. 5 is a diagram showing a method of performing parallel transmission by directly connecting ports of microcomputers. FIG. 6 is a diagram showing a method of transmitting information by providing a shared memory between microcomputers. DESCRIPTION OF SYMBOLS 1 ... Master microcomputer, 2 ... Slave microcomputer, 3a, 3b ... Register file, 4 ... Read signal generator, 5 ... Write signal generator, 15 ... Running means, 19 ... Steering means, 21 ... Position detection Means 24 obstacle detection means 25 storage device.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hidetaka Yabuuchi 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Inside

Claims (1)

(57) [Claims] 1. A master microcomputer, a slave microcomputer, a register file having both a read-only address port and a write-only address port, and a master microcomputer reading data in the register file. To
A read signal generator for sending a read signal to the register file by an address signal and a read signal output from the master microcomputer, and a slave microcomputer when the slave microcomputer writes data to the register file. A two-cpu one-way communication control circuit, comprising: a write signal generator that sends a write signal to the register file according to an address signal, a write signal output from the microcomputer, and an output signal from the read signal generator.