SU1411762A1 - Device for interfacing computer with communication channels - Google Patents

Abstract

The invention can be used in an information processing system and allows the reception of information from several channels and its transmission to a computer. The purpose of the invention is to improve the speed and increase the reliability of information transfer during its reception and transmission to a computer. The device contains at the input of the bus I channels connected to the inputs of the converter 2 bipolar code into unipolar, the outputs of which are connected to the information inputs of the switch of 3 channels. The control inputs of the switch 3 are connected to the output of the 4-pulse generator, and the outputs are connected to the information inputs of the service word register 5. The address multiplexer 6 generates address codes to the inputs of blocks 7 and 8 of the buffer memory. The output of block 8 is connected to the input of the bus driver 9, the output of which is the output of the device (data bus 10). To increase the speed, a block of 11 service words, an encoder 12 and an address counter 13 are entered into the device. Information is exchanged between the device and the computer, led by commands that are received at the input of the encoder 12 via the buses 14 addresses. 1 il. He, Hf, Ml, tj.fin, fgj C (L 9Sh)

Description

The invention relates to computing and can be used to receive serial information from multiple sources, buffering it and interface computers with several communication channels.

 The purpose of the invention is to increase the speed (receiving information from several sources, allowing to track any changes in any channel) and the reliability of information transmission.

The drawing shows the layout of the device.

The device contains buses of 1 channels, converter 2 of a bipolar code into a unipolar, switch of 3 channels, a generator of 4 pulses, the service word (H ("., Np, A, D ;,) corresponding to the connected (i-th ) the channel is overwritten from the block 1 of the memory of the control word into the register 5 of the control word. The control word of any channel contains information about the beginning of the word Nel.

about the number of accepted bits (Nf 1,2,3,.,. 32), about the previous state in the channel () ° state of address bits (A 1,2, .., 8), about the state of bit Dov data (D {

 Jj2 ..., 32), Information on the beginning of a word (Nel) on the number of accepted bits (Np), on the previous state (FO,., - ,, Fsf.,) Is fed to the input. encoder 12 which analyzes

gistr 5 service word multiplexed 20 received for all address inputs

information (N,

F ..

sor of address 6, first 7 and second 8 blocks of buffer memory, bus driver 9, the output of which is output 10 of the device (bidirectional data bus), memory block 1 service: rhythm, encoder 12, executed, for example, on the PROM, counter 13 and bus J4 addresses.

The device works as follows .. 30

Consecutive 32 bits

N,

F,

ate p -di-l sim t

  regardless of the bus signals, the address 14 generates control signals in accordance with algoFg,)

The beginning of the word H,

if a

T 2

(F, Fg.-F, -., - F5 ,,), 4T;

Fulfillment contains 1 if R "N

,, .-. -Fg,.,; .

The bit contains O, if P “- H ,. . -F.-fg ..,

codes (Fd, Fg .., Fd Fg in parallel along all buses of channel 1 are fed to the inputs of converter 2, which converts them into unipolar codes

logical equations (F

"1S a)

.. F,

am

% gp) transfers to the information inputs of the switch 3 channels.

The information of any (i-ro) channel from the first and second outputs of the switch-3 channels (F, Fg) is output to the information inputs of the service word register 5 and to the inputs of the encoder 12. The time to which the

T

The 1st channel t- is determined by the output signals f of the generator 4, and the 3 channels coming to the control input of the switch (T is the period of following bits in the channel words, m is the number of channels). Simultaneously, the output signals of the generator 4 are received; f is the input of the encoder 12, fg is the address input of the memory word memory block 11, and the output signals of the encoder 12 are fed to the control inputs of the memory 11 memory, word and register 5 service word.

information (N,

F ..

rhythm:

N,

F,

ate p -di-l SIM

  regardless of the bus signals, the address 14 generates control signals in accordance with algoFg,)

ohm:

The beginning of the word H,

if a

T 2

5 rhythm:

0

(F, Fg.-F, -., - F5 ,,), 4T;

Fulfillment contains 1 if R "N

,, .-. -Fg,.,; .

The bit contains O, if P “- H ,. . -F.-fg ..,

Pause between bits, if P

  "- t

H,

%, (M Si + F

01-1

five

ate 011

 Ffii-t);

Record address if ZP N

.-Fsi-r Fs)

Writing a word to the first buffer memory 7:

ate and

0

 F,

& 1-, where N,

ZP-, N + F

ate

; ± cl

N.

From

; -t) J

% r (F

aiM

N .. N

s f

0

qi

ai

% Frv.

Ol

B2

qi-1 6i is the number of connections of this channel. Liza;

8 or 32 bits;

the current channel status is 1; the current channel state is 0;

q; -i Si-i

oi-i oi- - (

five

previous channel condition equal to 1;. previous state in the channel, equal to O. According to the results of the analysis and under the influence of the control signals of the encoder 12, a new service word is formed (H

CA S

N

P AI

D,

one .

F Fg) in the register 5 of the service cjlov, then rewritten into the block 11 of the memory of the service word. If 32 bits are received, then the word D-, arriving at the information input of block 7, is written into block 7 in the cell corresponding to the received address A; received at the address input of block 7 (A, -, A); the word (all bits of the control word are 0) in register 5 of the control word, and the next (i + 1) -th channel is connected for analysis. In addition, in parallel, with the reception of information and recording it in block 7, information D is rewritten from block 7 B by block 8. For this, the output code of the counter 13 address goes to the second address input of the multiplexer 6 address, from the first and second output of which it enters to address inputs (A, A) and (A |, A of blocks 7 and 8. Control signals from the output of the encoder 12 block

7 transferred to the issuance mode, and the block

8- to record information. The exchange takes place between the memory cells of the same name and, after the exchange of the address 13 under the influence of the control signals of the encoder 12, is added 1. Sequentially word for word, the entire information of the block 7 is rewritten into block 8.

Information is exchanged between the computer and the proposed device regardless of its reception from the channels and starts when the command address 14 of the exchange command arrives from the computer 14, which is decoded and stored in the encoder 12, and the Ready signal is output to the computer. (D) from block 7 is not overwritten to block 8, which from that moment is transferred to the information output mode (D). „) In a computer. Then the computer sends the address entry command via the address bus 14, and the address of the cell from which the information is required via the data bus 10.

This address (A) is fed to the third address input of the multiplexer 6 address, is stored in it, and is output to the computer, the signal is Ready. Then, a data entry command is received from the computer via the address bus 14 via which the contents are output to the computer from block 8 via the bus driver 9 (the requested cell on bus 10 dan

five

0

five

0

five

0

five

0

five

Signal and signal Done. A computer writes this word in its memory and asks for the contents of another cell, etc. until he considers all the information she needs. After this, the computer, via the address bar 14, gives the command End of Exchange, which removes the Start of Exchange command and the device goes into receiving mode, recording information into block 7 and rewriting it into block 8. During the exchange of information with the computer for information received in this time from the channels is received and recorded in block 7.

Claims (1)

Invention Formula Device for coupling. A computer with communication channels containing a bipolar code to single-field converter, whose inputs are device inputs for connecting to communication channels, and the first and second groups of outputs are connected to the first and second groups of information inputs of the channel switch, controlling the input of which is connected to the first output of the pulse generator; The first and second outputs of the channel switch are connected respectively to the first and second information inputs of the service word register, the output of which is connected to the first address input of the address multiplexer and the information input of the first block of the buffer memory, the address input of which is connected to the first output. the address multiplexer, the output of the first block of the buffer memory is connected to the information input of the second block of the buffer memory, whose address input is connected to the second output of the address multiplexer, the output of the second. the buffer memory block is connected to: the information input of the shaper generator, the output of which is the output of the device for connecting to the computer data bus and connected to the second address input of the address multiplexer, characterized in that, in order to increase speed and increase reliability transferring information, the device contains a memory block of service words, an encoder and a counter, the counter output being connected to the third address input of the address multiplexer, the first to eighth outputs of the encoder are connected respectively to sync rods memory block of service words, service word register, first and second blocks of buffer memory, bus driver, address multiplexer, counting counter input and output device readiness, output of memory word memory block connected to the third information input of the service word register, Q channels, and the fifth input is the output of which is connected to the information input of the memory service unit oI4117626 words, and the first input of the encoder, the address input of the memory block of service words is connected to the first output of the pulse generator, the second output of which is connected to the second input of the encoder, the third and fourth inputs of which are connected respectively to the first and second outputs of the switch the device input to connect to the address of the computer bus.