JPS61201361A - Communication system between microprocessors - Google Patents

Abstract

PURPOSE:To perform transfer by using serial ports between microprocessors which differ in serial communication system by generating a clock signal with a serial transfer speed through the mutual synchronization of a counter between clock signals. CONSTITUTION:When data is set in the serial buffer 5 of the 1st microprocessor 1, a status signal (b) becomes busy and when the transmission of the data from the serial buffer 5 is completed and a stop bit SP is sent out, the status signal becomes ready. The sent data is applied to the serial input port SI and interruption port IRQ of the 2nd microprocessor 2, and when a start bit is detected, the counter is started and a clock signal CK 2 is applied to a serial clock port SC, so that received data is written in a serial buffer 6. The status signal (c) of the serial buffer 6 becomes full and the data is transferred to a logical processing part, etc.

Description

[Detailed Description of the Invention] [Summary] In a communication method between microprocessors, a common counting means is provided, and a clock signal generated by the counting means enables communication between microprocessors using different communication methods. shall be.

[Industrial application field]

The present invention relates to an inter-microprocessor communication system for transmitting and receiving serial data using serial ports between a microprocessor having an asynchronous serial port and a microprocessor having a synchronous serial port.

Multiprocessor systems, which are equipped with multiple microprocessors and perform distributed processing, are often used.For example, in high-performance telephones, an 8-bit microprocessor that is capable of high-speed processing but is expensive, and an inexpensive 8-bit microprocessor that performs distributed processing are often used. However, a 4-bit microprocessor with low-speed processing is provided, and data is transferred between the 8-bit microprocessor and the 4-bit microprocessor, and the 8-bit microprocessor is used to send and receive control information to and from the exchange. A configuration has been proposed in which control is performed and a 4-bit microprocessor performs push button switch input processing, display processing, etc.

[Conventional technology]

In such multiprocessor systems, serial communication methods often differ; in the case mentioned above, an 8-bit microprocessor has an asynchronous serial port, and a 4-bit microprocessor has a synchronous serial port. Therefore, since data cannot be transferred between serial ports, a configuration is adopted in which a buffer memory is provided between processors and parallel data is transferred using a parallel port.

FIG. 5 is a block diagram of a conventional example, in which 11 is a first microprocessor having an asynchronous serial port;
1 is a second microprocessor having a synchronous serial port, 13 is a buffer memory, 13A and 13B are buffer sections, SL is a serial input port, SO is a serial output port, SC is a serial clock port, IRQI, I
RQ2 is an interrupt signal, BSI, BS2 is a data bus, R1
, R2 is a successive control signal, Wl, W2 are write control signals, B
YI and BY2 are busy signals.

The buffer memory 13 is composed of buffer sections 13A and 13B, and when parallel data is applied via data buses BSI and BS2 and write control signals Wl and W2 are applied, the parallel data is written. . Then, the busy signal BY1. BY2 and interrupt signal IRQ1
．． IRQ2 is output. Also, when read control signals R1, R2 are applied, parallel data is transferred to data buses BS1. B
The busy signals BYI and BY2 indicate vacancy, and the output of the interrupt signals IRQI and IRQ2 is stopped.

The microprocessor 11.12 receives a busy signal BYI,
BY2 is monitored to identify whether or not the buffer memory 13 is free, and if the buffer memory 13 is free, the data buses BSI and BS2 are
It sends parallel data to the interrupt signal I.
It is determined by RQI and IRQ2 that data has been written into the buffer memory 13, and the parallel data is read out by successive control signals R1 and R2.

FIG. 6 is an explanatory diagram of the operation. When data is transferred from the first microprocessor 11 to the second microprocessor 12, the first microprocessor 11
The busy signal BYI shown in al is monitored and the busy signal BY
When I is "1" (empty), send the parallel data shown in (bl to data bus BSl. Then, (C)
A write control signal Wl shown in FIG. Parallel data is written into the buffer section 13B at the timing of the rise of the write control signal W1. By writing this parallel data, the interrupt signal IRQ2 shown in (d) becomes "0" indicating reception, and the busy signal BYI also becomes "O" indicating busy as shown in (a).

The second microprocessor 12 outputs “0” indicating reception.
In response to the interrupt signal I RQ2, the continuous control signal R2 shown in (e) is output. As a result, parallel data is read from the buffer section 13B to the data bus BS2 as shown in (f), and the second microprocessor 12 can read this parallel data. Buffer part 13B
By reading parallel data from
I becomes "1" indicating vacancy, and interrupt signal IRQI becomes "1" indicating no reception.

When transferring data from the second microprocessor 12 to the first microprocessor 11, (a) in FIG.
is the busy signal BY2, (b) is the parallel data of the data bus BS2, (C) is the write control signal w2, (d) is the interrupt signal I RQ 1 , (el is the read control signal R1, (f
) indicates the parallel data read out to the data path BSI, and communication between the microprocessors 11 and 12 can be performed via the buffer memory 13.

[Problem that the invention seeks to solve]

As mentioned above, data cannot be transferred between microprocessors 11 and 12 using different serial communication methods by directly connecting the serial ports, so data can be transferred via the buffer memory 13 using a parallel port. Microprocessors are generally configured to control peripheral devices on a per-boat basis, and parallel ports are used for inter-processor communication, so it is important to allocate ports for controlling peripheral devices. It had the disadvantage of being limited.

SUMMARY OF THE INVENTION An object of the present invention is to transfer serial data between microprocessors using different serial communication systems using an inexpensive configuration, thereby making effective use of ports.

[Means for solving problems]

The present invention will be explained using the principle block diagram shown in FIG. Between a first microprocessor 1 having an asynchronous serial port and a second microprocessor 2 having a synchronous serial port, the first microprocessor 1 is started and stopped under control from the second microprocessor 2, and Counting means 3 are provided for counting the clock signal CKI of the processor 1 to form the clock signal CK2 of the second microprocessor 2. Serial data to which a start bit and a stop bit have been added from the first microprocessor 1 is sent out from the serial output port SO. Second
The microprocessor 2 detects the start bit of the data, activates the counting means 3, and receives the serial data in accordance with the clock signal CK2 generated by the counting means 3. The microprocessor 2 of the writer 2 activates the counting means 3, and in accordance with the clock signal CK2 generated by the counting means 3, serial data to which a start bit and a stop bit are added is sent out from the serial output port SO. The first microprocessor 1 receives and identifies serial data by multi-point sampling in accordance with the clock signal CKI.

[Effect]

The counting means 3 forms a clock signal CK2 for serial data transmission/reception of the second microprocessor 2 having a synchronous serial port from a clock signal CKI for sampling of the first microprocessor l having an asynchronous serial port. Therefore, the second microprocessor 2 receives the clock signal CK2 formed by the counting means 3.
The first microprocessor 1 performs sampling identification of the received serial data using the clock signal CKI, thereby making it possible to communicate between processors using different communication methods without providing a pamphlet circuit or the like. There is.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, showing a serial output port So of a first microprocessor 1 having an asynchronous serial port and a serial input port So of a second microprocessor 2 having an asynchronous serial port. SI and interrupt baud) IRQ are connected, and the serial input port S1 of the microprocessor 1 of the writer 1 is connected to the serial output port SO of the second microprocessor 2.

The clock signal CKI applied to the serial clock port SC of the microprocessor 1 of the writer 1 is added to the counter (counting means) 3, and the clock signal C of the output of this counter 3 is
K2 is added to the serial clock port SC of the second microprocessor 2, and a start control signal is added to the counter 3 from the start control board SR of the microprocessor 2 of the writer 2.

Serial buffers 4 to 7 output status signals ad indicating whether data is being written or read. Further, 8.9 is a logic processing section. Serial buffer 5.7 contains data Dll with a start bit added to the beginning and a stop bit added to the rear.
, D21 are set, and status signals S, D become busy when data is sent to prevent double writing. When serial data is written to the serial buffer 4.6, the status signals a and c become busy signals, and the data D12. When D22 is read, it becomes ready.

For example, when transferring data from the first microprocessor 1 to the second microprocessor 2, data Dll from the logic processing unit 8 is set in the serial buffer 5 and sent from the serial output port SO. The second microprocessor 2 detects the start bit of the serial data added to the interrupt port IRQ and applies a start signal to the counter 3 from the start control port SR.

Thereby, the counter 3 starts counting the clock signal CKI and outputs the clock signal CK2. This clock signal CK2 is applied to the serial buffer 6 from the serial clock port SC, and the received serial data is written into the serial buffer 6. By writing one word, the status signal C becomes busy and the counting operation of the counter 3 is stopped. The received data D22 is then output and transferred to the logic processing section 9 of the microprocessor 2.

When transferring data from the microprocessor 2 of the writing device 2 to the first microprocessor 1, data D21 to which a start bit and a stop bit have been added is set in the serial buffer 7, the status signal d is set to a busy state, and the counter Start 3. Upon activation of the counter 3, the clock signal CK2 is applied to the serial buffer 7, and serial data is output from the serial output port SO. Then, the counting operation of the counter 3 is stopped by sending out one word. The first microprocessor 1 samples the received serial data using the clock signal CKI, detects a start bit and a stop bit, and transfers data D12 between them from the serial buffer 4 to the internal logic processing unit 8.

FIG. 3 is an explanatory diagram of the operation, and shows the case where serial data is transferred from the first microprocessor 1 to the second microprocessor 2. (a) is the serial data, ST is the start bit, and BO ~B7 are data bits of 8-bit configuration, and SP is a stop bit.

Further, (b) shows the clock signal CK1 of the first microprocessor 1, (C) shows the activation control signal of the counter 3, and (d) shows the clock signal CK2 generated by the counter 3. For example, when the clock signal CK1 is It is formed by dividing the frequency by 1/16 by 3. Also, (e) shows the contents of the serial buffer 6 of the second microprocessor 2, and (f) shows the status signal C1 (of the serial buffer 6).
phantom indicates the status signal of the serial buffer 5.

In the serial buffer 5 of the first microprocessor 1,
When the data shown in FIG. 3(a) is set, the status signal becomes busy (as shown in the figure, the set data is sent from the serial buffer 5, and a stop beep occurs). When the sending of SP is completed, , become a lady. The data shown in (a) is sent from this serial buffer 5 to the serial input port S of the second microprocessor 2.
I and interrupt baud) added to IRQ and start bit S
When T is detected, the counter 3 is activated by the activation control signal shown in (C), and the clock signal CK2 is applied to the serial clock port SC as shown in (dl), and the received data is transferred to the serial buffer according to this clock signal CK2. 6. Upon reception of 8 bits BO to B7, the operation of counter 3 is stopped by the activation control signal.
Since the generation of the clock signal CK2 is stopped, the contents of the serial buffer 6 become as shown in (81).
The status signal C shown in If) of the serial buffer 6 becomes full, and when the data D22 is transferred from the serial buffer 6 to the logic processing section or the like, the status signal C becomes empty.

FIG. 4 is an explanatory diagram of the operation when data is transferred from the second microprocessor 2 to the first microprocessor 1, and the data D21 shown in (A) is set in the serial buffer 7 of the second microprocessor 2. Then, the status signal d changes from ready to busy as shown in FIG. 4(C), the counter 3 is activated by the activation control signal shown in FIG. 4(D), and the clock signal CK2 shown in FIG. It is added to the serial buffer 7 from port SC. As a result, serial data is sent from the serial output port SO of the second microprocessor 2. Upon completion of sending one word, the operation of the counter 3 is stopped, and the status signal d of the serial buffer 7 becomes ready.

The first microprocessor 1 samples and identifies the data received at the serial input port S using the clock signal CK1, and when it detects the start bit ST, writes the next bits BO to B7 into the serial buffer 4. become. Then, the status of the serial buffer 4 (number i a changes from empty to full as shown in (E) in FIG. 4), and the data D12 is transferred to the logic processing unit 8 and the like.

In the embodiment described above, a case is shown in which serial transfer is performed in units of 10 bits including a start bit and a stop bit, but transfer can be performed in units of any number of bits. It can also be applied to cases where the processing bit widths are different, such as communication between an 8-bit microprocessor and a 4-bit microprocessor.

〔Effect of the invention〕

As explained above, the present invention forms a clock signal at a serial data transfer rate by synchronizing mutual clock signals by the counting means (counter) 3 even between microprocessors using different serial communication systems. Since it is possible to transfer serial data using a serial port, it does not require a conventional buffer memory, resulting in an economical configuration. Furthermore, by using a serial port to communicate between microprocessors, it is possible to allocate a parallel port for controlling other peripheral devices, which has the advantage of making effective use of the port.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Figs. 3 and 4 are explanatory diagrams of operation, Fig. 5 is a block diagram of a conventional example, and Fig. 6 is a block diagram of an embodiment of the present invention. It is a conventional operation explanatory diagram. 1 is a first microprocessor, 2 is a second microprocessor, 3 is a counter, 4 to 7 are serial buffers,
8.9 is the logic processing section, Sl is the serial input port, SO
is a serial output port, SC is a serial clock port, IRQ is an interrupt port, and SR is a startup control port.

Claims (1)

[Scope of Claims] A clock signal of the first microprocessor is connected between a first microprocessor (1) having an asynchronous serial port and a second microprocessor (2) having a synchronous serial port. counting means (3) for counting and creating a clock signal for the second microprocessor;
wherein the second microprocessor (2) activates the counting means (3) and processes the serial data from the first microprocessor (1) according to the clock signal formed by the counting means (3). and the first microprocessor (1) identifies the reception of the serial data from the second microprocessor (2) by multi-point sampling according to the clock signal of the microprocessor. Interprocessor communication method.