JP2573561B2 - High density memory device - Google Patents
High density memory deviceInfo
- Publication number
- JP2573561B2 JP2573561B2 JP60071412A JP7141285A JP2573561B2 JP 2573561 B2 JP2573561 B2 JP 2573561B2 JP 60071412 A JP60071412 A JP 60071412A JP 7141285 A JP7141285 A JP 7141285A JP 2573561 B2 JP2573561 B2 JP 2573561B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- transistor
- density memory
- mis
- dielectric film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 230000005260 alpha ray Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Landscapes
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は１個のMISトランジスタ（絶縁ゲート型電界
効果トランジスタ）と１個のキャパシタからなる１トラ
ンジスタ型MISダイナミックメモリの高密度メモリ素子
に関する。Description: TECHNICAL FIELD The present invention relates to a high-density memory element of a one-transistor MIS dynamic memory including one MIS transistor (insulated gate field effect transistor) and one capacitor.
（従来技術とその問題点） １トランジスタ型MISダイナミックメモリは、大容量
メモリとして広く用いられているが、アルファ線による
ソフトエラー対策の必要上、キャパシタに蓄積する電荷
量を30〜60fC以下に下げられない。このために、１メガ
ビットメモリでは、溝堀りキャパシタ等が用いられてい
るが、この構造は、アルファ線に当る面積が大となるの
で、本質的にアルファ線のソフトエラーに対して弱いと
考えられる。(Prior art and its problems) The one-transistor MIS dynamic memory is widely used as a large-capacity memory, but the amount of charge stored in the capacitor is reduced to 30 to 60 fC or less due to the need for countermeasures against soft errors by alpha rays. I can't. For this reason, a trench capacitor or the like is used in a 1-Mbit memory, but since this structure has a large area corresponding to an alpha ray, it is considered to be essentially vulnerable to a soft error of the alpha ray. Can be
さらに、キャパシタの誘電体膜として強誘電体を用い
ることも考えられるけれども、強誘電体はキュリー温度
以下においては、分極現象を伴うヒステリシス特性を有
しており誘電率が変るので安定性などに問題の生じるこ
とが考えられる。Furthermore, although it is conceivable to use a ferroelectric as the dielectric film of the capacitor, the ferroelectric has a hysteresis characteristic accompanied by a polarization phenomenon below the Curie temperature, and the dielectric constant changes. Can occur.
（発明の目的） 本発明の目的は、上記問題点を解消することにより、
アルファ線のソフトエラーが起りにくく、且つ安定に動
作し、高密度に集積可能な構造を有する１トランジスタ
型MISダイナミックメモリ用の高密度メモリ素子を提供
することにある。(Object of the Invention) The object of the present invention is to solve the above problems,
An object of the present invention is to provide a high-density memory element for a one-transistor MIS dynamic memory having a structure in which a soft error of alpha rays hardly occurs, operates stably, and can be integrated at a high density.
（発明の構成） 本発明の高密度メモリ素子は、１トランジスタ型MIS
メモリ素子の電荷を蓄積するキャパシタの誘電体膜に反
強誘電体又はキュリー点が室温よりも低い強誘電体を用
いたことからなっている。(Structure of the Invention) The high-density memory device of the present invention is a one-transistor type MIS.
This is because an antiferroelectric substance or a ferroelectric substance having a Curie point lower than room temperature is used for a dielectric film of a capacitor for storing charges of a memory element.
（実施例） 以下、本発明の実施例について図面を参照して説明す
る。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ）はそれぞれ本発明の第１の実施
例を示す断面図及び平面図である。1 (a) and 1 (b) are a sectional view and a plan view, respectively, showing a first embodiment of the present invention.
第１図（ａ），（ｂ）において、11はＰ型シリコン基
板、12はキャパシタの誘電体膜、13は１層目のポリシリ
コンからなるキャパシタ電極、14は選択トランジスタの
ゲート酸化膜、15は２層目のポリシリコンからなる選択
トランジスタのゲート電極、16はワード線となるAl配線
で、コンタクト17によりトランジスタのゲート電極15に
接続される。18は選択トランジスタのドレインとしての
N+型拡散層でビット線となる。19は層間絶縁膜である。1 (a) and 1 (b), 11 is a P-type silicon substrate, 12 is a dielectric film of a capacitor, 13 is a capacitor electrode made of first-layer polysilicon, 14 is a gate oxide film of a selection transistor, 15 Is a gate electrode of a selection transistor made of second-layer polysilicon, 16 is an Al wiring serving as a word line, and is connected to a gate electrode 15 of the transistor through a contact 17. 18 is the drain of the select transistor
It becomes a bit line in the N + type diffusion layer. 19 is an interlayer insulating film.
誘電体膜12としては、反強誘電体又は、キュリー温度
Tcが常温より低い強誘電体を用いる。As the dielectric film 12, an antiferroelectric material or a Curie temperature
A ferroelectric whose Tc is lower than room temperature is used.
ここで、反強誘電体としては、PbZrO3，Pb1-xBaxZrO3
（ｘ＝0.01〜0.99）その他がある。又、キュリー温度Tc
が室温附近より低い強誘電体としては、Cd2NO2O7，KH2P
O4，KH2AsO4，PbH2PO4，KTaO3，KD2PO4，Pb1-xBxTiO
3（ｘ＝０〜0.6）等がある。以下の実施例でも同じであ
る。Here, the anti-ferroelectric, P b Z r O 3, P b1-x B ax Z r O 3
(X = 0.01 to 0.99) Others are available. Curie temperature Tc
C d2 NO 2 O 7 , KH 2 P
O 4, KH 2 A s O 4, P b H 2 PO 4, KT a O 3, KD 2 PO 4, P b1-x B x T i O
3 (x = 0 to 0.6). The same applies to the following embodiments.
第２図（ａ），（ｂ）は本発明の第２の実施例を示す
断面図及び平面図である。2A and 2B are a sectional view and a plan view showing a second embodiment of the present invention.
第２図（ａ），（ｂ）において、21はＰ型シリコン基
板、22はキャパシタの誘電体膜、23aは２層目ポリシリ
コンからなるキャパシタ電極でコンタクト27bを介して
選択トランジスタのソースとなるN+型拡散層28bに接続
される。23bは３層目ポリシリコンからなるキャパシタ
電極、24は選択トランジスタのゲート酸化膜、25は１層
目ポリシリコンからなる選択トランジスタのゲート電極
でワード線に接続される。26はAl配線でビット線として
コンタクト27aを介して選択トランジスタのドレインと
なるN+型拡散層28aに接続される。29は層間絶縁膜であ
る。2 (a) and 2 (b), reference numeral 21 denotes a P-type silicon substrate, 22 denotes a dielectric film of a capacitor, and 23a denotes a capacitor electrode made of second-layer polysilicon, which is a source of a selection transistor via a contact 27b. Connected to N + type diffusion layer 28b. 23b is a capacitor electrode made of third-layer polysilicon, 24 is a gate oxide film of a selection transistor, and 25 is a gate electrode of a selection transistor made of first-layer polysilicon, which is connected to a word line. Reference numeral 26 denotes an Al wiring, which is connected as a bit line to an N + -type diffusion layer 28a serving as a drain of a selection transistor via a contact 27a. 29 is an interlayer insulating film.
（発明の効果） 以上、説明したように、本発明で、キャパシタの誘電
体膜として用いる反強誘電体は、例えば、PbZrO3は室温
における比誘電率が約80であり、従来のSiO2の約3.5に
対して20倍以上の値を持ち、しかも強誘電体のようなヒ
ステリシス特性が無い点に特徴があり、高密度メモリキ
ャパシタ用材料として好適である。(Effect of the Invention) As described above, in the present invention, the antiferroelectric used as the dielectric film of the capacitor, for example, P b Z r O 3 is the relative dielectric constant of about 80 at room temperature, conventional It has about 3.5 value of more than 20 times the of S i O 2 of, yet there is a point in feature hysteresis characteristic is not such a ferroelectric, is suitable as a high-density memory capacitor material.
又、キュリー温度Tc以上の温度Ｔにおける強誘電体の
誘電率εは で与えられるが、定数Ｃの値が大きいため、Ｔ＞＞Tcの
温度の場合でも大きなεの値を保持する。そこで、キュ
リー温度が室温よりも低い強誘電体を用いることによ
り、実質的にヒステリシス特性が無く、しかも高い誘電
率が得られる。例えば、KH2PO4はTc＝−150℃で、室温
における比誘電率は約40であり、従来のSiO2の約10倍以
上の値を持っている。Further, the dielectric constant ε of the ferroelectric at the temperature T equal to or higher than the Curie temperature Tc is However, since the value of the constant C is large, a large value of ε is maintained even at a temperature of T >> Tc . Therefore, by using a ferroelectric substance whose Curie temperature is lower than room temperature, substantially no hysteresis characteristics can be obtained and a high dielectric constant can be obtained. For example, KH 2 PO 4 at T c = -150 ° C., relative dielectric constant at room temperature is about 40, has a conventional value of about 10 or more times the S i O 2.
従って、本発明によれば、メモリセルの面積を大きく
することなく、キャパシタの容量を格段に大きくするこ
とができ、かつ強誘電体を用いた場合問題と考えられる
ヒステリシス特性に基づく不安定性が無いので、アルフ
ァ線のソフトエラーが起りにくく、且つ安定に動作し、
高密度に集積可能な構造を有する１トランジスタ型MIS
ダイナミックメモリ用の高密度メモリ素子が得られる。Therefore, according to the present invention, the capacity of the capacitor can be significantly increased without increasing the area of the memory cell, and there is no instability based on the hysteresis characteristic which is considered to be a problem when a ferroelectric is used. Therefore, alpha error is less likely to occur, and it operates stably.
One-transistor MIS with a structure that can be integrated at high density
A high-density memory element for a dynamic memory can be obtained.
第１図（ａ），（ｂ）はそれぞれ本発明の第１の実施例
を示す断面図及び平面図、第２図（ａ），（ｂ）はそれ
ぞれ本発明の第２の実施例を示す断面図及び平面図であ
る。 11……Ｐ型シリコン基板、12……誘電体膜、13……キャ
パシタ電極、14……ゲート酸化膜、15……ゲート電極、
16……Al配線、17……コンタクト、18……N+型拡散層、
19……層間絶縁膜、21……Ｐ型シリコン基板、22……誘
電体膜、23a,23b……キャパシタ電極、24……ゲート酸
化膜、25……ゲート電極、26……Al配線、27a,27b……
コンタクト、28a,28b……N+型拡散層、29……層間絶縁
膜。FIGS. 1 (a) and 1 (b) are a cross-sectional view and a plan view, respectively, showing a first embodiment of the present invention, and FIGS. 2 (a), (b) show a second embodiment of the present invention, respectively. It is sectional drawing and a top view. 11 ... P-type silicon substrate, 12 ... Dielectric film, 13 ... Capacitor electrode, 14 ... Gate oxide film, 15 ... Gate electrode,
16 ... Al wiring, 17 ... Contact, 18 ... N + type diffusion layer,
19 ... interlayer insulating film, 21 ... P-type silicon substrate, 22 ... dielectric film, 23a, 23b ... capacitor electrode, 24 ... gate oxide film, 25 ... gate electrode, 26 ... Al wiring, 27a , 27b ……
Contact, 28a, 28b ... N + type diffusion layer, 29 ... Interlayer insulating film.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭57−45968（ＪＰ，Ａ) 特開 昭55−108726（ＪＰ，Ａ) 「Ｆｅｒｒｏｅｌｅｃｔｒｉｃｓ」５ （1973）Ｇｏｒｄｏｎ ａｎｄ Ｂｒｅ ａｃｈ Ｓｃｉｅｎｃｅ Ｐｕｂｌｉｓ ｈｅｒｓ Ｌｔｄ．Ｐ267−280 「誘電体」1991−６−15（株）培風館 「強誘電体と構造相転移」1989−４− 25（株）裳華房 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-45968 (JP, A) JP-A-55-108726 (JP, A) "Ferroelectrics" 5 (1973) Gordon and Breakach Science Publishing Ltd. P267-280 “Dielectrics” 1991-6-15 Baifukan Co., Ltd. “Ferroelectrics and structural phase transitions” 1989-4-25 Shokabo Co., Ltd.
Claims (2)
タからなる１トランジスタ型MISメモリ素子の電荷を蓄
積する前記キャパシタの誘電体膜に反強誘電体を用いた
ことを特徴とする高密度メモリ素子。1. A high-density memory, wherein an antiferroelectric material is used for a dielectric film of a one-transistor type MIS memory element comprising one MIS transistor and one capacitor for storing electric charges. element.
タからなる１トランジスタ型MISメモリ素子の電荷を蓄
積する前記キャパシタの誘電体膜にキュリー点が室温よ
りも低い強誘電体を用いたことを特徴とする高密度メモ
リ素子。2. The method according to claim 1, wherein a ferroelectric material having a Curie point lower than room temperature is used for a dielectric film of the one-transistor type MIS memory element comprising one MIS transistor and one capacitor for storing charges. High-density memory element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60071412A JP2573561B2 (en) | 1985-04-04 | 1985-04-04 | High density memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60071412A JP2573561B2 (en) | 1985-04-04 | 1985-04-04 | High density memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61229350A JPS61229350A (en) | 1986-10-13 |
| JP2573561B2 true JP2573561B2 (en) | 1997-01-22 |
Family
ID=13459776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60071412A Expired - Lifetime JP2573561B2 (en) | 1985-04-04 | 1985-04-04 | High density memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2573561B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4873664A (en) * | 1987-02-12 | 1989-10-10 | Ramtron Corporation | Self restoring ferroelectric memory |
| EP0293798B2 (en) | 1987-06-02 | 1998-12-30 | National Semiconductor Corporation | Non-volatile memory ciruit using ferroelectric capacitor storage element |
| JP3169599B2 (en) | 1990-08-03 | 2001-05-28 | 株式会社日立製作所 | Semiconductor device, driving method thereof, and reading method thereof |
| WO2009128133A1 (en) * | 2008-04-14 | 2009-10-22 | 富士通株式会社 | Antiferroelectric gate transistor and manufacturing method thereof, and non-volatile memory element |
| JP5690207B2 (en) * | 2011-05-11 | 2015-03-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US11889701B2 (en) | 2021-04-22 | 2024-01-30 | Globalfoundries U.S. Inc. | Memory cell including polarization retention member(s) including antiferroelectric layer over ferroelectric layer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745968A (en) * | 1980-08-29 | 1982-03-16 | Ibm | Capacitor with double dielectric unit |
-
1985
- 1985-04-04 JP JP60071412A patent/JP2573561B2/en not_active Expired - Lifetime
Non-Patent Citations (3)
| Title |
|---|
| 「Ｆｅｒｒｏｅｌｅｃｔｒｉｃｓ」５（１９７３）Ｇｏｒｄｏｎ ａｎｄ Ｂｒｅａｃｈ Ｓｃｉｅｎｃｅ Ｐｕｂｌｉｓｈｅｒｓ Ｌｔｄ．Ｐ２６７−２８０ |
| 「強誘電体と構造相転移」１９８９−４−２５（株）裳華房 |
| 「誘電体」１９９１−６−１５（株）培風館 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61229350A (en) | 1986-10-13 |
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