JPH0451564A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0451564A JPH0451564A JP2160304A JP16030490A JPH0451564A JP H0451564 A JPH0451564 A JP H0451564A JP 2160304 A JP2160304 A JP 2160304A JP 16030490 A JP16030490 A JP 16030490A JP H0451564 A JPH0451564 A JP H0451564A
- Authority
- JP
- Japan
- Prior art keywords
- film
- grown
- electrode
- forming
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 13
- 239000010937 tungsten Substances 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 23
- 210000004027 cell Anatomy 0.000 description 5
- 230000015654 memory Effects 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
ＤＲＡＭ （ダイナミックランダムアクセスメモリ）の
記憶セル等のキャパシタを有する半導体装置とその製造
方法に関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor device having a capacitor, such as a storage cell of a DRAM (dynamic random access memory), and a method for manufacturing the same.
簡単なスタック構造のまま容量を増大させ、ソフトエラ
ーの低減を目的とし。The purpose is to increase capacity while maintaining a simple stack structure and reduce soft errors.
１）少なくとも表面にタングステンが露出し、該表面に
凹凸が形成されている下層電極と、該下層電極表面に重
ねて形成され１表面に凹凸を有する誘電体膜と、該誘電
体膜表面に重ねて形成され。1) A lower electrode having at least exposed tungsten on the surface and having an uneven surface, a dielectric film formed over the lower electrode surface and having an uneven surface, and a dielectric film overlapping the surface of the dielectric film. formed by
該下層電極とは電気的に直接接しない上層電極とを有す
るように構成する。It is configured to have an upper layer electrode that is not in direct electrical contact with the lower layer electrode.
２）素子形成面に、少なくとも表面にタングステンが露
出し、該表面に凹凸が形成されるように下層電極を形成
する工程と、該下層電極表面に重ね。2) forming a lower layer electrode on the element forming surface so that tungsten is exposed at least on the surface and unevenness is formed on the surface; and overlapping the lower layer electrode surface.
かつ表面に凹凸を有してなるように、誘電体膜を形成す
る工程と、該誘電体膜表面に重ね、かつ該下層配線とは
電気的に直接接しないように上層電極を形成する工程と
を有するように構成する。and a step of forming a dielectric film so as to have an uneven surface, and a step of forming an upper layer electrode so as to overlap the surface of the dielectric film and not be in direct electrical contact with the lower layer wiring. It is configured to have the following.
３）前記下層電極を形成する工程が、前記素子形成面上
にポリシリコン膜（１７）とタングステン膜（１８）と
第２のポリシリコン膜を順に成長して下層電極を形成す
るように構成する。3) The step of forming the lower electrode is configured such that the lower electrode is formed by sequentially growing a polysilicon film (17), a tungsten film (18), and a second polysilicon film on the element formation surface. .
４）前記下層電極を形成する工程が、前記素子形成面上
にタングステン膜（１８）を成長して下層電極を形成す
るように構成する。4) The step of forming the lower layer electrode is configured such that a tungsten film (18) is grown on the element forming surface to form the lower layer electrode.
〔産業上の利用分野）
本発明はＤＲＡＭの記憶セルのキャパシタを有する半導
体装置とその製造方法乙こ関する。[Industrial Application Field] The present invention relates to a semiconductor device having a capacitor of a DRAM memory cell and a method for manufacturing the same.
最近の半導体メモリにおいては、高集積化のために微細
化が要求されている。In recent semiconductor memories, miniaturization is required for higher integration.
ＤＲＡＭの記憶セルは、記憶容量の大規模化りこともな
いピント当たりのセル面積が小さくかつ記憶保持、読出
に十分な電荷を蓄積できる静電容量の大きいキャパシタ
構造が求められている。A DRAM memory cell is required to have a capacitor structure that has a small cell area per focus without increasing the storage capacity and has a large capacitance that can store sufficient charge for memory retention and readout.
本発明はこの要求に対応した記憶セルのキャパシタ構造
として利用できる。The present invention can be used as a capacitor structure for a memory cell that meets this requirement.
第２図は従来例によるキャパシタを説明する断面図であ
る。FIG. 2 is a sectional view illustrating a conventional capacitor.
図において、 １１は半導体基板、１２は分離酸化膜。In the figure, 11 is a semiconductor substrate, and 12 is an isolation oxide film.
１３、１４はソースドレイン領域、１５はワードライン
（ゲート） 、 １６．２１は眉間絶縁膜、１７は蓄積
電極。13 and 14 are source/drain regions, 15 is a word line (gate), 16.21 is an insulating film between the eyebrows, and 17 is a storage electrode.
１９は誘電体膜、 ２０は対向電極、２２はピントライ
ン。19 is a dielectric film, 20 is a counter electrode, and 22 is a focus line.
２３はカバー絶縁膜である。23 is a cover insulating film.
図のようるこ蓄積電極１７を覆って誘電体膜１９を介し
対向電極２０が重ねられてキャパシタを構成している。As shown in the figure, a counter electrode 20 is stacked over the storage electrode 17 with a dielectric film 19 in between to form a capacitor.
セル面積を小さくして、キャパシタの容量を増やすには
、蓄積電極の表面積を大きくすることが重要である。In order to reduce the cell area and increase the capacitance of the capacitor, it is important to increase the surface area of the storage electrode.
従って、これ以上に容量を増加させるためには複雑なス
タック構造をとる必要がある。Therefore, in order to further increase the capacity, it is necessary to adopt a complicated stack structure.
そのために１キヤパシタはトレンチやフィン構造のスタ
ックのような３次元構造をとってキャパシタ面積を大き
くして容量を確保していた。For this purpose, one capacitor has a three-dimensional structure such as a stack of trenches or fin structures to increase the area of the capacitor and secure the capacitance.
そこで１本発明は現状の簡単なスタック構造のまま容量
を増大させ、ソフトエラーを低減することを目的とする
。Therefore, one object of the present invention is to increase the capacity while keeping the current simple stack structure and reduce soft errors.
上記課題の解決は。 What is the solution to the above problem?
ｌ）少なくとも表面にタングステンが露出し、該表面に
凹凸が形成されている下層電極と、該下層電極表面に重
ねて形成され１表面に凹凸を有する誘電体膜と、該誘電
体膜表面に重ねて形成され。l) a lower layer electrode on which tungsten is exposed at least on the surface and has an uneven surface; a dielectric film formed over the lower electrode surface and having unevenness on one surface; formed by
該下層電極とは電気的に直接接しない上層電極とを有す
る半導体装置、あるいは
２）素子形成面に、少なくとも表面にタングステンが露
出し２．該表面に凹凸が形成されるように下層電極を形
成する工程と、該下層電極表面に重ね。A semiconductor device having an upper layer electrode that is not in direct electrical contact with the lower layer electrode, or 2) Tungsten is exposed at least on the surface of the element forming surface. forming a lower layer electrode so that irregularities are formed on the surface; and overlapping the lower layer electrode surface.
かつ表面に凹凸を有してなるように、誘電体膜を形成す
る工程と、該誘電体膜表面に重ね、かつ該下層配線とは
電気的に直接接しないように上層電極を形成する工程と
を有する半導体装置の製造方法、あるいは
３）前記下層電極を形成する工程が、前記素子形成面上
にポリシリコン膜（１７）とタングステン膜（１８）と
第２のポリシリコン膜を順に成長して下層電極を形成す
る前記２）記載の半導体装置の製造方法、あるいは
４）前記下層電極を形成する工程が、前記素子形成面上
にタングステン膜（１８）を成長して下層電極を形成す
る前記２）記載の半導体装置の製造方法により達成され
る。and a step of forming a dielectric film so as to have an uneven surface, and a step of forming an upper layer electrode so as to overlap the surface of the dielectric film and not be in direct electrical contact with the lower layer wiring. or 3) the step of forming the lower electrode comprises sequentially growing a polysilicon film (17), a tungsten film (18) and a second polysilicon film on the element formation surface. The method for manufacturing a semiconductor device according to 2) above, in which a lower layer electrode is formed; This can be achieved by the method for manufacturing a semiconductor device described in ).
（作用〕
本発明は蓄積電極として凹凸のあるタングステン（り膜
（元来、気相成長したに膜の表面はポリシリコン膜より
凹凸が大きく形成されているが。(Function) The present invention uses an uneven tungsten film (originally, the surface of a vapor-phase grown film is formed with larger unevenness than a polysilicon film) as a storage electrode.
とくに凹凸を強調して成長することもできる）を成長し
、その上に誘電体膜、対向電極となる導電膜を成長して
キャパシタを形成することにより。In particular, by growing a dielectric film (which can be grown with emphasis on the unevenness) and then growing a dielectric film and a conductive film that will become a counter electrode on top of it, a capacitor is formed.
キャパシタ面積を増加させて容量の増大をはかったもの
である。The capacitor area is increased to increase the capacitance.
さらに、Ｗ膜とその上に形成する誘電体膜との接着性を
向上するため、−膜の凹凸面に沿って薄く第２のポリシ
リコン膜を成長し、その上に誘電体膜を成長するとキャ
パシタ形成が一層容易となる。Furthermore, in order to improve the adhesion between the W film and the dielectric film formed on it, a second polysilicon film is grown thinly along the uneven surface of the film, and a dielectric film is grown on top of it. Capacitor formation becomes easier.
第１図（ａ）〜（ｄ）は実施例を工程１唾に説明する断
面図である。FIGS. 1(a) to 1(d) are cross-sectional views illustrating the embodiment in step 1.
第１ｅ（ａ）において、半導体基板としてｐ型シリコン
（ｐ−３ｉ）基板１１の素子分離領域に分離絶縁膜１２
を形成し５選択トランジスタのワードライン１５及びソ
ースドレイン領域１３．１４を形成する。In 1e(a), an isolation insulating film 12 is provided in an element isolation region of a p-type silicon (p-3i) substrate 11 as a semiconductor substrate.
A word line 15 and source/drain regions 13 and 14 of five selection transistors are formed.
その上に、気相成長の二酸化シリコン
（ＣＶＤ ＳｉＯ□）膜１６を成長し、この膜に蓄積電
極接続用のストレージコンタクトホールＳＣを開口する
。A vapor phase grown silicon dioxide (CVD SiO□) film 16 is grown thereon, and a storage contact hole SC for connecting the storage electrode is opened in this film.
次いで、上記の開口を覆って厚さ１０００人のポリシリ
コン膜１７を成長し、この上に厚さ５００人の凹凸面を
有する警膜１８を成長する。Next, a polysilicon film 17 with a thickness of 1,000 wafers is grown to cover the above-mentioned opening, and a protective film 18 having an uneven surface with a thickness of 500 wafers is grown thereon.
この場合、ポリシリコンの成長条件は１反応ガスとして
ＳｉＨ４を用い、これを０．Ｉ Ｔｏｒｒに減圧した雰
囲気中で基板温度を６２５”Ｃにして行う。In this case, the growth conditions for polysilicon are as follows: SiH4 is used as a reactive gas, and SiH4 is used as a reaction gas. The substrate temperature is 625''C in an atmosphere reduced to I Torr.
この場合、ｔｌｌの成長条件は９反応ガスとしてＷＦ６
． ｔ（ｚ＋ （ＳｉＨ４）を用い、これを０．Ｉ Ｔ
ｏｒｒに減圧した雰囲気中で基板温度を３００〜４５０
°Ｃにして行う。In this case, the growth conditions for tll are WF6 as 9 reactant gas.
．． t(z+ (SiH4)) and convert it to 0.I T
The substrate temperature is set to 300 to 450 in an atmosphere reduced to orr.
Perform at °C.
この際、Ｗ膜の表面を凹凸にするためには、誉膜の成長
を水素還元反応により高温（４００〜４５０’Ｃ）で行
うようにする。At this time, in order to make the surface of the W film uneven, the growth of the honor film is performed at a high temperature (400 to 450'C) by a hydrogen reduction reaction.
第１図（ｂ）において、これらの膜、匈膜１８とポリシ
リコン膜１７をパターニングして蓄積電極（下層電極）
を形成する。In FIG. 1(b), these films, the hoop film 18 and the polysilicon film 17, are patterned to form a storage electrode (lower layer electrode).
form.
次いで、基板上全面に誘電体膜として厚さ７０人の気相
成長の窒化シリコン（ＣＶＤ ５ｉＪ４） Ｆ１１９と
対向電極として厚さ１０００人のポリシリコン膜２０を
成長する。Next, a dielectric film of silicon nitride (CVD 5iJ4) F119 with a thickness of 70 wafers is grown on the entire surface of the substrate, and a polysilicon film 20 with a thickness of 1000 wafers is grown as a counter electrode.
この場合、 Ｓｉ３Ｎ４の成長条件は５反応ガスとして
５ｉＨｚＣ１２（または５ｉＨＣｂ） とＮＨ，を用
い、これをＩ Ｔｏｒｒに減圧した雰囲気中で基板温度
を７７５°Ｃにして行う。In this case, the growth conditions for Si3N4 are as follows: 5iHzC12 (or 5iHCb) and NH are used as reaction gases, and the substrate temperature is 775°C in an atmosphere reduced to I Torr.
第１図（Ｃ）において、ポリシリコン膜２０をパターニ
ングして対向電極（上層電極）とし、その上に層間絶縁
膜としてＣＶＤ ＳｉＯ□膜２１を成長し、ビットライ
ン用のコンタクトホールＢＣを形成する。In FIG. 1(C), the polysilicon film 20 is patterned to form a counter electrode (upper layer electrode), and a CVD SiO□ film 21 is grown thereon as an interlayer insulating film to form a contact hole BC for a bit line. .
第１図（ｄ）において、 ＡＩ膜でビットライン２２を
形成し、その上にカバー絶縁膜としてりん珪酸ガラス（
ＰＳＧ）膜２３を成長する。In FIG. 1(d), a bit line 22 is formed with an AI film, and phosphosilicate glass (
PSG) film 23 is grown.
実施例では、第１図（ａ）において、ポリシリコン膜１
７とＷ Ｍ１８を全面成長してパターニングしたが。In the example, in FIG. 1(a), a polysilicon film 1
7 and WM18 were grown on the entire surface and patterned.
ポリシリコン膜１７を先にパターニングして誓膜１８を
その上に選択成長してもよい。It is also possible to pattern the polysilicon film 17 first and then selectively grow the film 18 thereon.
また、実施例では凹凸面を持つ讐膜１８の上に直かにＳ
ｉ３Ｎ、膜１９を成長したが、 Ｓｉ：＋Ｎａ膜とＷ膜
の接着性をよくするために、これらの層の間に厚さ金属
度の第２のポリシリコン膜を介在させてもよい。In addition, in the embodiment, the S
Although the i3N film 19 was grown, in order to improve the adhesion between the Si:+Na film and the W film, a second polysilicon film having a metallic thickness may be interposed between these layers.
また、実施例ではり膜１８の下側全面にポリシリコン膜
１７を敷いたが、−膜１８だけで蓄積電極を形成しても
よい。ただし、この場合は基板とのコンタクト部のみに
誓とＳｉの反応阻止層としてポリシリコン膜を敷くのが
望ましい。Furthermore, although the polysilicon film 17 is spread over the entire lower surface of the peel-off film 18 in the embodiment, the storage electrode may be formed using only the - film 18. However, in this case, it is desirable to lay a polysilicon film as a reaction blocking layer between silicon and Si only in the contact portion with the substrate.
以上説明したように本発明によれば、現状の簡単なスタ
ック構造のまま、容量を増大させることができる。As described above, according to the present invention, the capacity can be increased while maintaining the current simple stack structure.
この結果、 ＤＲＡＭの放射線によるソフトエラーが低
減できる。As a result, soft errors caused by radiation in the DRAM can be reduced.
第１図（ａ）〜（ｄ）は実施例を工程順に説明する断面
図である。
第２図は従来例によるキャパシタを説明する断面図であ
る。
図おいて。
１１は半導体基板。
１２は分離酸化膜。
１３、１４はソースドレイン領域。
１５はワードライン（ゲート）。
１６、２１は層間絶縁膜。
１７は蓄積電極（下層電極）でポリシリコン膜。
１８は蓄積電極（下層電極）で
凹凸面を有する一膜。
１９は誘電体膜。
２０は対向電極（上層電極）。
２２はビットライン。
２３はカバー絶縁膜である。
実ａａｑの断面図
第 １ ｌFIGS. 1(a) to 1(d) are cross-sectional views illustrating an embodiment in the order of steps. FIG. 2 is a sectional view illustrating a conventional capacitor. In the diagram. 11 is a semiconductor substrate. 12 is an isolation oxide film. 13 and 14 are source and drain regions. 15 is a word line (gate). 16 and 21 are interlayer insulating films. 17 is a storage electrode (lower layer electrode), which is a polysilicon film. 18 is a storage electrode (lower layer electrode), which is a film having an uneven surface. 19 is a dielectric film. 20 is a counter electrode (upper layer electrode). 22 is the bit line. 23 is a cover insulating film. Cross section of actual aaq 1st l
Claims (4)
に凹凸が形成されている下層電極と、 該下層電極表面に重ねて形成され、表面に凹凸を有する
誘電体膜と、 該誘電体膜表面に重ねて形成され、該下層電極とは電気
的に直接接しない上層電極 とを有することを特徴とする半導体装置(1) A lower layer electrode on which tungsten is exposed at least on the surface and has an uneven surface; a dielectric film formed over the surface of the lower electrode and having an uneven surface; and a dielectric film on the surface of the dielectric film. A semiconductor device characterized by having an upper layer electrode that is formed in an overlapping manner and is not in direct electrical contact with the lower layer electrode.
露出し、該表面に凹凸が形成されるように下層電極を形
成する工程と、 該下層電極表面に重ね、かつ表面に凹凸を有してなるよ
うに、誘電体膜を形成する工程と、該誘電体膜表面に重
ね、かつ該下層配線とは電気的に直接接しないように上
層電極を形成する工程 とを有することを特徴とする半導体装置の製造方法。(2) a step of forming a lower electrode on the element formation surface so that tungsten is exposed at least on the surface and unevenness is formed on the surface; and overlapping the lower electrode surface and having unevenness on the surface A semiconductor device comprising the steps of forming a dielectric film, and forming an upper layer electrode so as to overlap the surface of the dielectric film and not be in direct electrical contact with the lower layer wiring. manufacturing method.
上にポリシリコン膜（１７）とタングステン膜（１８）
と第２のポリシリコン膜を順に成長して下層電極を形成
することを特徴とする請求項２記載の半導体装置の製造
方法。(3) In the step of forming the lower electrode, a polysilicon film (17) and a tungsten film (18) are formed on the element forming surface.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the lower electrode is formed by sequentially growing the first polysilicon film and the second polysilicon film.
上にタングステン膜（１８）を成長して下層電極を形成
することを特徴とする請求項２記載の半導体装置の製造
方法。(4) The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the lower electrode comprises growing a tungsten film (18) on the element forming surface to form the lower electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160304A JPH0451564A (en) | 1990-06-19 | 1990-06-19 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160304A JPH0451564A (en) | 1990-06-19 | 1990-06-19 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451564A true JPH0451564A (en) | 1992-02-20 |
Family
ID=15712064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2160304A Pending JPH0451564A (en) | 1990-06-19 | 1990-06-19 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451564A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629465A (en) * | 1992-05-12 | 1994-02-04 | Internatl Business Mach Corp <Ibm> | Capacitor and its manufacture |
| WO1999065063A3 (en) * | 1998-06-10 | 2000-03-16 | Siemens Ag | Dram storage capacitor |
| KR100295258B1 (en) * | 1993-12-28 | 2001-09-17 | 가네꼬 히사시 | Semiconductor integrated circuit device having a capacitor structure with increased capacitance and a method of manufacturing the same |
-
1990
- 1990-06-19 JP JP2160304A patent/JPH0451564A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629465A (en) * | 1992-05-12 | 1994-02-04 | Internatl Business Mach Corp <Ibm> | Capacitor and its manufacture |
| KR100295258B1 (en) * | 1993-12-28 | 2001-09-17 | 가네꼬 히사시 | Semiconductor integrated circuit device having a capacitor structure with increased capacitance and a method of manufacturing the same |
| WO1999065063A3 (en) * | 1998-06-10 | 2000-03-16 | Siemens Ag | Dram storage capacitor |
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