JP3019404B2 - Insulating film - Google Patents
Insulating filmInfo
- Publication number
- JP3019404B2 JP3019404B2 JP2315331A JP31533190A JP3019404B2 JP 3019404 B2 JP3019404 B2 JP 3019404B2 JP 2315331 A JP2315331 A JP 2315331A JP 31533190 A JP31533190 A JP 31533190A JP 3019404 B2 JP3019404 B2 JP 3019404B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- sio
- insulating
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁膜に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulating film.
超LSIに用いられる半導体メモリ素子は高集積化が進
み、各メモリセルの占有面積はどんどん縮小されてきて
いる。しかしながら、センスアンプの感度には目立った
向上がなく、またα線によるソフトエラーの防止のため
にも、蓄積容量は約30fF以上必要であるといわれてい
る。つまり、占有面積が縮小されているにもかかわら
ず、充分な蓄積容量が必要とされているのである。この
ために、容量素子に用いられる容量絶縁膜が、年々薄膜
化されてきた。また、この薄膜化にともなって、従来使
用されてきた誘電率が3.9のSiO2膜に代って、上層がSiO
2膜，中間層が誘電率7.5と高いSi3N4膜，下層がSiO2膜
で構成される多層構造の容量絶縁膜が用いられるように
なってきた。例えば、信学技報,1987年（SDM87−180）
の43頁〜47頁に「多結晶シリコン上の10nm以下のSiO2/S
i3N4多層膜の信頼性」と題して発表された論文がある。
この論文には、充分な蓄積容量を実現できる方法とし
て、第２図に示した構造の多層容量絶縁膜が提案されて
いる。As semiconductor memory elements used in VLSIs become more highly integrated, the area occupied by each memory cell is steadily reduced. However, it is said that there is no noticeable improvement in the sensitivity of the sense amplifier, and that a storage capacitance of about 30 fF or more is required to prevent soft errors due to α rays. That is, despite the reduced occupation area, a sufficient storage capacity is required. For this reason, a capacitor insulating film used for a capacitor has been reduced in thickness year by year. In addition, along with this thinning, instead of the SiO 2 film having a dielectric constant of 3.9, which has been conventionally used, the upper layer is made of SiO 2.
2 film, the intermediate layer is a dielectric constant 7.5 and higher the Si 3 N 4 film, lower layer has come to the capacitive insulating film of a multilayer structure composed of SiO 2 film is used. For example, IEICE Technical Report, 1987 (SDM87-180)
Pp. 43-47 of `` 10 nm or less SiO 2 / S on polycrystalline silicon
i have 3 N 4 multilayer film reliability "and articles published under the title of.
In this paper, a multilayer capacitor insulating film having a structure shown in FIG. 2 is proposed as a method for realizing a sufficient storage capacitor.
図中に示されているように、この論文で提案された多
層絶縁膜は、電荷蓄積ポリシリコン109上に、CVD法によ
るSi3N4膜103形成時に形成されてしまう自然SiO2膜131,
Si3N4膜130を熱酸化して形成されるSiO2膜132から構成
されている。As shown in the figure, the multilayer insulating film proposed in this paper is a natural SiO 2 film 131, which is formed on the charge storage polysilicon 109 when the Si 3 N 4 film 103 is formed by the CVD method.
It is composed of a SiO 2 film 132 formed by thermally oxidizing the Si 3 N 4 film 130.
従来構造の容量絶縁膜では多層膜の中間層として、誘
電率が7.5のSi3N4膜を用いている。このためさらに薄膜
化したい場合には、中間層の物理的な膜厚を減少させる
事が必要になる。物理的な膜厚を減少させた場合は、容
量値を増大するが、中間層に加わる電界が強くなり、絶
縁膜のリーク電流が増大してしまうという問題点があっ
た。In a capacitor insulating film having a conventional structure, a Si 3 N 4 film having a dielectric constant of 7.5 is used as an intermediate layer of a multilayer film. Therefore, when it is desired to further reduce the thickness, it is necessary to reduce the physical thickness of the intermediate layer. When the physical film thickness is reduced, the capacitance value increases, but the electric field applied to the intermediate layer increases, and there is a problem that the leakage current of the insulating film increases.
本発明の目的は、誘電率の異なる膜を積み重ねて形成
される絶縁膜において、中間層を誘電率が11.9とSi3N4
膜よりも高い多結晶シリコンで形成する事によって、容
量を増大するために絶縁膜が薄膜化された場合において
も、リーク電流を充分に低く抑制することにある。An object of the present invention is to provide an insulating film formed by stacking films having different dielectric constants, wherein the intermediate layer has a dielectric constant of 11.9 and Si 3 N 4
An object of the present invention is to suppress leakage current sufficiently low even when the insulating film is made thinner in order to increase capacitance by being formed of polycrystalline silicon higher than the film.
本願発明の絶縁膜は、容量素子の上部電極と下部電極
の間に設けられた絶縁膜において、第一の絶縁膜と第二
の絶縁膜の間に多結晶シリコン膜が設けられたことを特
徴とする。あるいは、MOSトランジスタのソース領域あ
るいはドレイン領域の上に形成された容量素子の上部電
極と下部電極の間に設けられた絶縁膜において、第一の
絶縁膜と第二の絶縁膜の間に多結晶シリコン膜が設けら
れたことを特徴とする。また、前記第一の絶縁膜と前記
第二の絶縁膜はシリコン酸化膜であることが好ましい。The insulating film of the present invention is characterized in that a polycrystalline silicon film is provided between a first insulating film and a second insulating film in an insulating film provided between an upper electrode and a lower electrode of a capacitor. And Alternatively, in an insulating film provided between an upper electrode and a lower electrode of a capacitor formed over a source region or a drain region of a MOS transistor, a polycrystalline structure is provided between the first insulating film and the second insulating film. A silicon film is provided. Preferably, the first insulating film and the second insulating film are silicon oxide films.
第１図は、本発明の一実施例によって形成される絶縁
膜を用いた半導体メモリセルの模式的断面図及び絶縁膜
部分の拡大図である。FIG. 1 is a schematic cross-sectional view of a semiconductor memory cell using an insulating film formed according to an embodiment of the present invention, and an enlarged view of an insulating film portion.
この実施例では、電荷蓄積ポリシリコン電極109上
に、下層膜として800℃のCVD法で堆積させたSiO2膜120,
中間層膜として650℃のCVD法で堆積させた多結晶シリコ
ン膜121,上層膜として800℃のCVD法で堆積させたSiO2膜
を用いた多層絶縁膜が形成されている。In this embodiment, on the charge storage polysilicon electrode 109, an SiO 2 film 120 deposited as a lower film by a CVD method at 800 ° C.
A multilayer insulating film using a polycrystalline silicon film 121 deposited by a CVD method at 650 ° C. as an intermediate layer film and a SiO 2 film deposited by a CVD method at 800 ° C. as an upper layer film is formed.
下層膜として、電荷蓄積ポリシリコン電極109を熱酸
化したSiO2膜、上層膜として、中間層膜の多結晶シリコ
ン膜121を熱酸化したSiO2膜を用いてもよい。As the underlying film, SiO 2 film charge storage polysilicon electrode 109 was thermally oxidized, as the upper layer, the polycrystalline silicon film 121 of the intermediate layer film may be used an SiO 2 film formed by thermal oxidation.
第２図は、本発明の他の実施例によって形成される絶
縁膜を用いた半導体メモリセルの模式的断面図及び絶縁
膜部分の拡大図である。FIG. 2 is a schematic cross-sectional view of a semiconductor memory cell using an insulating film formed according to another embodiment of the present invention, and an enlarged view of the insulating film portion.
図中に示された多層絶縁膜は、電荷蓄積ポリシリコン
109上に、CVD法によるSi3N4膜130形成時に形成されてし
まう自然SiO2膜131,Si3N4膜130を熱酸化して形成される
SiO2膜132から構成されている。The multilayer insulation film shown in the figure is a charge storage polysilicon
The natural SiO 2 film 131 and the Si 3 N 4 film 130 which are formed when the Si 3 N 4 film 130 is formed by the CVD method on the 109 are formed by thermal oxidation.
It is composed of an SiO 2 film 132.
第１図，第２図ともその他の部分は、全く同一であ
り、素子分離領域，スイッチングトランジスタ，容量素
子，ビット線から構成される。素子分離領域は、シリコ
ン基板101を選択酸化して形成されるフィールド酸化膜1
02で形成される。スイッチングトランジスタは、ゲート
SiO2膜103,ワード線104,SiO2膜105,LDD用側壁SiO2膜10
7,107′,n-層106,106′,n+層108,108′から形成され
る。容量素子は、電荷蓄積電極109,容量多層絶縁膜110,
対向電極111から形成される。ビット線114は、層間絶縁
膜112と自己整合絶縁用側壁SiO2膜113で容量素子と絶縁
され、スイッチングトランジスタのn+層108′と接続さ
れている。1 and 2, the other parts are completely the same, and include an element isolation region, a switching transistor, a capacitor, and a bit line. The element isolation region is a field oxide film 1 formed by selectively oxidizing the silicon substrate 101.
02 is formed. The switching transistor has a gate
SiO 2 film 103, word line 104, SiO 2 film 105, sidewall SiO 2 film for LDD 10
7, 107 ', n - layers 106, 106' and n + layers 108, 108 '. The capacitive element includes a charge storage electrode 109, a capacitive multilayer insulating film 110,
It is formed from the counter electrode 111. The bit line 114 is insulated from the capacitive element by the interlayer insulating film 112 and the self-aligned insulating side wall SiO 2 film 113, and is connected to the n + layer 108 ′ of the switching transistor.
以上のとおり、本発明によれば、膜厚く薄くされても
リーク電流を充分に小さく抑えることができる。As described above, according to the present invention, even if the film thickness is reduced, the leak current can be sufficiently suppressed.
第１図は本発明の一実施例図、第２図は他の実施例であ
る。 101……シリコン基板、102……フィールド酸化膜、103
……ゲート酸化膜、104……ワード線、105……SiO2膜、
106・106′……n-層、107・107′……LDD用側壁SiO
2膜、108・108′……n+層、109……電荷蓄積電極、110
……容量絶縁膜、111……対向電極、112……層間絶縁
膜、113……自己整合絶縁層側壁SiO2膜、114……ビット
線、120……800℃のCVD法で堆積させたSiO2膜、121……
650℃のCVD法で堆積させた多結晶シリコン膜、122……8
00℃のCVD法で堆積させたSiO2膜、130……CVD法によるS
i3N4膜、131……CVD法によるSi3N4膜形成時に形成され
てしまう自然SiO2膜、132……Si3N4膜を熱酸化して形成
されるSiO2膜。FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows another embodiment. 101 ... silicon substrate, 102 ... field oxide film, 103
…… Gate oxide film, 104… Word line, 105… SiO 2 film,
106 ・ 106 ′ …… n - layer, 107 ・ 107 ′ …… side wall SiO for LDD
2 films, 108 and 108 '... n + layer, 109 ... charge storage electrode, 110
...... capacitor insulating film, 111 ...... counter electrode, 112 ...... interlayer insulating film, 113 ...... self-aligned insulating layer sidewall SiO 2 film, 114 ...... bit lines, SiO deposited by CVD of 120 ...... 800 ° C. Two films, 121 ……
Polycrystalline silicon film deposited by CVD at 650 ° C, 122 …… 8
SiO 2 film deposited by CVD at 00 ° C, 130 ... S by CVD
i 3 N 4 film, 131: a natural SiO 2 film formed when forming a Si 3 N 4 film by a CVD method; 132: an SiO 2 film formed by thermally oxidizing a Si 3 N 4 film.
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/08,21/8242 H01L 27/04,21/822 H01L 21/316 Continuation of the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 27 / 08,21 / 8242 H01L 27 / 04,21 / 822 H01L 21/316
Claims (3)
られた絶縁膜において、第一の絶縁膜と第二の絶縁膜の
間に多結晶シリコン膜が設けられたことを特徴とする絶
縁膜。1. An insulating film provided between an upper electrode and a lower electrode of a capacitive element, wherein a polycrystalline silicon film is provided between a first insulating film and a second insulating film. Insulating film.
レイン領域の上に形成された容量素子の上部電極と下部
電極の間に設けられた絶縁膜において、第一の絶縁と第
二の絶縁膜の間に多結晶シリコン膜が設けられたことを
特徴とする絶縁膜。2. An insulating film provided between an upper electrode and a lower electrode of a capacitor formed on a source region or a drain region of a MOS transistor, wherein the insulating film is provided between a first insulating film and a second insulating film. An insulating film provided with a polycrystalline silicon film.
リコン酸化膜であることを特徴とする請求項１及び２記
載の絶縁膜。3. The insulating film according to claim 1, wherein said first insulating film and said second insulating film are silicon oxide films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2315331A JP3019404B2 (en) | 1990-11-20 | 1990-11-20 | Insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2315331A JP3019404B2 (en) | 1990-11-20 | 1990-11-20 | Insulating film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04184931A JPH04184931A (en) | 1992-07-01 |
| JP3019404B2 true JP3019404B2 (en) | 2000-03-13 |
Family
ID=18064126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2315331A Expired - Lifetime JP3019404B2 (en) | 1990-11-20 | 1990-11-20 | Insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3019404B2 (en) |
-
1990
- 1990-11-20 JP JP2315331A patent/JP3019404B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04184931A (en) | 1992-07-01 |
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