JPH08255878A - Floating gate transistor and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain a floating gate transistor, and a fabrication method thereof in which a refresh time appropriate for a DRAM, comprising a floating gate transistor can be ensured. CONSTITUTION: A gate insulation film comprising a dielectric film 4 and an SiC film 5 is provided on a silicon substrate 1 and a floating gate 6 is provided on the gate insulation film. The dielectric film 4 is provided at least one of the interface between the SiC film 5 and the silicon substrate 1 and the interface between the SiC film 5 and the floating gate 6. Thickness of the dielectric film 4 is set such that the tunnel conduction prevails.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating gate transistor and its manufacturing method, and more particularly to
RAM (Dynamic Random Access Memory)
And a method for manufacturing the same.

In recent years, as the integration density of semiconductor memory devices has been improved, stack type capacitors, fin type capacitors, trench type capacitors, etc. have been adopted in volatile memory DRAMs. However, it is becoming difficult to secure the capacitance of the capacitor.

It has also been proposed to use an insulating film having a high dielectric constant as a dielectric film forming the capacitor in order to increase the capacitance of the capacitor. However, a capacitor using this insulating film having a high dielectric constant is miniaturized. Therefore, there is a problem that the leakage current increases as the layer becomes thinner, and 4 Gb
Prospect of it after the DRAM is not standing.

On the other hand, EE that does not require a capacitor capacity
PROM (Electrically Erasable)
e Programmable Read-Only
A non-volatile memory such as a Memory) or a FLASH memory cannot be used as a DRAM because the rewriting speed, that is, the charge injection speed or the charge erasing speed is slow.

That is, in a normal nonvolatile floating gate transistor, a SiN _x film having a smaller forbidden band width than a SiO ₂ film is used as a gate insulating film in order to reduce an applied voltage and a writing time at the time of writing. However, the applied voltage during writing is still high, and
Since the writing time is long, it cannot be used as a DRAM.

In order to further reduce the applied voltage during writing and the writing time, a material having a small forbidden band width such as β-SiC (E _g = 2.2 eV) is used as the gate insulating film. Alternatively, the thickness of the gate insulating film may be set to 3 nm or less, but since the non-volatile memory aims at permanent storage of injected charges, diffusion current and tunnel current are neglected with such a material and thickness. Can not
There is an inconvenience that it cannot be put to practical use as a non-volatile memory.

Therefore, the present inventor has proposed to use the floating gate transistor as a DRAM by utilizing such inconvenience (Japanese Patent Application No. 6-121339). This proposal will be described with reference to FIG.

Referring to FIG. 3, this floating gate transistor is a source / source provided on a p-type silicon semiconductor substrate 1.
Between the drains 2 and 3, a β-SiC film 5 having a thickness of 10 nm
As a gate insulating film, on which a polysilicon floating gate 6 having a thickness of 200 nm, a SiO ₂ film 7 having a thickness of 5 nm as an interlayer insulating film, and a control gate 8 are formed.
Is provided. In addition, 9 and 10 are a source electrode and a drain electrode, respectively.

In this case, β-SiC (electron affinity: 3.
The height of the electron barrier due to the difference in electron affinity to silicon of 47 eV) is 0.55 eV, which is 0.5 to 1 which is the condition of the height of the electron barrier when the floating gate transistor is used as a DRAM. .2 eV
The conditions of are met.

If the height of the electron barrier is 0.5 eV or less, the injected charges (electrons) escape as a diffusion current in a very short time, so that a practical refresh time can be set. In addition, if the height of the electron barrier is 1.2 eV or more, the writing time becomes too long to be put to practical use.

Further, since this β-SiC can be directly epitaxially grown on a silicon substrate, there is an advantage that it is well compatible with the current VLSI manufacturing process.

A nonvolatile memory (see Japanese Patent Laid-Open No. 56-56677) provided with a double insulating layer composed of a SiO ₂ film and a SiC film is known as a structure similar to that proposed by the present inventor. There is.

However, this non-volatile memory is
The charge is held by the trap level at the SiO ₂ interface or SiC itself, and the thickness of the SiO ₂ film in this case is such that tunnel conduction is not dominant.
_Since the injection charge is held by utilizing the high insulation property of the _two films, the essence is different from the above proposal.

[0014]

However, .beta.-SiC is a condition of the height of the electron barrier when the floating gate transistor is used as a DRAM, which is 0.5-1.
Although the condition of 2 eV is satisfied, the height of the electron barrier is close to the lower limit of 0.55 eV, and accordingly, there is a problem that the charge retention time becomes short and an appropriate refresh time cannot be secured.

In order to obtain a proper refresh time,
Although an electron barrier height of about 0.85 eV is required, compatibility with the current VLSI manufacturing process is good, and no suitable material having an electron affinity difference with silicon of about 0.85 eV is found. , Β as the gate insulating film
-It was difficult to use materials other than SiC.

Therefore, an object of the present invention is to secure an appropriate refresh time of a DRAM composed of a floating gate transistor by using β-SiC which has good compatibility with the current VLSI manufacturing process.

[0017]

According to the present invention, a gate insulating film composed of a dielectric film (4 in FIG. 1) and a SiC film (5 in FIG. 1) is provided on a silicon substrate (1 in FIG. 1), and In a floating gate transistor in which a floating gate (6 in FIG. 1) is provided on the gate insulating film, the dielectric film (4 in FIG. 1) is replaced with the SiC film (5 in FIG. 1) and the silicon substrate (FIG. 1). Of 1) and the SiC
At least one of the interfaces between the film (5 in FIG. 1) and the floating gate (6 in FIG. 1) is provided, and the thickness of the dielectric film (4 in FIG. 1) is such that tunnel conduction becomes dominant. It is characterized by having done.

Further, the present invention is characterized in that any one of SiO ₂ , SiN _x and SiO _x N _y is used as the dielectric film (4 in FIG. 1). Further, the present invention is characterized in that the thickness of the dielectric film (4 in FIG. 1) is 3 nm or less.

According to the present invention, in the method of manufacturing a floating gate transistor, a SiC film (5 in FIG. 1) is deposited on a silicon substrate (1 in FIG. 1) and then thermally oxidized in an oxidizing atmosphere. Is characterized in that a SiO ₂ film (4 in FIG. 1) having a thickness at which tunnel conduction is dominant is formed at the interface between the silicon substrate (1 in FIG. 1) and the SiC film (5 in FIG. 1). .

Further, according to the present invention, in the method of manufacturing a floating gate transistor, after depositing a SiC film (5 in FIG. 1) on a silicon substrate (1 in FIG. 1), oxygen ions are implanted and heat treatment is performed. A SiO ₂ film (4 in FIG. 1) having a thickness at which tunnel conduction is dominant is formed at the interface between the silicon substrate (1 in FIG. 1) and the SiC film (5 in FIG. 1).

Further, according to the present invention, in a method of manufacturing a floating gate transistor, a dielectric film (4 in FIG. 1) having a thickness at which tunnel conduction is dominant is formed on a silicon substrate (1 in FIG. 1). , A SiC film (Fig. 1
5) is deposited.

Further, according to the present invention, in the method for manufacturing a floating gate transistor, a SiC film (5 in FIG. 1) is deposited on a silicon substrate (1 in FIG. 1), and then a dielectric film is formed on the surface thereof. It is characterized by

[0023]

The gate insulating film is effectively formed by sequentially stacking the dielectric film and the SiC film, which have the electron barrier against silicon higher than that of SiC on the silicon substrate and the tunnel conduction is dominant, on the silicon substrate. The height of the electron barrier can be increased, whereby the electron storage time, and thus the refresh time as a DRAM, can be set to a practical value.

As the dielectric film, SiO ₂ or SiN is used.
_x, and, by using any one of a SiO _x N _y, good integrity and silicon process, and, since characteristics of the interface with the substrate can be improved, the electron accumulation time It can be a proper value.

Further, when the thickness of the dielectric film is 3 nm or less, the tunnel tunneling of electrons occurs quantum mechanically, so the conduction in the dielectric film is dominated by the tunnel current, and the electrons of the dielectric film are Since the height of the electron barrier is not effectively sensed, the DRAM operation can be performed without exhibiting the property as an insulator. When the thickness of the dielectric film exceeds the thickness at which electrons can be tunneled, a normal floating gate type nonvolatile memory is obtained.

Further, by depositing a SiC film on a silicon substrate and then thermally oxidizing it in an oxidizing atmosphere,
Oxygen in the atmosphere permeates the SiC film, and the silicon substrate and S
The SiO ₂ film having a thickness reaching the interface with the iC film and in which tunnel conduction is dominant can be gradually formed, and the interface characteristics are excellent.

After depositing a SiC film on a silicon substrate, oxygen ions are implanted and a heat treatment is performed to form an SiO ₂ film having a thickness at which tunnel conduction is dominant at the interface between the silicon substrate and the SiC film. It can be formed with good controllability.

The basic principle of the present invention is a combination of a SiC film and a dielectric film having a thickness in which tunnel conduction is dominant, and the order of forming them does not matter, so that a dielectric film is formed on a silicon substrate. The SiC film may be deposited after forming the body film, or the dielectric film may be formed after depositing the SiC film, and the degree of freedom in the manufacturing process can be increased.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A floating gate transistor according to an embodiment of the present invention will be described with reference to FIG. Note that FIG. 1 shows a cross-sectional view of a main part of a floating gate transistor, and in reality, a large number of such floating gate transistors are arranged in a matrix.

First, referring to FIG. 1, first, a p-type silicon semiconductor substrate 1 having an impurity concentration of 5 × 10 ¹⁶ cm ⁻³ is formed on the surface thereof with a thickness of 1 nm by thermal oxidation.
_{After the two} films 4 are formed, a β-SiC film 5 with a thickness of 9 nm, a polysilicon floating gate 6 with a thickness of 200 nm, and a SiO ₂ film with a thickness of 10 nm as an interlayer insulating film are formed by a chemical vapor deposition method (CVD method). 7 and control gate 8 are deposited. In this case, since the interface with the silicon substrate is the Si / SiO ₂ interface whose process technology is improved, a good interface with few trap levels can be obtained.

The growth condition of the β-SiC film 5 in this case is that the substrate temperature is 800 to 1000 ° C., preferably 900.
C., a mixed gas of acetylene (C ₂ H ₂ ) and disilane (Si ₂ H ₆ ) is used as a source gas, and H ₂ or He is used as a carrier gas so that the total pressure is 2
The condition is 00 Pa, and β-SiC in a polycrystalline state is obtained.

Next, the control gates 8 through SiO
₂ After patterning the film 4 to have a gate length of 0.8 μm and a gate width of 1 μm, As is ion-implanted to form n ⁺ type source / drains 2 and 3 in a self-aligned manner with respect to the gate. Finally, the source / drain electrodes 9 and 10 are formed through a protective film such as a PSG film and a contact hole provided in the protective film to complete the floating gate transistor.

As described above, since the gate insulating film is formed by combining the β-SiC film 5 for ensuring the insulation reliability and the SiO ₂ film 4 having a thickness that does not exhibit the properties as an insulator, the charge storage life is increased. That is, the retention time of memory can be controlled by the thickness of the SiO ₂ film 4, and in the case of the embodiment, it is 1 s.
Since it can be set to about (second), the refresh time can be set to a practical value.

Further, since the SiO ₂ film 4 allows carriers to freely enter and exit by a tunnel current, unlike a non-volatile memory, the Fowler-Nordheim (Fowler-Nordheim) is used without using avalanche injection.
im) type tunnel injection can be used to inject charge into the polysilicon floating gate,
Therefore, the write / read / erase time is about 10 ns, and it can be used as a DRAM.

Next, a method of writing / reading / erasing information of the floating gate transistor will be described with reference to FIG. The capacitance between the control gate and the floating gate in this case is 16 fF (fem
to Farad), the capacitance between the floating gate and the silicon substrate is 7 fF, the bit line capacitance during reading is 2 pF,
Also, the floating gate potential during writing is -0.5.
V.

First, referring to FIG. 2, the case of writing information will be described. For example, when writing information to the cell 22 in the figure, the word line 2 is set to 3V and the other word lines are set to 1.5V. When the bit line 2 and the source line 2 are set to 0V and the other bit lines and the source lines are set to 1.5V, the voltage between the silicon substrate and the control gate is 3V in the cell 22 and 1.5 or 0V in the other cells. And the cell 22 with a potential of 3V
Information is written only in the Fowler-Nordheim tunnel injection.

Next, the case of reading the information of the cell 22 will be explained. It is assumed that all the bit lines are 0.5V, all the source lines are 0V, the word line 2 is 0.5V, and the other word lines are 0V.

Then, the floating gate potential is 0 V, that is, the bit line potential when information is not written is lowered, and the floating gate potential is-.
Since the bit line potential is 0.5 V, that is, there is no fluctuation when information is written, the presence or absence of information writing in the cell 22 is detected by the difference.

Next, the case of erasing the information written in the cell 22 will be described. The bit line 2 and the source line 2 are set to 3
V, all other bit lines and source lines are 1.5V
And word line 2 is 0V, other word lines are 1.5V
And

In this case, the potential difference between the source / drain and the control gate is 3 V only in the cell 22 and 1.5 V at maximum in the other cells.
The electrons accumulated in the cell 22 to which the potential difference of 2 is applied escape to the source / drain side by the Fowler-Nordheim tunnel injection, and the floating gate potential becomes 0.
However, the erasing of information in the cell 22 is completed, but the floating gate potential does not change in other cells having a small potential difference.

In the above embodiment, polycrystalline β-SiC is used as SiC forming a part of the gate insulating film, but other crystalline SiC such as α-Si is used.
C may be used, and the crystalline state does not necessarily have to be polycrystalline, and may be amorphous, microcrystalline, or in some cases,
It may be a single crystal.

Further, the present invention is not limited to the numerical values described in the embodiments, and for example, the thickness of the SiO ₂ film 4 may be 0.5 to 3.0 nm, and the β-SiC film 5 may be formed. The thickness may be ₂ to 100 nm, the thickness of the polysilicon floating gate 6 may be 50 to 400 nm, and the thickness of the SiO ₂ film 7 may be 4.0 to 15 nm.

The impurity concentration of the silicon substrate 1 and the source / drain 2 and 3 may be in the range used as the impurity concentration of a normal MISFET, and the channel length and the channel width are 0.08 to 1, respectively. It may be in the range of 0.0 μm and 0.5 to 20 μm.

Next, a modification of the embodiment of the present invention will be described. In the above embodiment, Si is used as the gate insulating film as well.
Although the O ₂ film 4 is formed by the thermal oxidation method before the β-SiC film 5 is deposited, it may be deposited by the CVD method. In this case, the SiO ₂ film is formed as compared with the thermal oxidation method. Although the withstand voltage of No. 4 is slightly lowered, the floating gate transistor of the present invention does not cause a problem because it is not driven by high voltage.

Further, as the gate insulating film, SiO _{2 is used.}
The film 4 may be replaced with another dielectric film such as a SiN _x film or a SiO _x N _y film. In this case, SiN _x film is used.
_Since the forbidden band width of the _x film or the SiO _x N _y film is smaller than the forbidden band width of the SiO ₂ film and the tunneling probability of charges becomes large, the charge storage time is the thickness and the forbidden band of the SiN _x film or the SiO _x N _y film. It can be controlled by the band width.

Also in this case, the interface with the silicon substrate 1 is the Si / SiN _x interface whose process technology is improved,
Alternatively, since the Si / SiO _x N _y interface is used, a good interface with few trap levels can be obtained.

The SiN _x film in this case has the same composition as or close to the stoichiometric ratio of Si ₃ N ₄ , that is, N / Si.
It suffices if the ratio x is in the range of 1.2 to 1.4. In this case,
This is because if the ratio x is too small, the film quality becomes unstable, and if it is too high, the tensile stress becomes too large. In the SiO _x N _y film, the ratio of N to O is y /
x is 0.5 or less.

Further, such SiN _x film and SiO _x N
_{When the y} film is used, hot carrier resistance due to nitrogen content is improved, insulation reliability is improved, and a blocking effect against impurity diffusion is obtained.Furthermore, the film stress is controlled by selecting the composition ratio appropriately. There is an advantage that can be done.

Further, when the gate insulating film is a SiN _x film or a SiO _x N _y film, the silicon substrate 1 is NH.
_The SiN _x film or the SiO _x N _y film may be formed by directly nitriding in a nitriding atmosphere such as ₃ atmospheres.

The basic principle of the present invention is a combination of the β-SiC film 5 for ensuring insulation reliability and the dielectric film (4 in FIG. 1) having a thickness that does not exhibit properties as an insulator. Therefore, the dielectric film (4 in FIG. 1) is formed on the silicon substrate 1 and β
It does not have to be between the -SiC film 5 and the silicon substrate 1.
The β-SiC film 5 is directly deposited on top of the
CVD of O ₂ film, SiN _x film, or SiO _x N _y film
It may be deposited by a method.

Further, a dielectric film such as SiO ₂ (4 in FIG. 1) may be provided on both upper and lower surfaces of the β-SiC film 5, and in this case, one side is formed as the layer becomes thinner. Even if a defect such as a pinhole occurs in part of the dielectric film (4 in FIG. 1) provided on the other side, a defect such as a pinhole may occur at the corresponding position of the dielectric film provided on the other side. Are very few,
As a whole, a good gate insulating film can be obtained,
Manufacturing yield is improved.

As a method of forming the dielectric film, after the β-SiC film 5 is directly deposited on the silicon substrate 1,
A SiOC film may be formed by oxidizing the surface of the β-SiC film 5 by heat treatment at a temperature of 800 ° C. or higher in an oxidizing atmosphere such as a dry O ₂ atmosphere, a wet O ₂ atmosphere, or a steam atmosphere. In this case, at the same time as the surface of the β-SiC film 5 is oxidized, O ₂ also enters the interface between the silicon substrate 1 and the β-SiC film 5, and the surface of the silicon substrate 1 is gradually oxidized. Trap levels and the like are rarely generated, which leads to improvement of interface characteristics.

The oxidizing atmosphere is the dry O described above.
₂ atmosphere, wet O ₂ atmosphere, water vapor atmosphere, the oxidation rate becomes slower and the controllability of the film thickness becomes better. Furthermore, if an O ₃ atmosphere is used in place of these oxidizing atmospheres, low temperature oxidation will occur. It will be possible.

[0054]

According to the present invention, as a gate insulating film of a floating gate transistor, a dielectric film in which tunnel conduction is predominant and β-SiC for ensuring insulation reliability.
Since the film was used in combination, the writing / reading time was 10
A DRAM having an appropriate refresh time of about ns and a memory retention time of about 1 s (1 second) can be formed without a capacitor, which largely contributes to the improvement of the integration degree of the semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a sectional view of a floating gate transistor according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a circuit configuration of a capacitorless DRAM according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional floating gate transistor.

[Explanation of symbols]

1 p-type silicon semiconductor substrate 2 source 3 drain 4 SiO ₂ film 5 β-SiC film 6 polysilicon floating gate 7 SiO ₂ film 8 control gate 9 source electrode 10 drain electrode

Claims (7)

[Claims] 1. A floating gate transistor in which a gate insulating film made of a dielectric film and a SiC film is provided on a silicon substrate, and a floating gate is provided on the gate insulating film, wherein the dielectric film is the SiC film. The floating gate is provided on at least one of the interface with the silicon substrate and the interface between the SiC film and the floating gate, and the thickness of the dielectric film is such that tunnel conduction is dominant. Transistor. 2. As the dielectric film, SiO ₂ or SiN is used.
_2. The floating gate transistor according to claim 1, wherein any one of _x and SiO _x N _y is used. 3. The floating gate transistor according to claim 1, wherein the dielectric film has a thickness of 3 nm or less. 4. A SiO film having a thickness such that tunnel conduction is predominant at an interface between the silicon substrate and the SiC film by depositing a SiC film on the silicon substrate and then performing thermal oxidation in an oxidizing atmosphere. _A method of manufacturing a floating gate transistor, which comprises forming _two films. 5. A SiC film is deposited on a silicon substrate, oxygen ions are implanted into the SiC film, and then a heat treatment is performed, whereby the silicon substrate and the S
The thickness of S that makes tunnel conduction dominant at the interface with the iC film
A method of manufacturing a floating gate transistor, which comprises forming an iO ₂ film. 6. A method of manufacturing a floating gate transistor, comprising: forming a dielectric film having a thickness on which tunnel conduction is dominant on a silicon substrate, and then depositing a SiC film on the dielectric film. 7. A method of manufacturing a floating gate transistor, comprising depositing a SiC film on a silicon substrate and then forming a dielectric film on the surface of the SiC film.