JP2572432B2 - Color display device - Google Patents

Description

The present invention relates to a color display that stores color image information in a VRAM (video RAM) using luminance data and color difference data, and reads out the stored data for display. Related to the device.

2. Description of the Related Art As a display device that performs color dot display by a CRT display device, a device that stores dot data including luminance data and color difference data in a VRAM has been developed.

This display apparatus converts color data R, G, B into, for example, Y = (1/4) R + (1/8) G + (1/2) B = (1/8) (2R + G + 4B)... (1) J = R−Y (2) K = G−Y (3) The image data is converted into luminance data Y and color difference data J and K based on the following equation. Next, for example, average values J ', K' of the color difference data J, K are calculated for every four continuous dots, and the average values J ', K' are calculated.
And the luminance data Y is stored in the VRAM. That is,
The luminance data is stored in the VRAM corresponding to each dot, but the color difference data is stored as one data every four dots. The reason for this is to limit the capacity of the VRAM, and since the human eyes are less sensitive to changes in color difference, even if this is done, it does not look very different from the original color.

Next, at the time of display, each data Y,
J ′, K ′ are read, and these data Y, J ′, K ′ are written as R = Y + J ′ (4) G = Y + K ′ (5) B = (5/4) Y− (1 / 2) J ′ − (1/4) K ′ = (1/4) {5Y− (2J ′ + K ′)} (6) The color data is returned to R, G, B based on the following formula (6). The data R, G, B are converted to analog signals and output to a CRT display device.

[Problems to be Solved by the Invention] By the way, it is certain that the human eye is not sensitive to the change of the color difference, but if the change of the color difference is every four dots, the change of the color of the screen is not possible. It is inevitable that the state will be unnatural to some extent.

Accordingly, it is an object of the present invention to provide a color display device that stores color difference data for each of a plurality of dots, and that also eliminates unnatural color on a screen.

[Means for Solving the Problems] A first aspect of the present invention is that, among continuous display dots corresponding to luminance data and color difference data, an average value of color difference data for each predetermined number of display dots, Calculate a change obtained by dividing the difference between the average value and the previously calculated average value by the predetermined number of display dots, and determine whether the color difference data is the average value or the change amount. Creation means for creating identification data to be shown, a memory for storing the luminance data, the average value or the change of the color difference data, and the identification data as image data, and an image from the memory at a dot clock timing. Reading means for reading data, detecting whether the color difference data in the read image data is an average value or a variation based on the identification data in the image data, If it is an average value, the average value is output as color difference data.If it is a change amount, the average value of the color difference data in the image data previously read from the memory is used. First arithmetic means for calculating and outputting color difference data by cumulatively adding the predetermined number of display dots, luminance data read from the memory, and color difference data output from the first arithmetic means; And a display means for displaying color dots based on the color data obtained by the second calculation means.

Further, the second invention is a calculating means for calculating an average value of color difference data for each predetermined number of display dots among continuous display dots corresponding to the brightness data and the color difference data, and the brightness data as image data; A memory in which an average value of the color difference data is stored, and reading means for reading image data from the memory at a timing of a dot clock;
The difference between the average value of the color difference data read from the memory this time and the average value of the color difference data read from the previous memory is calculated, and the calculated difference is divided by the predetermined number of display dots to obtain the display dot. A change for each number is calculated, and the change is cumulatively added to the average value of the color difference data read from the previous memory for the predetermined number of display dots for each display dot to calculate and output color difference data. First calculating means;
Second calculation means for obtaining red, green, and blue color data from the luminance data read from the memory and the color difference data output from the first calculation means; Display means for displaying color dots based on the color data.

According to the first aspect of the present invention, the amount of change obtained by dividing the difference between the currently calculated average value and the previously calculated average value of the color difference data for each predetermined number of display dots by the predetermined number of display dots is calculated. Store in memory. Then, this change is read from the memory, and the change is cumulatively added for a predetermined number of display dots for each display dot to the average value of the previously read color difference data to form color difference data. Display based on As a result, the color difference data changes for each dot, and accordingly, the color difference data changes smoothly.

According to the second aspect, the average value of the color difference data for each predetermined number of display dots is stored in the memory, as in the conventional case. Then, when the average value of the color difference data is read from the memory, the difference between the average value and the average value of the color difference data read from the memory last time is calculated, and the calculated difference is divided by a predetermined number of display dots. The resulting change is calculated. Then, the change is cumulatively added by a predetermined number of display dots for each display dot to the average value of the color difference data read from the memory last time to form color difference data, and display is performed based on the formed color difference data.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment, in which 1 is a CPU (central processing unit) and 2 is a C
This is a memory including a ROM in which a program used in PU1 is stored and a RAM for storing data. CPU1 is
Various control commands are output to the display controller 3 based on the control program in the memory 2, and color codes corresponding to display dots are sequentially output to the display controller 3 based on the display program in the memory 2. 1-bit data M is output together with the color code. The data M will be described later in detail. The display controller 3 outputs a control signal to each unit of the apparatus based on a control command from the CPU 1, converts a color code supplied from the CPU 1 into red, green, and blue color data R, G, and B, and outputs the data together with the data M. And outputs the write / read address AD to the VRAM7.

Reference numeral 4 denotes a switching circuit, which outputs color data when the data M output from the display controller 3 is "0".
R, G, and B are output as they are, and when the data M is "1", the data G and B of the input color data R, G, and B are output.
Is replaced and output. Reference numeral 5 denotes a data conversion circuit for converting the color data R, G, B into luminance data Y, color difference data J, K. When the data M is "0", that is, the input terminals I1 to I3
When the color data R, G, B are supplied to the respective sections, data conversion is performed based on the above-described equations (1) to (3).
On the other hand, when the data M is “1”, that is, when the input terminals I1 to I1
When the color data R, B, and G are supplied to I3, the operations of the above equations (1) to (3) in which G and B are interchanged are performed. That is, in this case, Y = (1/4) R + (1/8) B + (1/2) G = (1/8) (2R + B + 4G) (7) J = R−Y (8) K = B−Y (9) The color data R, G, B are converted into the luminance data Y and the color difference data J, K based on the operation formula:

That is, in this color display device,
The color data R, G, and B can be converted into luminance data Y and chrominance data J and K based on the two arithmetic expressions of the expressions (1) to (3) and (7) to (9). It has become. Then, which conversion formula is used is determined by the data M. That is, it is determined by the display program in the memory 2. Note that the luminance data Y is 8-bit data without a sign bit, and the color difference data J and K are both 8-bit data whose MSB is a sign bit (the numerical value is 7 bits).
Data represented by bits).

Here, the reason why two conversion formulas are prepared will be described. First, when the conversion is performed according to the equations (1) to (3), errors in the operation result concentrate on blue (B). The reason for this is that in equations (1) to (3), R and G are included in the equations as they are, but {see equations (2) and (3)}, and B is 1 /
It is included only in the form of 2 (see equation (1)). That is, for B, the LSB (least significant bit) is included in the formula in a cut form, and the conversion error increases accordingly. Further, when the conversion is performed according to the equations (1) to (3), the reproducibility of the high frequency component of green (G) deteriorates. The reason is as follows. That is, in equation (1), the coefficient of G is the smallest and is 1/8. In this embodiment, as will be described in detail later, data is stored for each display dot for luminance data, but one data is stored for every four dots for color difference data. Therefore, data that greatly affects the luminance data Y has the highest reproducibility of the high-frequency component, and conversely, data that has the least effect on the luminance data Y, that is, the color difference data G, has the lowest reproducibility of the high-frequency component. For the same reason, when the conversion is performed by the equations (7) to (9), the error of the conversion operation is concentrated on green (G), and the reproducibility of the high frequency component of blue (B) is deteriorated.

Therefore, if two arithmetic expressions are prepared, the conversion expression can be dynamically switched according to the display image, and the image quality can be improved. Note that, of course, the inside of the data conversion circuit 5 is not changed according to the conversion formula.

Next, the write data creation circuit 6 is a circuit for forming write data to be written to the VRAM 7. In this embodiment, the luminance data Y and the chrominance data J and K output from the data conversion circuit 5 are not directly written in the VRAM 7, but are compressed in the write data forming circuit 6, and the data M and the following data are written. 1-bit data D described in
Is added and written. That is, the write data creation circuit 6 creates write data by the following process every time it receives four pieces of display data including the luminance data Y and the color difference data J and K from the data conversion circuit 5, and writes the write data to the VRAM 7. .

For each of the color difference data J and K, an average value J ′, K ′ of each of the four data is obtained.

The difference ΔJ between the average value J ′ obtained in the above process and the average value J ′ obtained last time and the average value K ′ obtained in the above process
And the difference ΔK between the last calculated average value K ′.

If the absolute value of the obtained difference ΔJ is “0,0,1,0,0,0,0” or more, D = “0” is written into the internal memory, and “0,0,0,1,1” is written. If it is 1,1,1 "or less, write D =" 1 "to the same memory.

When D = “1”, △ J / 4 and △ K / 4 are calculated.

The 4-byte write data is created by the format shown in FIG. Here, y ₁ ~y ₄ is the next data determined in accordance with the upper 5 bits, j, k each data D for each luminance data Y.

D = "0" → upper 5 bits of J ', K' D = "1" → △ J / 4, △ K / 4 Output to VRAM7 sequentially from byte B0 shown in FIG.

Next, based on the address AD output from the display controller 3, the above-described write data is sequentially written into the VRAM 7.
, Each data (byte) is sequentially read based on the address AD supplied at the timing of the dot clock DCLK. The data read from the VRAM 7 is output to the RGB data reproducing circuit 10.

The RGB data reproduction circuit 10 converts the dot clock DC from the VRAM 7
Data y, j, k, D, M (second
Is a circuit for returning color data R, G, and B to the color data R, G, and B shown in FIG.

FIG. 3 is a circuit diagram showing details of the RGB data reproducing circuit 10. In this figure, T1 is a terminal to which data read from the VRAM 7 is supplied, and T2 is a clock pulse D having a frequency of 1/4 of the dot clock DCLK from the display controller 3.
A terminal to which CLK / 4 is supplied, and a terminal T3 to which a dot clock DCLK is supplied from the display controller 3. Also, T4
Is a terminal from which data M is output, and T5 to T7 are terminals from which color data R, G, B (or R, B, G) are output, respectively.

Next, 11 to 17 are parallel in / parallel out registers that read input data based on the dot clock DCLK, 18 are parallel in / parallel out registers that read input data based on the clock pulse DCLK / 4, and 19 is a register 18 When the output data D is "0", the selector outputs the data at the input terminal <0>, and when it is "1", the selector outputs the data at the input terminal <1>. Reference numeral 20 denotes when the data D is "0". A gate circuit 21 which is in a closed state and opened when "1" is provided, and 21 is an adder. At the input terminal A of the adder 21, the output data of the selector 19 is supplied to the upper 5 bits, and the lower 3 bits are grounded. The output data of the gate circuit 20 is supplied to the lower 5 bits of the input terminal B of the adder 21, and the MSB (most significant bit) of the output data of the gate circuit 20 is supplied to the upper 3 bits. Then, the output of the adder 21 is supplied to the register 17. Components 17 to 21 described above
Constitutes a color difference data reproduction circuit G1, and the same color difference data reproduction circuit G2 is provided. Then, the color difference data J, K
Is output.

Reference numeral 22 denotes a flip-flop for reading the data M output from the register 11 based on the clock pulse DCLK / 4, and reference numeral 23 denotes an output of the flip-flop 22 for one of the dot clocks DCLK.
This is a shift register that outputs a signal delayed by a fixed time in units of periods. The certain time will be described later. 24 is luminance data Y, color difference data J and K are color data R,
This is an arithmetic circuit for converting into G and B.

Next, the operation of the RGB data reproducing circuit 10 having the above configuration will be described.

First, the data read from the VRAM 7 is sequentially read into the registers 11 to 14 based on the dot clock DCLK. Here, the format of the read data of the VRAM 7 is as shown in FIG. 2, and data of this format is read in the order of bytes B0 → B3. Therefore, when the first four data are read from the VRAM 7 and read into the registers 11 to 14, the luminance data y _{4 to} y ₁ are respectively output from the lower 5 bits of the registers 11 to 14, and the upper Data j is output from the three bits and the fifth and sixth bits of the register 13, data D is output from the seventh bit of the register 13, and the upper three bits of the register 12 and the
5, Data k is output from the sixth bit, and
Data M is output from the 7th bit 11.

Next, a dot clock DCLK is generated. At this time, a clock pulse DCLK / 4 is generated at the same timing. Then, the dot clock DCLK, luminance data y ₄ ~y ₁ in register 11 to 14 is shifted into the register 12-15, and the next data from VRAM7 in register 11 is written. Also, the clock pulse DCLK / 4 causes the register
The data j and data D output from the circuits 14 and 13 are read into the register 18 in the circuit G1.
The data k and the data D output from 2, 11 are read into the register 18 in the circuit G2.
Is output to the flip-flop 22.

The data j read into the register 18 of the circuit G1 is supplied to the selector 19. When the data D read into the register 18 is “0”, that is, when the data j is the average value J ′, the data j is input via the selector 19 to the input terminal A of the adder 21. Supplied to On the other hand, data D
Is “0”, the gate circuit 20 is closed and the adder
The data “0” is supplied to the input terminal B of 21. As a result,
Data j is output from the adder 21 and supplied to the register 17.

Next, when the dot clock DCLK is generated, the register 12
Luminance data y ₄ ~y ₁ in 15 are respectively shifted to the registers 13 to 16, the luminance data Y from the register 16 to the arithmetic circuit 24 (=
y ₁ ) is supplied. An adder is added to register 17 of circuit G1.
Data j output from 21 is read, and the read data j is supplied to the arithmetic circuit 24 as color difference data J. Similarly, the data k is obtained from the register 17 in the circuit G2.
Is output to the arithmetic circuit 24 as color difference data K. The arithmetic circuit 24 includes the luminance data Y output from the register 16 and the circuit G
The color data R, G, B are calculated from the color difference data J, K respectively output from 1, G2 based on the following equations, and output to the switching circuit 30 (FIG. 1) from terminals T5 to T7.

J + Y = R (10) K + Y = G (11) (5/4) Y−J / 2−K / 4 = B (12) Note that these equations (10) to (12) are (1)-
It is obtained by solving equation (3) for R, G, and B.

Next, when the dot clock DCLK is generated, the register 16
The luminance data Y = y ₂ is read into the arithmetic circuit 24 and output to the arithmetic circuit 24. The output data of the adder 21 is read into the register 17 of the circuit G1 again, and is output to the arithmetic circuit 24. However, since data is read into the register 18 once every four pulses of the dot clock DCLK, at this time, the output data of the adder 21 is the same as the previous one (before one dot clock DCLK). The data is the same as before. Similarly, the data K output from the circuit G2
Is the same as last time. Then, the arithmetic circuit 24 the luminance data Y = y ₂ and the color difference data J as described above, the color data from the K
Calculate and output R, G, B. Thereafter, the same processing is repeated twice, whereby the arithmetic circuit 24 outputs four sets of color data.
R, G, B are output.

On the other hand, the data M read into the flip-flop 22 is delayed for a predetermined time by the shift register 23 and output to the terminal T4. Here, the delay time by the shift register 23 is the delay time by the register 17 and the delay time by the processing in the arithmetic circuit 24. Therefore, the data M is output from the terminal T4 at the same timing as when the color data R, G, B based on the data j and D read into the register 18 are output from the terminals T5 to T7.

Now, while the four data read from the VRAM 7 are being converted into the color data R, G, B in the above-described process, the next four data are sequentially read from the VRAM 7. Then, when these four data are read into the registers 11 to 14, each of the registers 1 and 2 of the circuits G1 and G2 at the timing of the next dot clock DCLK.
8, new data j, k and data D are read. When the data D is "0", the calculation of the color data R, G, B is performed in the same manner as described above.

On the other hand, when data D is "1", that is, data j, k
Is △ j (= △ J / 4) and △ k (= △ K / 4), the following operation is performed. That is, when the data #j and the data D ("1") described above are read into the register 18 of the circuit G1 by the clock pulse DCLK / 4, the gate circuit 20 is opened, and the data $ j causes the gate circuit 20 to operate. Through adder
It is supplied to 21 input terminals B. When data D = “1” is supplied to the selector 19, the data in the register 17, that is, the color difference data J output to the arithmetic circuit 24 one dot clock DCLK before is supplied to the adder 21 via the selector 19. Is supplied to the input terminal A. The adder 21 adds the color difference data J supplied to the input terminal A and the data $ j supplied to the input terminal B, and outputs the addition result (J + $ j) to the input terminal of the register 17.

Next, when the dot clock DCLK is generated, the above-mentioned data (J +） j) is read into the register 17 and the operation circuit
The signal is output to the adder 21 via the selector 19. Similarly, data (K + @ k) is output from the register 17 in the circuit G2 and supplied to the arithmetic circuit 24. The arithmetic circuit 24 calculates and outputs color data R, G, B based on the luminance data Y output from the register 16 and the data (J + Δj) and (K + Δk). On the other hand, circuit G
The adder 21 in 1 is the input terminal A data (J + Ｊj).
And the data △ j of the input terminal B, and the result of this addition (J + 2 △ j) is output to the register 17. Next, when the dot clock DCLK is generated, data (J + 2 @ j) is output from the register 17 in the circuit G1 and the register 17 in the circuit G2.
(K + 2 @ k) are respectively output from the
Is supplied to the arithmetic circuit 24 together with the luminance data Y therein. The arithmetic circuit 24 calculates color data R, G, B based on these data.
Is calculated and output. Thereafter, when the dot clock DCLK is generated, data (J + 3 △ j), (K + 3
Δk), data (J + 4 △ j), and (K + 4 △ k) are sequentially output and supplied to the arithmetic circuit 24, and the arithmetic circuit 24 sequentially outputs color data R, G, and B based on these data. .

As described above, when the data D is “1”, the data #j read into the register 18 is added to the previous color difference data J at every dot clock DCLK and output to the arithmetic circuit 24. Therefore, in the conventional display device,
For example, as shown in FIG. 4 (a), the color difference data J changes every four dots, whereas in this display device, as shown in FIG.
It can be changed stepwise for each dot. It goes without saying that D = "1" may be continuously written to the VRAM7.

The color data R, G, B output from the terminals T5 to T7 of the RGB data reproduction circuit 10 and the data M output from the terminal T4 are supplied to the input terminals I1 to I3 of the switching circuit 30 in FIG. Is done. When the data M is “0”, the switching circuit 30
The color data R, G, and B output from the B data reproduction circuit 10 are output as they are, while if the data M is "1", the input terminal
The data of I2 and the data of input terminal I3 are exchanged and output.

That is, as described above, when the data M is "0", the data conversion circuit 5 converts the data R, G, B into data Y, J, K based on the above equations (1) to (3). Thus, the data y, j, k based on the equations (1) to (3) are stored in the VRAM 7. When the data y, j, k are read from the VRAM 7 and supplied to the RGB data reproducing circuit 10, the (1)
0) to (12), data conversion is performed,
5, T6 and T7 output color data R, "G" and "B", respectively. Then, at this time, since the data M = "0",
The color data R, G, B are output from the switching circuit 30 as they are, and DACs (digital / analog converters) 31, 32, 33
Supplied to

On the other hand, when the data M is "1", the data conversion circuit 5 converts the data R, G, B into the data Y, based on the equations (7) to (9).
The data is converted into J and K and output. Therefore, data y, j and k based on the equations (7) to (9) are stored in the VRAM 7. When the data y, j, k are read from the VRAM 7 and supplied to the RGB data reproducing circuit 10, data conversion is performed based on the above equations (10) to (12). As a result, the color data R, "B", "G" are output from the terminals T5, T6, T7, respectively. At this time, since the data M is "1", the data B and G in the color data R, B, and G are exchanged and output from the switching circuit 30 in the order of R, G, and B. The signals are supplied to DACs (digital / analog converters) 31, 32, and 33.

The DACs 31 to 33 convert the color data R, G, and B supplied from the switching circuit 30 into analog color signals, respectively, and output the analog color signals to the CRT display device 35. The CRT display device 35 performs color dot display based on these color signals.

The above is the details of the first embodiment of the present invention. next,
A second embodiment of the present invention will be described. The second embodiment differs from the first embodiment in the following two points.

Data D is not created in write data creation circuit 6. Therefore, the data D is not stored in the VRAM 7, and the data j, k stored in the VRAM 7 always have the average value J ',
K '.

The configuration of the color difference data reproducing circuits G1 and G2 in the RGB data reproducing circuit 10 is different. Each of the color difference data reproducing circuits G1a and G2a in the second embodiment forms and outputs color difference data J and K which constantly change stepwise for each dot (see FIG. 6 (b)).

Next, the details of the above-described color difference data reproducing circuit G1a will be described in the fifth.
This will be described with reference to the drawings. In this figure, T11 is a terminal to which data j is applied, T12 is a terminal to which a clock pulse DCLK / 4 is applied, T13 is a terminal to which a dot clock DCLK is applied, and T14 is a terminal to which color difference data J is output. . Next, 41 and 42 are registers for reading data at the input terminal based on the clock pulse DCLK / 4, and 43 is an arithmetic circuit. The arithmetic circuit 43 converts the output data of the register 41
Is subtracted, the result of the subtraction is divided by 4, and output as data De (see FIG. 7 (g)), and at the same timing as the clock pulse DCLK / 4, FIG.
The signal LOAD shown in is output. 44 is a selector, 45 is an adder, and 46 is a register for reading the data of the input terminal based on the dot clock DCLK.

Next, the operation of the color difference data reproducing circuit G1a having the above configuration will be described with reference to the timing chart shown in FIG.

First, as shown in FIG. 7 (b), the display data D0 ₁ ~D0 ₄ of 4 bytes from VRAM7 are read sequentially, the register 11
When loaded in to 14 (FIG. 3), the input end to the data j in the register 41 via the terminal T11 of FIG. 5 (hereinafter referred to as j ₁₎ is supplied. Next, a dot clock DCLK is generated and a clock pulse DCLK / 4 {FIG. 7 (C)} is generated. This clock pulse DCLK / 4, the data j ₁ is read into the register 41 {7 (d)}. Next, VR
4 bytes of display data D1 ₁ ~D1 ₄ is read out from the AM7,
When read into registers 11-14, these display data
D1 ₁ ~ D1 included in the _fourth data j (hereinafter referred to as j2) is supplied to the input of register 41. Next, when the clock pulse DCLK / 4 is generated, the data j ₁ are registers 42, The data j ₂ is loaded into the register 41. At this time, the signal LOAD {FIG. 7 (f)} simultaneously output from the arithmetic circuit 43 becomes “1”, and the output data De {FIG. 7 (g)} indicating the arithmetic result of the arithmetic circuit 43 becomes “1”. 0 ". When signal LOAD becomes "1", the output data j ₁ of the register 42 is supplied to the input terminal A of the adder 45 via the selector 44, in the adder 45 is added to the data De (= 0) {7 Figure (h)}, the sum j ₁ is supplied to the input of the register 46.

Then, the dot clock DCLK is generated, the output data j ₁ is loaded into register 46 {FIG. 7 (i)} of the adder 45, is outputted to the terminal T14, the input terminal of the selector 44 to the <0> Supplied. Then, at this time, the signal LOAD
Is “0”, the data j ₁ is supplied to the adder 45 via the selector 44. On the other hand, at this time, the arithmetic circuit 43 outputs data De as shown in FIG.
“(J ₂ −j ₁ ) / 4 = △ 1” is output, and as a result, the adder
Data “j ₁ + $ 1” is output from 45 {FIG. 7 (H)}. Next, when the dot clock DCLK is generated, the output data "j + $ 1" of the adder 45 described above is read into the register 46 (FIG. 7 (i)) and output to the terminal T14.
The same data “j + ｊ1” is supplied to the adder 45 via the selector 44, and the adder 45 outputs data “j + 2 △ 1”. Then, when the next dot clock DCLK is generated, data “j + 2 △ 1” is output from the register 46, and as a result, data “j + 3 △ 1” is output from the adder 45.

Next, the clock pulse DCLK / 4 and the signal LOAD (“1” signal) are generated at the same time when the dot clock DCLK is generated. When the dot clock DCLK is generated, the register 46 reads and outputs the data “j + 3 △ 1”. When the clock pulse DCLK / 4 is generated, the data j ₂ and j ₃ are read into the registers 41 and 42, respectively (see FIGS. 7D and 7E), and the data j read into the register 42 is read. ₂ is supplied to the adder 45 via the selector 44.
At this time, the data De “0” is output from the arithmetic circuit 43 and supplied to the adder 45. As a result, the data j ₂ is output from the adder 45 is supplied to the register 46. Then, the dot clock DCLK is generated, the data j ₂ described above is outputted loaded into register 46. Thereafter, as described above, each time the dot clock DCLK is generated, the register
From 46, “j ₂ + △ 2”, “j ₂ + 2 △ 2”, “j ₂ + 3 △ 2”
(However, △ 2 = (j ₃ −j ₂ ) / 4) is sequentially output, then data j ₃ is output, and the above processing is repeated thereafter. FIG. 6 (a) shows data j read from VRAM7.
(B) shows a change in the data J output from the register 46 corresponding to the data j shown in (a).
Thus, while the data j read from the VRAM 7 changes every four display dots, the data J output from the register 46 changes stepwise for each display dot.

[Effects of the Invention] As described above, according to the present invention, the difference between the currently calculated average value and the previously calculated average value of the color difference data for each predetermined number of display dots is calculated using the predetermined number of display dots. The change obtained by dividing is stored in a memory, and when this change is read from the memory, the change is cumulatively added for each display dot by a predetermined number of display dots to the average value of the color difference data read last time. Color difference data is formed, and the display is performed based on the formed color difference data. Therefore, the effect of eliminating the unnatural color of the display screen by performing the display based on the average value of the color difference data can be eliminated. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a color display device according to a first embodiment of the present invention, FIG. 2 is a diagram showing a format of data stored in a VRAM 7 in the embodiment, and FIG. FIG. 4 is a block diagram showing the configuration of the RGB data reproducing circuit 10 in FIG.
FIG. 5 is a diagram for explaining the operation of the color difference data reproducing circuit G1 at 0, FIG. 5 is a block diagram showing the configuration of the color difference data reproducing circuit G1a according to the second embodiment of the present invention, and FIG. FIG. 7 is a diagram for explaining the operation of G1a, and FIG. 7 is an operation timing chart of each part of the same color difference data reproduction circuit G1a. 3 display controller, 7 VRAM, 24 arithmetic circuit, 35 CRT display device, G1, G2, G1a, G2a color difference data reproduction circuit.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-100490 (JP, A) JP-A-55-124375 (JP, A) JP-A-55-124376 (JP, A)

Claims (2)

(57) [Claims] 1. An average value of color difference data for each predetermined number of display dots among continuous display dots corresponding to luminance data and color difference data, or the average value calculated this time and the average value calculated last time. Calculating a change obtained by dividing the difference from the average value by the predetermined number of display dots, and creating identification data indicating whether the color difference data is the average value or the change amount. Means, (b) a memory for storing the luminance data, the average value or the change of the color difference data, and the identification data as image data, and (c) image data from the memory at a dot clock timing. (D) detecting whether the color difference data in the read image data is an average value or an amount of change based on the identification data in the image data, In the case of, the average value is output as color difference data, and in the case of a change amount, the average value of the color difference data in the image data read from the memory last time is used, and the change amount is provided for each display dot. To calculate and output color difference data by cumulatively adding the number of display dots
(E) from the luminance data read from the memory and the color difference data output from the first calculating means,
A color display device comprising: a second calculating means for obtaining green and blue color data; and (f) a display means for displaying a color dot based on the color data obtained by the second calculating means. (A) calculating means for calculating an average value of color difference data for each predetermined number of display dots among continuous display dots corresponding to luminance data and color difference data; and (b) said image data as said image data. A memory in which luminance data and an average value of the color difference data are stored; (c) reading means for reading image data from the memory at a dot clock timing; and (d) color difference data read from the memory at this time. And the average value of the color difference data read from the previous memory is calculated, and the calculated difference is divided by the predetermined number of display dots to calculate a change for each display dot number. A first calculating means for calculating and outputting color difference data by cumulatively adding the change to the average value of the color difference data read from the memory for the predetermined number of display dots for each display dot; (E) to red luminance data read from the memory, and the color difference data output from said first calculating means,
A color display device comprising: a second calculating means for obtaining green and blue color data; and (f) a display means for displaying a color dot based on the color data obtained by the second calculating means.