JPH0661034B2 - Color display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color display device in which the storage capacity of VRAM (video RAM) is reduced.

"Prior Art" When displaying color dots on a CRT display device,
A method is known in which red color data R, green color data G, and blue color data B are stored in the VRAM for each dot, the color data R, G, B are read out and converted into analog color signals for display. ing. As another method, the color data R, G, B are once converted into luminance data and color difference data and stored in the VRAM, and the luminance data and color difference data are read out from the VRAM and converted into the color data R, G, B. There is also known a method of converting and further converting into an analog color signal for display. In the case of this method, mutual conversion of color data R, G, B and luminance data and color difference data is usually performed by an analog circuit.

"Problems to be Solved by the Invention" By the way, when high-gradation color dot display is performed in a color display device, the number of bits of display data such as color data R, G, B or luminance data and color difference data must be increased. I have to. However, there is a problem that the capacity of the VRAM increases as the number of bits of display data increases.

Further, in the case of a color display device in which the color data R, G, B are converted into luminance data and color difference data and stored in the VRAM, a conversion error occurs when the color data R, G, B luminance data and color difference data are mutually converted. There is.

The present invention has been made in view of the above circumstances, and an object thereof is a digital technique capable of compressing the amount of display data and minimizing the influence of the conversion error. To provide a color display device of a luminance data and color difference data storage system according to the above.

"Means for Solving Problems" A first aspect of the present invention is, in a color display device that performs color dot display, color information indicating a color of each dot including luminance data Y, "red-luminance" color difference data U, and "color information". Conversion means for converting into "green-luminance" color difference data W, calculation means for calculating an average value of each of the color difference data U, W for each plurality of dots, average value of the color difference data U, W and the luminance data And a writing means for writing Y in the memory.

In a second aspect of the present invention, in a color display device that displays color dots, the color information indicating the color of each dot includes luminance data Y, an average value of “red-luminance” color difference data U, and “green-luminance”. “Memory stored by the average value of the color difference data W and the data read from the memory, and the read data is red green blue color data R, G, B
And a display means for performing color dot display based on the color data R, G, B.

[Operation] According to the present invention, since the average values of the color difference data U and W are taken and stored in the memory, for example, when the average value is taken every 4 dots, one data may be stored for every 4 dots. , The memory capacity can be reduced. Further, according to the present invention, since the "red-luminance" color difference data U and the "green-luminance data color difference data W are used, the conversion error is concentrated in blue. As a result, the influence of the conversion error can be minimized.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment, and the color display device shown in this figure converts the color data R, G, B into luminance data and color difference data and stores them in the VRAM. The data is read, the color data R, G, B are reproduced, and display is performed based on the reproduced color data R, G, B.

More specifically, in the figure, 1 is a CPU, 2 is a CPU 1
Is a memory including a ROM storing a program used in and a RAM for storing data. DC is a display controller, which outputs a control signal to each part of the device under the control of the CPU 1 and also has a VRAM 21.
Write / read address AD is output to. 3 is a terminal to which a composite video signal CV is input, 4 is a composite video signal CV, which is converted into color data R, G, B,
This is a well-known decoder that sequentially outputs at the timing of the dot clock DCLK. In this embodiment, the color data R, G, B are each 5 bits. The dot clock DCLK is a clock pulse at the same timing (cycle) as the display of each dot on the CRT display device 7.

A data conversion circuit 5 converts color data R, G, B into luminance data Y and color difference data U, W, and performs data conversion based on the following equation.

Y = (1/4) R + (1/8) G + (1/2) B = (1/8) (2R + G + 4B) …… (1) U = R−Y …… (2) W = G−Y… (3) FIG. 2 is a diagram showing a specific configuration of the data conversion circuit 5, in which 6 and 7 are 8-bit full adder circuits and 8 and 9 are 6-bit full subtraction circuits, respectively. Circuit, 10-1
Reference numeral 8 is a parallel-in / parallel-out register.
Further, the terminal T1 is a terminal for supplying the dot clock DCLK from the display controller DC, T2 to T4 are terminals for supplying the color data R, G, B from the decoder 4, respectively.
5, T7 are terminals for outputting color difference data U and W, respectively, and T6
Is a terminal for outputting the luminance data Y. Here, the color data R, G, B and the luminance data Y are 5-bit positive integers, the color difference data U, W are 6-bit positive or negative integers, and the negative numbers are expressed by "2's complements". There is.

Next, the operation of the data conversion circuit 5 will be described with reference to the timing chart of FIG. Now, after the time t0 shown in FIG. 3, color data (r ₁ , g ₁ , b ₁ ), (r ₂ , g ₂ , b ₂ ), etc. for each cycle of the dot clock DCLK ((a) in the figure) ... ... are sequentially supplied in parallel to the terminals T2, T4, T3 (see FIG.
(B)). First, at time t0, the adder circuit 6 outputs data (4b ₁ + g ₁ ) as shown in FIG. Here, the data 4b ₁ is obtained by shifting the data b ₁ in the upper direction by 2 bits and inputting it to the adder circuit 6. At time t1, the registers 10 to 12 have data r ₁ , (4b ₁ +
g ₁ ) and g ₁ are output ((d), (e), (f) in the figure). further,
Adder circuit 7 for adding the output data of the registers 10 and 11
Outputs data (4b ₁ + g ₁ + 2r ₁ ). Here, the data r2 ₁ is obtained by shifting the data r1 upward by 1 bit and inputting it to the adder circuit 7.

At time t2, the registers 13 to 15 have data r ₁ ,
(1/8) (4b ₁ + g ₁ + 2r ₁ ) and g ₁ are output. Adder circuit 7
(1/8) (4b ₁ + g ₁ + 2g ₁ ) is obtained by inputting only the lower 3 bits of the output data of 1 to the register 14. At this stage, the luminance data described above was obtained.
This brightness data is y ₁ .

(1/8) (4b ₁ + g ₁ + 2r ₁ ) = y ₁ (4) Then, the subtraction circuits 8 and 9 respectively output the data (r ₁ −y ₁ ), (g ₁
-Y ₁ ) is output ((l) and (e) in the figure). Where the second
As is clear from the equations (2) and (3), the output data of the subtraction circuits 8 and 9 are color difference data, and these color difference data are u ₁ and w ₁ , respectively.

r ₁ −y ₁ = u ₁ (5) g ₁ -y ₁ = w ₁ (6) Next, at time t3, the registers 16 to 18 have color difference data u ₁ , luminance data y ₁ , and color difference data respectively. The data w ₁ is output and supplied from the terminals T5 to T7 to the write data forming circuit 20 of FIG. 1 ((W), (F), (Y) in the same figure. Hereinafter, similarly, the dot clock DCLK rises. Terminals T5 to T7 for each
To color difference data and luminance data (u ₂ , y ₂ , w ₂ ),
(U ₃ , y ₃ , w ₃ ) ... are output sequentially.

The write data forming circuit 20 forms data to be written in the VRAM 21. The color difference data U and W and the luminance data Y output from the data conversion circuit 5 are not stored in the VRAM as they are, but are stored after being compressed by the write data forming circuit 20.

Here, a method of data compression will be described. The human eye has the property that it is impossible to distinguish colors in a small area. Therefore, for example, even if the same color difference data that is averaged for four consecutive dots is assigned, there is no visually noticeable difference compared to the case where independent color difference data is assigned to each dot. The write data forming circuit 20 receives the color difference data U, V from the data converting circuit 5.
Each time 4 data items are received, the 4 data items are averaged, and the average value and the 4 brightness data items form the data to be written in the VRAM. FIG. 4 is a diagram showing the structure of write data. In this figure, y _{1 to} y ₄ are luminance data (5 for each).
, U′h, u′l are the upper 2 bits and the lower 4 bits of the average value u ′ of the _four color difference data u _{1 to} u ₄ input together with the luminance data y _{1 to} y ₄ , respectively, and w ′ H, w′l,
Four color difference data w ₁ input together with luminance data y _{1 to} y ₄
~ Upper 2 bits and lower 4 bits of the average value of w ₄ . Then, the write data thus formed is sequentially stored in the VRAM 2 from the address B0 indicating the storage position of 1 byte.
It is output to 1.

If the luminance data Y and the color difference data U and W are written in the VRAM as they are, (5 + 6 + 6) × 4 = 68 bits are required for 4 dots, but according to the above data compression, 8 × 4 = It will be 32 bits.

FIG. 5 is a circuit diagram showing a specific configuration of the write data forming circuit 20 described above. In this figure, reference numeral T10
.About.T12 are terminals to which the color difference data U, the luminance data Y, and the color difference data W are supplied from the data conversion circuit 5, respectively.
T17 is a terminal to which the clock pulse UWCLK, dot clock DCLK, clock pulse UWCLKa, select signals TC1 and TC0 are supplied from the display controller DC, and T18 is a terminal to which 8-bit write data supplied to the VRAM 21 is output. . Dot clock DCLK, clock pulses UWCLK, UWCLK
a, select signals TC0 and TC1 are respectively shown in FIGS. 6 (a) to 6 (e).
Shown in. Here, the clock pulse UWCLK is a clock pulse obtained by dividing the dot clock DCLK by 1/4, and the clock pulse UWCLKa is the clock pulse UWCLK.
Is a clock pulse with a slight delay. The select signals TC0 and TC1 are clock pulses UWCL.
At the rising edge of K, it becomes "0, 0", and thereafter at the rising edge of the dot clock DCLK, "1,"
It is a signal that sequentially changes from 0 "," 0, 1 "," 1, 1 "," 0, 0 "....

Reference numerals 23 and 24 denote averaging circuits, which accumulate four color difference data U and W, which are sequentially supplied, to obtain 1 /
4 is output. FIG. 7 is a circuit diagram showing the configuration of the averaging circuit 23. In this figure, 25 is an 8-bit parallel-in / parallel-out register, and 26 is an 8-bit adding circuit. First, the register 25 outputs the clock pulse UW.
It is reset to "0" by CLKa. Next, the data in the register 25 (“0” in this case) and the color difference data U are added by the adder circuit 26, and the addition result is registered in the register 25 when the dot clock DCLK rises.
Write to. Further, the addition result of the adder circuit 26 is shifted by 2 bits in the lower direction (that is, ¼) and output. The above shift processing means that the upper 6 bits of the adder circuit 26 are output. Next, the written data and the next color difference data U are added in the adder circuit 26. This operation is repeated four times to obtain the accumulation result of four color difference data U. The lower 2 bits are rounded down to 1/4. Since the signal TC0 is supplied to the carry input C0 of the least significant bit of the adder circuit 26,
The results are rounded off at the average of / 4. The averaging circuit 24 also has the same configuration as the above averaging circuit 23.

Next, reference numerals 30 to 35 in FIG. 5 denote parallel in / parallel out registers, data is written to the registers 30 to 33 at the rising edge of the dot clock DCLK, and data is written to the registers 34 and 35 at the rising edge of the clock pulse UWCLK. Be done. Reference numerals 36 and 37 denote selectors, which are input terminals <0> based on the select signals TC0 and TC1.
~ Select one of the data <3> and output from the output end.

Next, the operation of the write data forming circuit 20 described above
A description will be given with reference to the timing chart in the figure. The averaging of the color difference data w operates in the same way as the color difference data u, and therefore its description is omitted.

First, at time t11, the dot clock DCLK rises, and at this rise, terminals T10 to T12
It is assumed that the color difference data u ₁ , the luminance data y ₁ , and the color difference data w ₁ are supplied to the respective color difference data (FIG. 6 (f)). At this time, the clock pulse UWCLK rises at the same time, and shortly thereafter, the clock pulse UWCLKa rises. Clock pulse U
When WCLKa rises, the register 25 shown in FIG. 7 is cleared and its output data becomes "0". As a result,
The adder circuit 26 calculates “u ₁ +0”.

Next, at time t12, the respective color difference data u ₂ to terminals T10 to T12, the luminance data y _2, color difference data w ₂ appears (Sixth
(Figure F)). The output u _{1 of the} register 25 and the color difference data u ₂ are added. Also, the dot clock DCL at time t12
At the rising edge of K, the brightness data y ₁ is written in the register 30. Thereafter, the same processing is performed at times t13 and t14, and the luminance data y ₁ is sequentially shifted from the register 31 to the register 32.

Next, at time t15, the color difference data u ₅ , the luminance data y ₅ , and the color difference data w ₅ are supplied to the terminals T10 to T12, respectively. At this time, at the same time, the clock pulse UWCLK rises,
A short time after this, the clock pulse UWCLKa rises. When the dot clock DCLK rises, the output data y ₁ of the register 32 is written in the register 33. Further, at the rising edge of the clock pulse UWCLK, the output data of the averaging circuits 23 and 24 "(u ₁ + u ₂ + u ₃ + u ₄ ) /
4 ”and“ (w ₁ + w ₂ + w ₃ + w ₄ ) / 4 ”(see FIGS. 6 (g) and 6 (h)) are written in the registers 34 and 35, respectively. Hereinafter, the same operation is repeated.

As described above, in the write data forming circuit 20 shown in FIG. 5, the average value of the color difference data U and W is written to the registers 34 and 35 each time four data are supplied (that is, every four dot clocks). , On the other hand, luminance data Y
Registers 30 to 33 according to the dot clock DCLK
Are sequentially shifted. Then, the output data of the register 33 is output from the terminal T18 to the VRAM 21, and
Each bit of the output data of the registers 34 and 35 is selected by the selectors 36 and 37, and the selected data is output from the terminal 18 to the VRAM 21 (see FIG. 4).

That is, first, at time t15 in FIG. 6, the data y ₁ is output from the register 33 and supplied to the 0th to 4th bits of the terminal 18. Further, at this time, as shown in FIGS. 6 (d) and 6 (e), the select signals TC0, TC1 are "0, 0", respectively. As a result, the output data of the register 34 from the selector 36 is “(u ₁ + u ₂ + u ₃ + u ₄ ) / 4 =
u _'1 "fourth bit data is output, is supplied to the fifth bit of the terminal T18, also from the selector 37, output data u of the register 34' output of the 0-bit data and the register 35 of ₁ Data “(w ₁ ＋ w ₂ ＋ w ₃ ＋ w ₄ ) / 4
= W ' ₁ 0th bit data is output respectively at terminal T18
Are supplied to the 6th and 7th bits of. On the other hand, at this time, the display controller DC (FIG. 1) outputs the address AD of the VRAM 21. As a result, the data of the terminal T18 described above is written in the VRAM 21. Next, time t in FIG.
When it becomes 16, the luminance data y ₂ becomes 0th to 4th of the terminal T18.
Supplied to bits. In addition, select signals TC0, TC
1 becomes “1,0” respectively, and therefore the selector 36
Outputs the fifth bit data of the output data u ′ ₁ of the register 34 and supplies it to the fifth bit of the terminal T18, and the selector 37 outputs the first bit of the output data u ′ ₁ of the register 34. And the data of the first bit of the data w ′ ₁ output from the register 35 are output and supplied to the sixth and seventh bits of the terminal T18. Then, the data of the terminal T18 is written in the VRAM 21 based on the address AD output from the display controller DC. Thereafter, the same process is repeated, and the data is written in the VRAM 21 as shown in FIG.

The above is the details of the write data forming circuit 20. next,
The RGB data reproducing circuit 40 shown in FIG. 1 is a circuit for reproducing the luminance data Y and the color difference data U ′, W ′ read from the VRAM 21 at the timing of the dot clock DCLK into the color data R, G, B. I am calculating.

R = Y + U '... (7) G = Y + W' ... (8) B = (5/4) Y- (1/2) U '-(1/4) W' = (1/4) {5Y − (2U ′ + W ′)} (9) In these equations, U and W in equations (1) to (3) above are set as U ′ and W ′, respectively, and solved by R, G, and B. Required by Further, in these equations (7) to (9), since only equation (9) includes division, the conversion error appears only in blue (B). However, since the human eye is most insensitive to a slight hue change in which blue is mixed, the effect of conversion error can be minimized according to this conversion formula.

FIG. 8 is a circuit showing the details of the RGB data reproducing circuit 40. In this figure, T21 and T23 are terminals for the dot clock DCLK and the clock pulse 4XCLK output from the display controller DC, respectively. here,
The clock pulse 4XCLK is a clock pulse obtained by dividing the dot clock DCLK into quarters as shown in FIG. T22 is a terminal that supplies data read from the VRAM 21, and T24 to T26 are terminals that output color data B, R, and G, respectively. Reference numerals 41 to 45 are parallel in / parallel out registers for reading input data based on the dot clock DCLK, and 46 to 48 are parallel in / parallel out registers for reading input data based on the above-described clock pulse 4XCLK. Further, 49 to 53 are addition circuits, 54 is an inverting circuit that inverts and outputs each bit of input data, 55 to 5
9 is an exclusive OR gate.

Next, the operation of the RGB data reproducing circuit 40 will be described with reference to FIG. Now, at the rising times t21 to t24 of the dot clock DCLK shown in FIG.
Assume that the bytes B0 to B3 shown in FIG. 4 are sequentially read from the VRAM 21 and supplied to the terminal T22 (see FIG. 9C). In this case, each data is sequentially shifted in the registers 41 to 43 by the dot clock DCLK (9th
(Fig. (D), (e), (f)). Then, at time t24, when the register 43 outputs the luminance data y ₁ , this luminance data
y ₁ is supplied to the first input terminal of the adder circuit 49, and 4
It is multiplied and supplied to the second input terminal of the adder circuit 49. As a result, the data 5y ₁ is output from the adder circuit 49 and supplied to the input terminal of the register 44 (FIG. 9 (g)). Further, at the same time t24, when the respective data of the bytes B0 to B3 of FIG. 4 are output from the registers 43, 42, 41 and the terminal T22, the input end of the register 46 and the adder circuit 5 are added.
The color difference data u'composed of the data u'h and u'l of FIG. 4 is supplied to the first input terminal of 0, and similarly to the input terminal of the register 47 and the second input terminal of the adder circuit 50. , Color difference data composed of the data w′h and w′l in FIG.
w'is supplied. In this case, the data u'is shifted by 1 bit (doubled) and supplied to the adder circuit 50. As a result, the data (2u '+ w') is output from the adder circuit 50 (Fig. 9 (h)). It is supplied to the register 48.

Next, at time t25, the dot clock DCLK rises and the clock pulse 4XCLK rises. When the dot clock DCLK rises, the output data 5y ₁ of the adder circuit 49 is read into the register 44,
Further, the luminance data y ₁ output from the register 43 is read into the register 45 (FIG. 9 (i), (n)). When the clock pulse 4XCLK rises, the color difference data u ', w'and the data (2u' + w ') are read into the registers 46 to 48, respectively (Figs. 9 (l), (e),
(Wa)). When the output data of the register 44 is supplied to the first input terminal of the subtraction circuit 51 and the output data of the register 48 is inverted by the inversion circuit 54 and supplied to the second input terminal of the subtraction circuit 51, the subtraction circuit 51 outputs the data. The data (1/4) {5y ₁ − (2u ′ + w ′)} (10) is output (Fig. 9 (f)). As is clear from the comparison between the equation (10) and the equation (9), the output of the subtraction circuit 51 is the color data B. Further, to the first input terminal of the output data addition circuit 52 of the register 45, the output data of the register 46 are respectively supplied to the second input of the adder circuit 52, the adder circuit 52, y ₁ + u '...... The data of (11) is output (Fig. 9 (Yo)). This data is the color data R as is clear from the equation (7).
Similarly, the output data of the register 45 is input to the first input terminal of the adding circuit 53, and the output data of the register 47 is output to the adding circuit 53.
When they are respectively supplied to the second input terminals of, the adder circuit 53 outputs the data y ₁ + w '... (12) (FIG. 9 (T)). This data is the color data G as is clear from the equation (8).

Thus, at time t25, the luminance data y ₁ and the color difference data u ′, w ′ are converted into color data B, R, G and output from the adder / subtractor circuits 51-53. Similarly, at times t26, t27, and t28, the luminance data y ₂ ,
y ₃ , y ₄ and color difference data u ′, w ′ are color data B,
It is converted into R and G and output from the adder / subtractor circuits 51 to 53. On the other hand, from the time t25 to t28, the terminal T2
The following 4 data are sequentially supplied to 2 and these data are sequentially read into the registers 41 to 43. And time t
At 29 to t32, color data B, R, and G based on these data are sequentially output from the adder / subtractor circuits 51 to 53, and this process is repeated.

Next, the output of the subtraction circuit 51 is supplied to the terminal T24 through the exclusive OR gates 55 to 59, and
The outputs of the adding circuits 52 and 53 are supplied to the terminals T25 and T26, respectively. Where the exclusive or gate 55
.About.59 are provided for cases where the subtraction result of the subtraction circuit 51 overflows or underflows. That is, first, when the subtraction result of the subtraction circuit 51 does not overflow or underflow, the subtraction circuit 51
Since the signal at the output terminal S8 of the above is "0", the exclusive OR gates 55 to 59 are in the through state. On the other hand, when the subtraction result overflows and the signal at the output terminal S8 is "1" and the signals at the other output terminals S3 to S7 are "0", the exclusive OR gates 55 to 59 are provided.
Operates as an inverter, and data "11" is applied to terminal T24.
111 "is also supplied. Also, when the subtraction result underflows and the signal of the output terminal S8 and the signals of the other output terminals S3 to S7 all become" 1 ", the exclusive OR gates 55 to 55 are supplied. 59 operates as an inverter, and terminal T
The data “00000” is supplied to 24. The error is ± 1
It's just that.

Next, the color data R, G, B respectively output from the terminals T25, T26, T24 described above are supplied to the DACs (digital / analog converters) 56, 57, 58 in FIG. The DACs 56 to 58 are color data R, G, B.
Is converted into an analog color signal and output to the CRT display device 7. The CRT display device 7 includes the synchronization signals SYNC and DACs 56 to 58 output from the display controller DC.
Color dot display is performed based on the color signal output from the.

The above is the details of the embodiment of the present invention. Although the format of the data written in the VRAM 21 is shown in FIG. 4 in the above embodiment, it may be, for example, the format shown in FIG.

In the circuit of FIG. 2, (4B + G + 2R) /
Although the decimal point or less in the calculation of 8 is rounded down, it may be rounded off. When this rounding is performed, the calculation of (4B + G + 2R + 4) is performed, and this calculation result may be divided by 8. Similarly, in the circuit of FIG. 8 as well, the fractional part in the calculation {5Y- (2U '+ W')} / 4 is rounded down, but it may be rounded off. In this case, {5Y- (2U '+ W')
The calculation of +2} / 4 may be performed.

By the way, the display device according to the above embodiment has a problem when performing overwriting. That is, in computer graphics or the like, the first image may be used as a background and the second image may be displayed on top of it. In this case, the color data R, G, and
When B is stored, the color data in the storage area corresponding to the second image in the VRAM may be rewritten, but when one color difference data is stored for every 4 dots as in the above embodiment, It becomes impossible to rewrite every dot. In this case, of course, it is possible to rewrite data in units of 4 bits, but in such rewriting,
The resolution of the second image becomes low. Next, another embodiment in which the problem in this overwriting is solved will be described.

FIG. 11 is a diagram showing a format of write data in the embodiment. This format is different from that shown in FIG. 4 in that the 0th bit of each byte B0 to B3 is the attribute bit ATR and the luminance data Y is 4 bits. Then, in the same manner as in the above embodiment, when an image is displayed by the luminance data Y and the color difference data U and W, the attribute bit A
TR is set to "0". When the color of some dots is changed (in the case of overwriting), the color code CC is written instead of the brightness data Y of the dot, and the attribute bit ATR is set to "1".

FIG. 12 is a diagram showing the configuration of the RGB data reproducing circuit 40 in the case of this embodiment, in which the RGB data forming circuit 60 is the same as the circuit constituted by the components 49 to 59 in FIG. Circuit. That is, this circuit has a configuration in which the register 62, the color lookup table 63, and the selector 64 are added to the circuit of FIG. Here, the register 62 is a dot clock DCL.
The color lookup table 63, which is a register that reads data at the rising edge of K, is a table that converts the color code CC output from the register 62 into color data R, G, and B. Further, the selector 64 outputs the color data R, G, B output from the RGB data forming circuit 60 to the terminals T25, T26, T24 when "0" is supplied to the select terminal SE, and also selects. When "1" is supplied to the terminal SE, the color data R, G, B output from the color look-up table 63 is output.
To terminals T25, T26, T24. The above-mentioned attribute bit ATR is supplied to the select terminal SE of the selector 64.

When the attribute bit ATR is "0", "0" is supplied to the select terminal SE of the selector 64, so that the color data R, G, B output from the RGB data forming circuit 60 is the selector 64. Is supplied to terminals T25, T26, T24 via. That is, in this case, the operation is the same as that of the circuit of FIG. On the other hand, when the attribute bit ATR is "1", the color code CC written in place of the luminance data Y is supplied to the color lookup table 63 via the register 62, where the color data R, G, B And the color data R, G, B are converted to terminals T25,
It is supplied to T26 and T24. As a result, dots are displayed in the color corresponding to the color code CC.

[Advantages of the Invention] As described above, according to the present invention, since the average values of the color difference data U and W are obtained and stored in the memory, the memory capacity can be reduced. Further, according to the present invention, "red-luminance" color difference data U and "green-luminance"
Since the "luminance" color difference data W is used, the conversion error concentrates on the blue color, so that the influence of the conversion error can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention,
FIG. 2 is a circuit diagram showing details of the data conversion circuit 5 in the embodiment, FIG. 3 is a timing diagram for explaining the operation of the data conversion circuit 5, and FIG. 4 shows a format of data written in the VRAM 21. 5 and 5 are circuit diagrams showing details of the write data forming circuit 20 in the embodiment, FIG. 6 is a timing diagram for explaining the operation of the write data forming circuit 20, and FIG. 7 is the same write data forming. A circuit diagram showing a configuration of an averaging circuit 23 in the circuit 20,
FIG. 8 is a circuit diagram showing the details of the RGB data reproducing circuit 40 in the embodiment, and FIG. 9 is the RGB data reproducing circuit 4 in the same.
0 is a timing chart for explaining the operation of 0, and FIG.
FIG. 11 is a diagram showing another format of the write data of the RAM 21, FIG. 11 is a diagram showing the format of the write data in another embodiment of the present invention, and FIG. 12 is a block showing the configuration of the RGB data reproducing circuit 40 in the same embodiment. It is a figure. 5 ... Data conversion circuit, 7 ... CRT display device, 20 ...
... write data forming circuit, 21 ... VRAM, 23, 2
4 ... Averaging circuit, 40 ... RGB data reproducing circuit.

Claims (2)

[Claims] 1. In a color display device for displaying (a) color dots, (b) color information indicating a color of each dot is displayed as luminance data Y.
And a conversion means for converting the "red-luminance" color difference data U and the "green-luminance" color difference data W, and (c) an operation for calculating an average value of each of the color difference data U and W for each plurality of dots. A color display device comprising: a means for writing the average value of the color difference data U and W and the luminance data Y in a memory. 2. In a color display device for displaying (a) color dots, (b) color information indicating a color of each dot is a luminance data Y and an average value of "red-luminance" color difference data U, A memory stored by the average value of the "green-luminance" color difference data W; and (c) conversion means for reading the data from the memory and converting the read data into red green blue color data R, G, B. d) A color display device comprising: display means for displaying color dots based on the color data R, G, B.