JPH0269091A - Color display device - Google Patents

Abstract

PURPOSE:To prevent an erroneous display caused by an error in digital calculation by setting all bits of calculated results to '1' when an overflow occurs and to '0' when negative data are produced in the course of calculation for returning to color data. CONSTITUTION:When an overflow occurs in output data of adder circuits 21-23, data of 'All 1' are outputted from terminals T4-T6. When the output data of the adder circuits 21-23 become negative data, data of 'All 0' are outputted from the terminals T4-T6. Color data R, G, and B outputted from the terminals T4-T6 are respectively supplied to DACs 70, 71, and 72. A CRT display device 8 performs a color dot display based on a synchronizing signals SYNC outputted from a display controller DC and color signals outputted from the DACs 70-71. Therefore, display of high-luminance dots in a low-luminance state and low- luminance dots in a high-luminance state can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a color display device in which color image information is stored in a VRAM (video RAM) using luminance data and color difference data.

``Prior Art'' A display device that displays color dots using a CRT display device has been developed in which dot data consisting of luminance data and color difference data is stored in a VRAM.

This display device displays color data fl, G.

For example, let B be Y = 0/4)n + (t,/s)G + (1/
2) B= (1/8) (2rt + G + 4B)
・・・・・・(1) u=rt−y ・・・
...(2) W=G-Y ......(3) Luminance data Y and color difference data U, W based on the formula
Convert to Next, for example, calculate the average values U' and W' of the color difference data U and W for every four consecutive dots, and calculate this average value U
', W' and brightness data Y are stored in VrlAM. In other words, for brightness data, V
The color difference data is stored in the RAM, and one data is stored for every four dots. The reason for doing this is to limit the capacity of the VRAM, and since the human eye is highly sensitive to changes in color difference, even if you do this, the color will not appear significantly different from the original color. .

Next, at the time of display, each of the above data Y, U', W' is read from the VRAM, and these data y, u',
w', R=Y+U' ・・・・・・(4) G=Y+W'
・・・・・・(5) B = (5/4) Y −(
1/2) U'-(1/4)W.

= (1/4) (5Y - (2U' + W'))
. . . Based on the formula (6), the color data R, G, [() are returned, and the color data RG, B are converted into analog signals and output to the CRT display device.

"Problem to be Solved by the Invention" By the way, the color data R, G, and 13 before being recorded fα in VrlAM are each positive data. therefore,
The luminance data Y calculated by the above equation (1) is positive data. However, the color difference data U, W and their average values U'', Wo calculated by the above equations (2) and (3) can each take on both positive and negative values.

Then, from these data Y, U'', W', the above (4th
) to color data R, C;, I(
When , the calculated color data R, G, and B should all be positive data.

However, when the calculations of the above-mentioned equations are performed by digital circuits, errors inevitably occur, and as a result, data that should originally be positive may end up being negative data. In this case, since the circuit configuration is not normally based on negative data, the data will be completely different in value from the original data, and dots that should be displayed with low brightness will be displayed with high brightness.

In addition, if the color data R, G, and B are, for example, 5 pits, the data Y, U'', and W° calculated by performing the calculations of equations (1) to (3) are stored in the VRAM. The data Y, U', W' are read out, and the (4th) to (6th) data are read out.
) calculation is performed to obtain the original color data R, G.

If the color data is returned to B, the color data R, G, and B should become 5-bit data. However, since there are errors based on the digital calculations mentioned above,
6) Overflow may occur due to calculation of expressions. In this case as well, since the circuit configuration is based on 5 bits, the data will have a completely different value from the original data, and dots that should be displayed with high brightness will be displayed with low brightness.

An object of the present invention is to provide a color display device that can prevent erroneous display due to the above-mentioned digital calculation errors.

"Means for Solving the Problem" This invention provides a first data conversion means that changes each bit of the calculation result to "!" when the calculation result in the calculation means exceeds a predetermined number of bits; and second data conversion means for changing each bit of the calculation result to "O" when the calculation result is negative.

"Operation" According to this invention, in the calculation to return to color data,
When an overflow occurs, all bits of the operation result are set to "1", and when negative data occurs, all bits of the operation result are set to "0". This can prevent high-brightness dots from being displayed with low brightness, or conversely, preventing low-brightness dots from being displayed with high brightness.

"Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the same embodiment. The color display device shown in this figure converts color data R, G, and B into luminance data and color difference data, and converts color data R, G, and B into luminance data and color difference data.
Store it in RAM and read this stored data,
Regenerate color data R2G, B, and reproduce color data R, G.

It is designed to serve as a display based on B.

To explain in detail below, in the figure, 1 is a CPU (central processing unit), and 2 is a memory consisting of a ROM in which programs used in the CPUI are stored and a RAM for data storage. DC is a display controller, which outputs control signals to each part of the device under the control of the CPUI, and also outputs a write/read address AD to the VRAM 7.

3 is a terminal to which a composite video signal CV is input; 4
represents a composite video signal Cv, color data RG,
This is a well-known decoder that converts the signal to H and sequentially outputs it at the timing of the dot clock DCI.

Note that in this embodiment, color data R1G, B
are each 5 bits. Also, dot clock DC
LK is a clock pulse having the same timing (period) as the display of each dot on the CRT display device 8.

Reference numeral 5 denotes a data conversion circuit that converts color data R, G, B into luminance data 71 and color difference data U, W, and performs data conversion based on the above-mentioned equations (1) to (3).

The write data forming circuit 6 is a circuit that forms data to be written into the VRAM 7. In this embodiment, the color difference data U, W and luminance data Y output from the data conversion circuit 5 are not stored in the VRAM 7 as they are, but are compressed in the write data forming circuit 6 and then stored. That is, the write data forming circuit 6 receives the color difference data U and W from the data conversion circuit 5.
Each time the data is received, the average of the four data is taken, and this average value and the four luminance data form data to be written to the VRAM. FIG. 2 is a diagram showing the structure of write data. In this figure, Y I - Y a is luminance data (5 bits each), U''h, u'Q are luminance data Y I
-Four color difference data u 1 ” input together with Y 4
” The upper 2 bits and lower 4 bits of the average value U° of u 4, and w'h and w'12 are the luminance data Y
Four color difference data W, ~w input together with l-'14
These are the upper 2 bits and lower 4 bits of the average value of 4.

The write data thus formed is sequentially output from the byte BO shown in FIG. 2, and is sent to the display controller D.
VRAM based on the address AD supplied p++ from C.
7 is written.

Note that if the luminance data Y and color difference data U and W are written as they are to the VRAM, (5+6+6)
4=68 bits are required, but according to the data compression described above, 8X4=32
Bits will suffice.

Next, the RGB data reproducing circuit IO converts the luminance data Y and color difference data U', W" read from VrtAM7 at the timing of the dot clock DCLK into color data R based on the above-mentioned equations (4) to (6). ,G,H
This is the circuit that returns it to .

FIG. 3 is a circuit diagram showing details of this RGB data reproducing circuit IO. In this figure, Tl and T2 are terminals to which the dot clock DCLK and clock pulse 4XCLK output by the display controller DC are respectively supplied. Here, the clock pulse 4XCLK is a clock pulse obtained by dividing the dot clock DCLK into 1/4 as shown in FIG. 4(b). T3 is a terminal to which data read from VI'tAM7 is supplied, and T4 to T6 are each
This is a terminal to which color data B, R, and G are output. 1
1-15 is a parallel in/parallel out register that reads input data based on the dot clock DCLK;
16 to 18 are parallel in/parallel out registers that read manual data based on the above-mentioned clock pulse 4XCLK. Also,! 9 to 23 are adder circuits, 24
numerals 27 to 29 are inverters, 31 to 45 are OR gates, and 46 to 60 are AND gates.

Next, the operation of this RGB data reproducing circuit 10 will be explained with reference to FIG. Now, assume that bytes BO to B3 shown in FIG. 2 are sequentially read out from the VRAM 7 and supplied to the terminal T3 at rising times t21 to t24 of the dot clock DCLK shown in FIG.
(See C). In this case, each data is dot clock DC
Registers 11 to 13 are sequentially shifted by LK (
4), (E), (Heno. Then, at time [24], when the register 13 outputs the luminance data y1, this luminance data y is transmitted to the input terminals 31 to B5 of the adder circuit 19.
It is also supplied to the input terminals A3 to A7 of the adder circuit 19 (multiplied by 4 (shifted by 2 bits in the upper direction)).
As a result, data 5yI is supplied from the adder circuit I9.
is output and register! 4 input terminal (4th
Figure (g)). Also, at the same time t24, register 1
3, 12.11 and terminal T3 to byte BO in Figure 2
~ When each data of B3 is output, the register! Color difference data U'' consisting of data u'h and u'Q in FIG. The color difference data W consisting of the data v'h and w' (7) shown in FIG. ) is supplied to the adder circuit 20. As a result, the adder circuit 20 outputs data (2umov') (Fig.
Each bit of w') is inverted by the inverting circuit 24, resulting in data r-(2u'+w')J, which is supplied to the register 8.

Next, at time t25, the dot clock DCLK rises and the clock pulse 4XCLK rises. When the dot clock DCLK rises, the output data 5Y+ of the adder circuit 19 is read into the register 4, and the luminance data y output from the register 3 is read.
l is read into register 5 (Fig. 4(su), (nuno). Also, when clock pulse 4
Color difference data u', w' and data "-(2n'+w')J" are read into registers 6 to 18, respectively (Fig. 4 (L), (O), (W)). Then, the output of register 4 The data is sent to the input terminal Al-A3 of the adder circuit 21, and the output data of the register 8 is sent to the input terminal B of the adder circuit 21.
1-88, the adder circuit 21 outputs the data (1/4)(5yl-(2u'+v')L・-(
7) is output (Figure 4 (force)). Furthermore, (1/4)
is performed by shifting the output of the adder circuit 21 by 2 bits in the lower direction. As is clear from a comparison between this equation (7) and the above equation (6), the output of the adder circuit 2I is color data B. Further, the output data of the register 15 is sent to the input terminal Al-A3 of the adder circuit 22, and the output data of the register 16 is sent to the input terminal Bl-A3 of the adder circuit 22.
When each is supplied to B7, the adder circuit 22 outputs the data y, +u... (8) (Fig. 4). This data is clear from equation (4) above. Similarly, when the output data of the register 15 is supplied to the input terminal Al-A3 of the adder circuit 23, and the output data of the register 17 is supplied to the input terminals I31 to B7 of the adder circuit 23, The adder circuit 23 outputs the following data: y, +v (9) (Fig. 4 (evening)). This data is color data G as is clear from equation (5) above. .

In this way, at time t25, the luminance data Y and color difference data u'4' are converted into color data I3, R, and G, which are output from the addition/subtraction circuits 21-23. Similarly, at times t26 to t27 and L28, the luminance data Yt+Y*+Ya and the color difference data u', w' are converted into color data B, R, G, and the adder circuits 21 to 2
Output from 3. On the other hand, from time t25 to L28, the following four data are sequentially supplied to the terminal T3, and these data are sequentially read into the register ll-13.

Then, from time t29 to t32, based on these data (color data B).

IN and G are sequentially output from adder circuits 21 to 23, and this process is repeated thereafter. And adder circuits 21 to 2
If each output data of 3 does not overflow 5 bits and does not have a negative value, each data is supplied to terminals T4 to T6 via OR gates 31 to 45 and AND gates 46 to 60. and these terminals T 4
- Output from T6 to the next stage.

Next, a case where the output data of the adder circuits 21 to 23 overflows 5 bits or becomes negative data will be explained. First, the case of the adder circuit 22 will be explained.

First, the luminance data Y output from the register 15 is positive 5-bit data, and is input to the input terminal A1 of the adder circuit 22.
~A5 is supplied. Further, the color difference data U° outputted from the register 16 is 6-bit data, and the most significant bit is a sign bit (“0” → positive, “1” → negative), and is connected to the input terminal of the adder circuit 22. B! ~B6 is supplied. Further, the sign bit supplied to input terminal B6 is supplied to input terminal B7. Also, the output terminal S! of the adder circuit 22! ~S5 is Or Gate 40~
36 and terminal T5 via AND gates 55-51.
The output terminal S6 is connected to one input terminal of each of OR gates 40 to 3G, and the output terminal S7 is connected to one input terminal of each of AND gates 55 to 51 via an inverter 28.

Next, the operation of the circuit portion with the above configuration will be explained.

(1) When data U' is positive (I36.B7="0")
In this case, the addition result of the addition circuit 22 will never become negative data. Normally, the addition result is 5 bits, and the output terminal S6 . S7 is “0” Inverter 2
The output of 8 is "1". Therefore, Orgate 4
0 to 36 and AND gates 55 to 51 are all in the through state and serve as addition ports.

The data at the output terminals 81 to S5 of the line 22 is sent directly to the terminal T.
5.

Next, when an overflow occurs, the output terminal S6 of the adder circuit 22 becomes "1" (the output terminal S7 becomes "O"). When this output terminal S6 becomes "L", OR gate 40~
Each output of 36 becomes “!”, and the data “1.1, l
, 1.1'' are supplied to terminal T5.

(2) When data U° is negative (B6.B7="1") Also in this case, the addition result is normally 5-bit positive data, and the output terminals S6. Both S7 become "0", and the data of the output terminals 81 to S5 are supplied as they are to the terminal T5.

Next, if the addition result is negative, output terminal S6. S
Both 7 become "1". Then, the output terminal S7 is “1”
As a result, the output of the inverter 28 becomes "0", and therefore each output of the AND gates 55 to 51 becomes "0".
0” and the data “0,0°0.0.0” is output to terminal T5.
supplied to

The operations of the adder circuit 23, OR gates 45 to 41, AND gates 60 to 56, and inverter 29 are also similar to those described above.

Next, the addition circuit 21 will be explained. First of all, always
The output of this adder circuit 21 is positive 7-bit data. In this case, output terminal S8 and carrier terminal CO
are both at “0”, and the data at output terminals 5t-S7 is set to 1.
/4 data, that is, the data at the output terminals 83 to S7 are output to the OR gates 35 to 31 and the AND gate 50.
~46 to the terminal T4.

Next, when an overflow occurs in the addition result, the output terminal S8 becomes "L", and therefore the OR gate 3
Each output of 5 to 31 becomes °1", and the data "I, I
, l, 1. , 1'' are supplied to terminal T4.

Furthermore, if the addition result is negative data, "1" is output from the carrier terminal CO, and therefore each output of the AND gates 50 to 46 becomes 102.
Data "o, o, o, o, o" is supplied to the terminal T4.

In this way, when an overflow occurs in the output data of the adder circuits 21 to 23, A(lQ
“1° data is output, while adder circuits 21 to 2
If the output data of 3 becomes negative data, the terminal T4
~A(IQ "0" data is output from T6.

Next, the color data R, G, B output from the terminals T4 to T6 mentioned above are transferred to the DAC (digital/
analog converter) 70, 71, and 72.

The DACs 70 to 72 convert the color data R1G and R1B into analog color signals and output them to the CRT display device 8. C
The rtT display device 8 displays color dots based on the synchronization signal 5YNC output from the display controller DC and the color signals output from the DACs 70 to 72.

"Effects of the Invention" As explained above, according to the present invention, when an overflow occurs in the calculation to return luminance data and color difference data to red, green, and blue color data, all the multi-bits of the calculation result are In addition, when negative data is generated, all bits of the calculation result are set to "0", so high brightness dots may be displayed with low brightness,
On the other hand, it is possible to prevent dots with low brightness from being displayed with high brightness.

[Brief explanation of the drawing]

1 is a block diagram showing the configuration of a display device according to an embodiment of the present invention, FIG. 2 is a diagram showing the format of write data written to the VRAM 7, and FIG. 3 is a circuit showing details of the RGB data reproducing circuit 10. Figure, Figure 4 is RGB
3 is a timing diagram for explaining the operation of the data reproducing circuit 10. FIG. -ta, 3 1~4 5......or gate, ...anto game-

Claims (1)

[Scope of Claims] (a) a memory in which color information indicating the color of each dot is stored as luminance data and an average value of color difference data; (b) data read out from the memory; and (b) data read out from the memory. (c) a display device that displays color dots based on the color data R, G, B; and (c) a display device that displays color dots based on the color data R, G, and B. (d) first data conversion means that changes each bit of the operation result to "1" when the operation result in the operation means exceeds a predetermined number of bits; and (e) the operation result in the operation means. a second data conversion means that changes each bit of the calculation result to "0" when the calculation result becomes negative;