JPS63207292A - Chrominance signal converter - Google Patents

Abstract

PURPOSE:To improve the precision of conversion and the conversion speed by providing three frame memories, a lookup table means, three latch means where picture data is latched, and an adder and operating multiplication with the look-up table means and operating addition with the adder. CONSTITUTION:A look-up table in a ROM 24 uses picture data from a latch circuit 20 as an argument to generate picture data whose value is obtained by multiplying the argument by a prescribed coefficient. For example, conversion formulas of YUV RGB are R=Y+1.403V, B=Y+1.773U, and G=1.704Y+(-0.509)R+(-0.194)B. Consequently, a relatively small-capacity memory having 5k-Ward storage capacity is sufficient as the ROM 24. An adder 26 adds picture data from the ROM 24 and the picture data from a latch circuit 22. The multiplication and addition of digital picture data are quickly processed with hardware in this manner to improve the conversion precision as well as the conversion speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a color signal conversion device that converts a color signal into a color signal of another color system, and particularly relates to a color signal conversion device that improves conversion accuracy and conversion speed with an inexpensive configuration. At the same time, it is possible to improve the

(Conventional technology) Any color has three stimulus values, e.g. (R,G.

B) or (Y, M, C) or three indicators, e.g. (Y,
U, V). These color systems can be converted to each other using a certain relational expression, and color signals can also be converted to each other by calculating the relational expression in some way.

FIG. 3 shows an example of a typical conventional color signal conversion device. In this device, a CPU 100 is connected to a frame memory 102.
, 104, 106, the three video signals Y, M, C (or Y, U, V) are digital image data D Y, D M
, D C (again, D Y, D U, D V),! : and write. Next, the display control 108 synchronizes the frame memories 102, 104, and 108 to output image data at regular intervals. Output image (i-day IDY,
DM, DC (* or DY, DO, Dv) are analog video signals Y,
After being converted into M, C (or Y, U, , V), it is input to the resistance matrix circuit 116, where it is subjected to matrix calculation according to the conversion formula from the MMC (or YUV) color system to the RGB color system. be done. Thus, three analog video signals R, G, and B are obtained from the resistance matrix circuit 116, and these video signals are sent to a CRT display (not shown).

FIG. 4 shows another example of a typical conventional color signal conversion device. In this device, CPU2C)O is YMC (or Y
UV) Calculation is performed according to the conversion formula from the color system to the RGB color system, and the resulting image data DR, DG,
DB is stored in the frame memories 202, 204, 206. Next, the display control 208 synchronizes the frame memories 202, 204, and 206 to output the image data DR, DG, and DB at regular intervals. The output image data is converted into analog video signals R, G, and B by D/A converters 210, 212, and 214, and then sent to a CRT display (not shown). Buffer memory 21
6 stores image data DY, DM, and DC (or DY, DU, and Dv) before or during calculation by the CPU 200.

(Problems to be Solved by the Invention) However, the conventional same-color signal conversion devices described above each have the following drawbacks.

First, the device shown in Figure 3 uses a resistor matrix circuit to convert color signals in an analog manner, so an expensive resistor matrix circuit is required if conversion accuracy is to be improved. .

On the other hand, the device shown in FIG. 4 uses a CPU 200 to perform conversion calculations digitally, so it is easy to improve conversion accuracy, but it requires a buffer memory with a relatively large capacity in addition to the frame memory, and the conversion speed is also low. Since it is limited by the calculation speed of the CPU, it cannot be increased.

The present invention has been made in view of such problems, and an object of the present invention is to provide a color signal conversion device that can simultaneously increase conversion accuracy and conversion speed.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a color signal converting device for converting a color signal of a first color system to a color signal of a second color system. One of the three types of video signals constituting the first color signal or one of the three types of video signals constituting the second color signal is selectively stored in the address as digital image data.3 two frame memories;
look-up Φ table means for inputting image data of a predetermined one of the video signal and the second video signal and outputting image data of a value obtained by multiplying the image data by a predetermined coefficient; a first latch means for latching image data to be input to the means; for adding the image data read from the frame memory or the image data in the middle of calculation to the image data output from the look-up table means; a second latch means for latching; an adder for adding together the image data output from the pull-up table means and the image data output from the second latch means; The third latch means is configured to latch the image data of the second video signal in order to store it in the frame memory.

(Operation) The calculation for color signal conversion consists of multiplication and addition, and the look-up table means performs the multiplication and the adder circuit performs the addition in an extremely short time. The first to third latch means are used to control the transfer or distribution of image data between the frame memory, look-up table means and adder.

Thus, the conversion speed can be substantially increased to the access speed of the frame memory, and the conversion accuracy can be easily increased depending on the bit accuracy of the image data. Moreover, no special buffer memory is required other than the frame memory.

(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2. In this embodiment, the color signal of YUV color system is R
The present invention relates to a device that converts into a color signal of the GB color system.

In the device configuration shown in FIG. 1, three frame memories 10, 12, and 14 receive video signals Y and U constituting color signals of the YUV color system from the CPU I E3.

The image data DY, DU, and DV of (2) are written respectively.

The latch circuit 20 is the first transfer means of this embodiment, and transfers the image data to be input to the ROM 24 which performs a look-up table. The latch circuit 22 is
In the second step of this embodiment, one of the image data to be input to the adder 26 is latched by the Sochi means.

The look up table in the ROM 24 uses the image data from the latch circuit 20 as an argument and generates image data of a value obtained by multiplying the image data by a predetermined coefficient. Here, YUV→
The RGB conversion formula is as follows.

R= Y + Vlo, 713 B=Y+U10.564 G = (Y −0,299R−0,114B ) 1
0.587 If the above equation is transformed into an equation that only requires addition and multiplication, it becomes as follows.

R= Y + 1.403V B = Y + 1.773U G = 1.704Y + (-0,509)R+
(-0,194)B However, the look-up table in the ROM 24 is designed to perform the following data conversion.

Tomo Yu L-mu Dejbo-2j- ■・ DY 1.704
DY■・DV 1.40
3DV■, Dtl
+, F73DU■, DR(-0,
509) D RO, DB (-0, 1
94) DB The required storage capacity of the ROM 24 is as follows, assuming that the bit precision of image data is 8 bits.

2"2"2"5:5kW Here, 2' is the carry coefficient, 2' is the number of possible 8-bit values, 21 is the number of codes, and 5 is the variable (DY, Dv, D
U, DR, DB).

In this way, a relatively small capacity memory with a storage capacity of 5 kW is sufficient for the ROM 24.

The adder 26 adds the image data from the ROM 24 and the image data from the latch circuit 22 and outputs the image data of the added value to the latch circuit 28. The latch circuit 30 constitutes the third latch means of this embodiment together with the latch circuit 28, and latches the RGB image data DR, DC, and DB to be stored in the frame memories 10 to 14.

The timing control circuit 18 controls the timing of the operation of each part of the device in synchronization with the CPU 16.

Next, the color signal conversion operation of one pixel will be explained with reference to the timing diagram of FIG. 2.

'' ~ Monkey 1, (#O cycle) First, Y image data DY is read out from the frame memory 10 and latched into the latch circuit 22 (Fig. 2 A, B
, D, E, F).

2. (#1 cycle) Next, the V image data Dv is read out from the frame memory 14 and latched by the latch circuit 20 (FIG. 2A,
B + D + G + H).

3. (#2 cycle) Next, the ROM 24 is accessed by the output (DV) of the latch circuit 20, and the corresponding image data (1,403D
V (■)) (Fig. 2 H, M).

N). Then, the adder 26 outputs the ROM 24 (1, 4
03DV) and the output (DY) of the latch circuit 22 are added together, and the addition B output (DY+ 1.403D V)it
The R image data DR is latched by the latch circuit 28 (FIG. 2, 0.I, J).

2゛~Zile 1, (#3 cycle) First, U image data DU is read out from the frame memory 12 and latched into the latch circuit 20 (see A and B in Fig. 2).
, D, G, H).

2. (#4 cycle) Next, the ROM 24 is accessed by the output (DO) of the latch circuit 20, and the corresponding image data (1,773D
U (■)) (Figure 2 H, M).

N). Then, the adder 26 outputs the ROM 24 (1, 7
73DU) and the output (DY) of the latch circuit 22 are added, and the added output (DY+1.773DI+) is R image data DB, which is latched by the latch circuit 28 (
Figure 2 0.1. J). At the same time, the image data DR that had been latched in the latch circuit 28 is shifted to the latch circuit 30 (L in FIG. 2).

3. (#5 cycle) Next, the output (DR) of the latch circuit 30 is stored in a predetermined location of the frame memory 10 (FIG. 2 A, C, D). This predetermined address is the address where the previously read Y image data DY was stored.

・ゝ ~ Monkey 1, (#4
Cycle) First, the Y image data DY latched in the latch circuit 22 is transferred to the latch circuit 20 (FIG. 2 F, G,
H).

2. (#5 cycle) Next, the ROM 24 is accessed by the output (DY) of the latch circuit 20, and the corresponding image data (1,704D
Y (■)) (Fig. 2 H, M).

N). The output (1,704 DY) of this ROM 24 is latched by the latch circuit 22 (FIG. 2 E, F).

On the other hand, the output (DR) of the latch circuit 30 is
(Fig. 2 G, H).

L), the output (DB) of the latch circuit 28 is the latch circuit 30
(FIG. 2 J, L).

3. (#6 cycle) Next, the ROM 24 is accessed by the output (DR) of the latch circuit 20, and the corresponding image data (-0,509
DR(■)) (Fig. 2 H, M).

N). Then, the adder 26 outputs the ROM 24 (-0,
509D R) and the output of the latch circuit 22 (1,704D
Y) is added, and the addition output (1,704DY −
0,509 DI? ) is latched by the latch circuit 22 (
Figure 2 0. E, F).

On the other hand, the output (DB) of the latch circuit 30 is stored in a predetermined location of the frame memory 12 and latched by the latch circuit 20 (FIGS. 2A and 2C).

D, G, H). Note that the predetermined address is the address where the U image data DU was stored.

4. (#7 cycle) Next, the ROM 24 is accessed by the output (DB) of the latch circuit 20, and the corresponding image data (-0, 194
DB(■)) (H, M in Figure 2).

N). Then, the adder 26 outputs the ROM 24 (-0,
194D B) and the output of the latch circuit 22 (1,704D
Y -0,509DR) is added, and the addition output (1°704DY -0,509DR-0,194DB
) is G image data DG, which is latched by the latch circuit 28 (0.1.J in FIG. 2).

5. (#8 cycle) Next, the output (DG) of the latch circuit 28 is sent to the latch circuit 30.
(L in Figure 2).

6. (#9 cycle) Finally, the output (DC) of the latch circuit 30 is stored in the predetermined address of the frame memory 14, that is, the address where the V image data Dv was stored (FIG. 2 A, C, D) .

This completes the YUV-RGB conversion for one pixel, and the same operation as above is repeated for the next pixel. Note that the RGB image data D R and D B stored in the frame memories 10, 12, and 14.

DG sequentially uses a display controller (not shown) for display.
The data may be read out under the control of the controller and sent to a CRT display (not shown) after D/A conversion.

Clock cycles #0 to #9 of the conversion operation described above are CP
It is much faster than the U system clock,
The conversion speed can be increased to the frame memory access speed. Conversion precision can be easily improved by increasing the bit precision of image data. As for the device price, it is relatively inexpensive because it does not use a large-capacity buffer memory other than the frame memory.

Note that although the apparatus of the above-described embodiment is related to YUV-RGB conversion, the present invention is of course applicable to other color signal conversions such as YMC→RGB conversion and RGB-YUB conversion.

(Effects of the Invention) As described above, according to the present invention, conversion accuracy and conversion speed can be simultaneously improved by performing multiplication and addition on digital image data at high speed using hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a YUV-)RGB conversion device according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the conversion device shown in FIG. 1, and FIG. , a block diagram showing the configuration of one example of a typical conventional color signal conversion device, and FIG. 4 is a block diagram showing the configuration of another example of the conventional typical color signal conversion device. 10.12.14...Frame memory, 16...
・CPU. 18...timing control circuit, 20... latch circuit (first latch means), 22...
...Latch circuit (second latch means), 24...
ROM (look up table means), 26...
...Adder, 28.30...Latch circuit (third latch means).

Claims (1)

[Scope of Claims] In a color signal conversion device that converts a color signal of a first color system to a color signal of a second color system, three types of images constituting the first color signal are stored at each address. three frame memories that selectively store one of the signals or one of the three types of video signals constituting the second color signal as digital image data; 2. A look inputting the image data of a predetermined one of the two video signals and outputting image data of a value obtained by multiplying the image data by a predetermined coefficient.
look-up table means; first latch means for latching image data to be input into the look-up table means; a second latch means for latching to add to the image data output from the look-up table means; the image data output from the look-up table means and the image data output from the second latch means; and a third latch unit that latches the image data of the second video signal output from the adder in order to store it in the frame memory. Color signal conversion device.