JPH01177587A - Color display device - Google Patents

Abstract

PURPOSE:To reduce the memory capacity of the title device and to suppress influence of conversion error by operating each average value of color difference data to store it in a memory and using red-luminance color difference data and green-luminance color difference data. CONSTITUTION:A converting means 5 which converts color information indicating respective colors of dots to luminance data Y, 'red-luminance' color difference data U, and 'green-luminance' color difference data W, a calculating means which calculates respective average values of color difference data U and W for every plural dots, and a writing means 20 which writes average values of color difference data U and W and luminance data Y in a memory (video RAM) 21 are provided. That is, since respective average values of color difference data U and W are calculated and are stored in the memory 21, one data is stored per four dots if the average value is calculated for every four dots, and the memory capacity is reduced. Since 'red-luminance' color difference data U and 'green-luminance' color difference data W are used, the conversion error is concentrated on blue and the influence of the conversion error is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a color display device in which the storage capacity of a VRAM (video RAM) is reduced.

"Prior art" When displaying color dots using a CRT display device,
A known method is to store red color data R1, green color data G1, and blue color data B in correspondence with each dot in a VRAM, read out the color data R, G, and B, and convert them into analog color signals for display. . In addition, as another method, color data R, G, B is once converted into luminance data and color difference data and stored in VRAM, and this luminance data and color difference data are read out from VRAM. A method is also known in which the signal is converted into an analog color signal and then displayed. In this method, mutual conversion of color data R, G, B, luminance data, and color difference data is usually performed by an analog circuit.

"Problems to be Solved by the Invention" By the way, when displaying high-gradation color dots in a color display device, the number of bits of display data such as color data R, G, B or luminance data and color difference data must be increased. Must be. However, as the number of bits of display data increases, there is a problem that the capacity of the VRAM increases.

In addition, in the case of a color display device that converts color data R', G, and B into luminance data and color difference data and stores them in VRAM, there is a problem that a conversion error occurs when mutually converting color data R1G, B - luminance data 1 color difference data. There is.

This invention was made in view of the above-mentioned circumstances, and its purpose is to develop a digital technology that can compress the amount of display data and minimize the effects of the above-mentioned conversion errors. An object of the present invention is to provide a color display device that stores luminance data and color difference data.

"Means for Solving the Problem" The first invention provides a color display device that displays color dots, in which color information indicating the color of each dot is divided into luminance data Y and "red-luminance" color difference data U. “Green-
a conversion means for converting the luminance into color difference data W; a calculation means for calculating the average value of each of the color difference data U and W for each plurality of dots; and a calculation means for calculating the average value of the color difference data U and W and the brightness data Y It is equipped with a writing means for writing into the memory.

Further, in a second invention, in a color display device that displays color dots, the color information indicating the color of each dot includes luminance data Y, the average value of "red-luminance" color difference data U, and "green-luminance". ``The average value of the color difference data W is stored in a memory, the data is read from the memory, and the read data is converted into red, green, and blue color data R, G, H.
and a display means for displaying color dots based on the color data R, G, H.

"Function" According to this invention, each average value of the color difference data U and W is taken and stored in the memory, so for example, if the average value is taken every 4 dots, it is only necessary to store the I data every 4 dots. , memory capacity can be reduced. Further, according to the present invention, since "red-luminance" color difference data U and "green-luminance" color difference data W are used, conversion errors are concentrated in blue.

The human eye is relatively insensitive to changes in the color blue, and as a result,
The influence of conversion errors can be minimized.

"Embodiment" 14= Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the same embodiment. The color display device shown in this figure converts color data R, G, and B into luminance data and color difference data, and converts color data R, G, and B into luminance data and color difference data.
Store it in RAM and read this stored data,
The color data R1G, B are reproduced, and the reproduced color data R, G.

Display is performed based on B.

To explain in detail below, in the figure, 1 indicates the CPU 12 is the CPU
This memory consists of a ROM in which programs used in the computer are stored and a RAM for data storage. DC is a display controller, which outputs control signals to each part of the device under the control of the CPUI, and also outputs control signals to the VRAM21.
Outputs the write/read address AD to. 3 is a terminal to which the composite video signal Cv is input; 4 is a terminal for converting the composite video signal Cv into color data R, G, B;
This is a well-known decoder that sequentially outputs data at the timing of the dot clock DCLK. In this embodiment, color data R, G, and B are each 5 bits. Further, the dot clock DCLK is a clock pulse having the same timing (period) as the display of each dot on the CRT display device 7.

5 is a data conversion circuit that converts color data R, G, B into luminance data 79 and color difference data U, W, and performs data conversion based on the following equation.

Y = (1/4)R+ (1/8)G + (1/2)
B-(]/8X2R+G+4B)...
...(1) U=RY...(2) W=G-Y...(3) FIG. 2 is a diagram showing a specific configuration of this data conversion circuit 5, In this figure, 6 and 7 are 8-bit full addition circuits, 8 and 9 are 6-bit full subtraction circuits, and IO to I
8 is a parallel in/parallel out register.

Further, terminal TI is a terminal that supplies the dot clock DCLK from the display controller DC, terminals T2 to T4 are terminals that supply color data R, G, and B from the decoder 4, respectively, and T5 is a terminal that supplies the dot clock DCLK from the display controller DC.
T7 is a terminal that outputs color difference data U and W, respectively, and T6 is a terminal that outputs luminance data Y. Here, the color data R, G, B and luminance data Y are 5-bit positive integers, and the color difference data U, W are 6-bit positive or negative integers, and negative numbers are expressed in "two's complement". There is.

Next, the operation of this data conversion circuit 5 will be explained with reference to the timing diagram of FIG. Now, the time to shown in Figure 3
After that, color data (r+, gt, bl), (r2, gt
, b2)... are sequentially connected to terminals T 2 , T 4 , T
3 in parallel (see figure (b)). First, at time to, the adder circuit 6 outputs data (4bl+gt) as shown in FIG. Here, data 4b is obtained by manually shifting data b by 2 bits toward the higher order and inputting it to adder circuit 6. Time tl
, registers 10 to 12 each contain data r, ,
(4b+ 10g+), gt is output ((d)bajo), (to)). Furthermore, the adder circuit 7 that adds the output data of the registers 10 and 11 adds the data (4bl + gt
+2 r+). Here, the data r2+ is obtained by shifting the data r1 by one bit toward the higher order and inputting the shifted data to the adder circuit 7.

At time t2, registers 13 to 15 each contain data r
+, (1/8) (4b++ g++ 2 r+), gt
Output.

By inputting only the lower three bits of the output data of the adder circuit 7 to the register 14, (1/8×4bl+g++2g+) is obtained. At this stage, the luminance data described above was obtained.

Let this luminance data be y.

(178) (4bl 10g+ +2 r+)-L+”'
”' (4) Then, the subtraction circuits 8 and 9 each input data (
r+-y+), (gt-y+) (same figure (le)
, (o)). Here, as is clear from the above equations (2) and (3), each output data of the subtraction circuits 8 and 9 is color difference data, and this color difference data is
Let it be I.

r+ Y+-Ll+ (5) L Yl=W+ (6) Next, at time t3, the registers 16 to 18 contain color difference data ul+luminance data Y+ and color difference data W, respectively.

is output and supplied from terminals T5 to T7 to the write data forming circuit 20 shown in FIG.
. Thereafter, in the same way, every time the dot clock DCLK rises, the color difference data and luminance data (uz, Y2+W2), (II3.y313), etc. are sent from the terminals T5 to T7.
...is output sequentially.

The write data forming circuit 20 forms data to be written into the VRAM 21. The color difference data U, W and luminance data Y output by the data conversion circuit 5 are not stored in the VRAM as they are, but are compressed by the write data forming circuit 20 and then stored.

Here, a data compression method will be explained. The human eye has a property that it is unable to distinguish colors in small areas. Therefore, even if, for example, the same averaged color difference data is assigned to four consecutive dots, no noticeable difference will appear visually compared to the case where independent color difference data is assigned to each dot. The write data forming circuit 20 receives color difference data U, V from the data conversion circuit 5.
Each time 4 data are received, the average of the 4 data is taken, and this average value and the 4 luminance data form data to be written to the VRAM. FIG. 4 is a diagram showing the structure of write data. In this figure, y, to y4 are luminance data (5 bits each), u'h, u'ρ are luminance data Y I
-)' The four color difference data u1 to u input together with 4
The upper 2 bits and lower 4 bits of the average value U° of 4, and the upper 2 bits of the average value of the 4 color difference data w1 to w4 input together with the luminance data YI-Y4, respectively, w'h and w'. and the lower 4 bits.

The write data thus formed is sequentially output to the VRAM 21 from address BO indicating the storage location of one byte.

In addition, luminance data Y and color difference data U and W.

If you write it to VRAM as is, every 4 dots (5+6
+6) X4 = 68 bits are required, but according to the data compression described above, 8x4 = 32
Bits will suffice.

FIG. 5 is a circuit diagram showing a specific configuration of the write data forming circuit 20 described above. In this figure, the symbol TIO
~TI2 are terminals to which color difference data U, luminance data Y1 and color difference data W are supplied from the data conversion circuit 5, T13~
TI7 is a terminal to which clock pulses UWCLK, dot clock DCLK, and clock pulses UWCLKa1 select signals TCI and TCO are supplied, respectively, from the display controller DC, and TI8 is a terminal to which 8-bit write data supplied to LiVRAM2] is output. The above dot clocks DCLK, clock pulse 7, UWCLK, UW
CLKa, select signals TCO, TCI are shown in Fig. 6 (
Shown in a) to (e). Here, the clock pulse UWCL
K is a clock pulse obtained by dividing the dot clock DCLK into 1/4, and the clock pulse UWCLKa is a clock pulse obtained by slightly delaying the clock pulse UWCLK. In addition, select signals TCO, TCIli, and O-t
It becomes "0, 0" at the rising edge of dot clock UwcLK, and thereafter "1.0", "0.1", "1.1", "0" at the rising edge of dot clock DCL'.
．． This is a signal that changes sequentially from 0"...

23 and 24 are averaging circuits that accumulate four pieces of color difference data U and W that are sequentially supplied, and calculate 1/1/2 of the accumulated results.
Outputs 4. FIG. 7 is a circuit diagram showing the configuration of the averaging circuit 23. In this figure, 25 is an 8-bit parallel in/parallel out register, and 26 is an 8-bit adder circuit.

First, the register 25 is reset to "0" by the clock pulse UWCLKa. Next, this register 25
The data within (in this case "0") and the color difference data U are added by the adder circuit 26, and the addition result is written into the register 25 at the rise of the dot clock DCLK. Further, the addition result of the adder circuit 26 is shifted by 2 bits in the lower direction (that is, converted to 1/4) and output. Note that the above shift processing means that the upper six bits of the adder circuit 26 are output. Next, this written data and the next color difference data U are added in an adding circuit 26. This operation is repeated four times to obtain the cumulative results of four color difference data U. It is converted to I/4 by cutting off the lower two bits. Since the signal TCO is supplied to the carry input C0 of the least significant bit of the adder circuit 26, the result is rounded off at the time of 1/4 averaging. Note that the averaging circuit 24 also has the same configuration as the above-mentioned averaging circuit 23.

Next, 30 to 35 in Fig. 5 are parallel in/parallel out registers, data is written to registers 30 to 33 at the rising edge of the dot clock DCLK, and data is written to registers 34 and 35 at the rising edge of the clock pulse UWCLK. It will be done. 36.37 is a selector, which selects input terminal <0 based on the select signal TCO1TC1.
Select one of the data from <3> to output from the output terminal.

Next, the operation of the write data forming circuit 20 described above will be explained in the sixth section.
This will be explained with reference to the timing diagram shown in the figure.

The averaging of the color difference data W is performed in the same manner as the color difference data U, so the description thereof will be omitted.

First, at time tll, the dot clock DCLK rises, and at this rise, the terminals TIO to TI2
to each color difference data ul + luminance data y1, color difference data w
Assume that I is supplied (see FIG. 6).

At the same time, the clock pulse UWCLK rises, and a little later, the clock pulse UWCLKa rises. When the clock pulse UWCLKa rises, the seventh
Register 25 in the figure is cleared and its output data is “0”.
”. As a result, the adder circuit 26 calculates ru++OJ.

Next, at time t12, the color difference data u2. Luminance data y2+color difference data w2 appear (FIG. 6(f)). The output u1 of the register 25 and the color difference data u2 are added. Also, at the rising edge of the dot clock DCLK at time t12, the luminance data y1 is written into the register 30. Hereinafter, time t13. At t14, the same processing is performed, and the luminance data yI is sequentially shifted from the register 31 to the register 32.

Next, at time t15, color difference data '5+luminance data y51 and color difference data w5 are supplied to the terminals TIO to TI2, respectively. At the same time, the clock pulse UWCLK rises, and a little later, the clock pulse UWCLKa rises.
stands up. When the dot clock DCLK rises, the output data y of the register 32 is written to the register 33. Furthermore, at the rising edge of the clock pulse UWCLK, the output data r(u, +ut+
L13+ [4)/4 J, r(w+ +L + W
3 + W4) / 4 J (See Figure 6 (G) and (H))
are written to registers 34 and 35, respectively. Thereafter, the same operation is repeated.

In this manner, the write data forming circuit 20 of FIG. 5 writes the average value into the register 34.35 every time four pieces of color difference data U and W are supplied (that is, every four dot clocks). On the other hand, brightness data Y
registers 30 to 33 according to the dot clock DCLK.
will be shifted sequentially. Then, the output data of the register 33 is outputted from the terminal T18 to the VRAM21, and
Each bit of the output data of registers 34 and 35 is selected by selectors 36 and 37, and this selected data is output from terminal I8 to VRAM 21 (see Figure 4).
.

First, at time t15 in FIG. 6, data y is output from the register 33, and the 0th
~4th bit. Also at this time, Figure 6 (d)
, (e), select signals TCO, TC
Each I becomes "0.0". As a result, the selector 36 outputs the output data r(u+ +ut+
U3+u4)/4=u' The data of the 4th bit of J is output and supplied to the 5th bit of terminal T18,
Further, from the selector 37, the data of the 0th bit of the output data + of the register 34 and the output data of the register 35 [(w+ + Wffi + W3+ W4)/4
= w', the data of the 0th bit of J are output, and the data of the 6th bit of the terminal T18 is output. Supplied to the 7th bit. -At this time,
The display controller DC (FIG. 1) outputs the address AD of the VRAM 21. As a result, the above-mentioned terminal T1
8 data is written to the VRAM21. Next, at time t16 in FIG. 6, luminance data y2 is supplied to the 0th to 4th bits of terminal TI8. In addition, select signal TC
O and TCI each become "1.0", and therefore, the selector 36 outputs the data of the fifth bit of the output data of the register 34 +1, which is supplied to the fifth bit of the terminal TI8, and the selector 37 outputs the data of the fifth bit of the output data of the register 34 +1. is register 34
The data of the first bit of the output data +1 of the register 35 and the data of the first bit of the output data + of the register 35 are respectively outputted and supplied to the 6th and 7th bits of the terminal T18.

The data on this terminal T18 is then transferred to the display controller D.
VRAM2 based on the address AD output from C.
Written to +. Hereafter, the same process is repeated, and V
Data is written into the RAM 21 as shown in FIG.

The details of the write data forming circuit 20 have been described above.

Next, the RGB data reproducing circuit 40 of FIG.
This circuit reproduces the luminance data Y and color difference data U', W' read out from 21 at the timing of the dot clock DCLK into color data R, G, B, and calculates the following equation.

R=Y+U' ・・・・・・(7) G=Y+W'
...(8) B = (5/4) Y - (1/2) U' - (
1/4)W'-(1/4)(5Y-(2U'+W'
Month ......(9) These equations are calculated by replacing U and W in equations (1) to (3) above with U' and W', respectively, and R
, G, and B. Further, among these equations (7) to (9), only equation (9) includes division, so the conversion error appears only in blue (B). but,
Since the human eye is most insensitive to slight changes in hue mixed with blue, this conversion formula can minimize the effects of conversion errors.

FIG. 8 is a circuit diagram showing details of this RGB data reproducing circuit 4o. In this figure, T21 and T23 are the dot clocks DCLK output by the display controller DC, respectively.
and a terminal for clock pulse 4XCLK. Here, the clock pulse 4XCLK is a clock pulse obtained by dividing the dot clock DCLK into 1/4 as shown in FIG. 9(b). T22 is a terminal that supplies data read from the VRAM 21, and T24 to T26 are terminals that output color data B, R, and G, respectively. 41 to 45 are parallel in/parallel out registers that read input data based on the dot clock DCLK, and 46 to 48 are parallel in/parallel out registers that read input data based on the above-mentioned clock pulse 4XCLK. Further, 49 to 53 are adder circuits, 54 is an inversion circuit that inverts and outputs each bit of input data, and 55 to
59 is an exclusive or gate.

Next, the operation of this RGB data reproducing circuit 40 will be explained with reference to FIG. Now, at the rising time L21-t24 of the dot clock DCLK shown in FIG. 9(A), bytes BO to B3 (not shown in FIG. 4) are sequentially stored in the VRAM 21.
Suppose that it is read from and supplied to terminal T22 (Fig. 9 (
(See C). In this case, each data is dot clock DC
The registers 41 to 43 are sequentially shifted by LK ((d), (e), (v) in FIG. 9). And time t2
4, when the register 43 outputs the luminance data y, this luminance data Y+ is supplied to the first input terminal of the addition circuit 49, and is also multiplied by 4 and supplied to the second input terminal of the addition circuit 49, As a result, data 5 is output from the adder circuit 49.
y+ is output and supplied to the input terminal of the register 44 (
Figure 9(g)). Further, at the same time t24, when each data of bytes BO to B3 in FIG. 4 is output from the registers 43, 42.41 and the terminal T22, the register 46
The color difference data U'' consisting of the data u'h and u'12 in FIG. The color difference data W' consisting of the data W''h and w' (in FIG. 4) is supplied to the second input terminal of.

In this case, the data U' is shifted by 1 bit (multiplied by 2) and supplied to the adder circuit 50. As a result, data (2u'10w') is output from the adder circuit 50 (Fig. 9 (
h)) is supplied to register 48.

Next, at time t25, the dot clock DCLK rises and the clock pulse 4XCLK rises. When the dot clock DCLK rises, the output data 5y1 of the adder circuit 49 is read into the register 44, and the luminance data y output from the register 43 is read.
, are read into the register 45 (FIG. 9 (wa) and (nu)). Further, when the clock pulse 4
Figure (ru), (o), (wa)). Then, when the output data of the register 44 is supplied to the first input terminal of the subtraction circuit 51 and the output data of the register 48 is inverted by the inversion circuit 54 and supplied to the second input terminal of the subtraction circuit 51, the subtraction circuit 51
1 to data (1/4) (5y, -(2u' + w')) -
-(10) is output (Figure 9 (force)). This (10
) and the above-mentioned equation (9), it is clear that the output of the subtraction circuit 51 is color data B. Further, the output data of the register 45 is input to the first input terminal of the adder circuit 52, and the output data of the register 46 is input to the second input terminal of the adder circuit 52.
When each is supplied to the input end, the adder circuit 52 outputs the following data (y, +u'...(11)) (FIG. 9 (Y)). This data is color data R as is clear from equation (7) above. Similarly, the output data of the register 45 is sent to the adder circuit 53.
When the output data of the register 47 is supplied to the first input terminal of the adder circuit 53 and the output data of the register 47 is supplied to the second input terminal of the adder circuit 53, the adder circuit 53 outputs the data YI+W' (12) ( Figure 9 (evening)). This data is color data G, as is clear from equation (8) above.

In this way, at time t25, the luminance data y and color difference data u', w' are converted into color data B, R, G, and outputted from the addition/subtraction circuits 51-53. Similarly, at times t26, t27, and t28, luminance data y21 Y31)'4 and color difference data 11'
, W' are converted into color data B, R, and G, which are output from addition/subtraction circuits 51-53. On the other hand, the above time t25~
At t28, the following four data are sequentially supplied to the terminal T22, and these data are sequentially read into the registers 41-43. Then, at times t29 to t32, color data B, R, and G based on these data are sequentially output from the addition/subtraction circuits 51 to 53, and this process is repeated thereafter.

Next, the output of the subtraction circuit 51 is supplied to the terminal T24 via exclusive OR gates 55 to 59, and
The outputs of adder circuits 52 and 53 are respectively connected to terminals T25. It is supplied to T26. Here, exclusive or gate 55
59 are provided in case the subtraction result of the subtraction circuit 51 overflows or underflows. That is, first, if the subtraction result of the subtraction circuit 51 does not overflow or underflow, the subtraction circuit 51
The signal at the output terminal S8 is "0", so the exclusive OR gates 55 to 59 are in the through state. On the other hand, if the subtraction result overflows and the signal at the output terminal S8 becomes "l" and the signals at the other output terminals 83 to S7 become "0", the exclusive or gate -55 to 59
operates as an inverter and sends data “11” to terminal T24.
111'' is supplied.Furthermore, when the subtraction result underflows and the signal at the output terminal S8 and the signals at the other output terminals 83 to S7 become "1", the exclusive OR gates 55 to 59 operates as an inverter, and the terminal T
Data “ooooo” is supplied to 24.

It takes advantage of the fact that the error is only ±1.

Next, the above-mentioned terminals T 25 , T 26 , T 24
The color data R, G, and B respectively output from the DAC (digital/analog converter) 56゜57 in Fig. 1
．． 58. The DACs 56 to 58 convert the color data R, G, and B into analog color signals and output them to the CRT display device 7. The CRT display device 7 receives synchronization signals 5YNC and DAC output from the display controller DC.
Color dot display is performed based on color signals output from 56 to 58.

The details of one embodiment of the present invention have been described above. In the above embodiment, the format of the data written to the VRAM 21 is shown in FIG. 4, but it may be, for example, in the format shown in FIG. 10.

Moreover, in the circuit of FIG. 2, (4B + G 12
Although the decimal point in the calculation R)/8 is rounded down, it may be rounded off.

When rounding off, it is sufficient to perform the calculation (4B0G+2R+4) and divide the result of this calculation by 8.

Similarly, in the circuit of FIG. 8, (5Y - (2U'
Although the decimal point in the calculation +W'))/4 is rounded down, it may be rounded off. In this case, the calculation (5y-(2u'+w')+2)/4 may be performed.

However, the display device according to the above embodiment has a problem when performing overwriting. That is, in computer graphics, etc., a second image may be displayed in a superimposed manner on top of a first image. In this case, color data R, G, B is stored in VRAM corresponding to each dot.
If it is stored, you can simply rewrite the color data in the storage area corresponding to the second image in VRAM.
If one color difference data is stored for every four dots as in the above embodiment, it becomes impossible to rewrite each dot. In this case, of course, data can be rewritten in units of 4 dots, but in such rewriting, the second
The resolution of the image becomes low. Next, another embodiment that solves this overwriting problem will be described.

FIG. 11 is a diagram showing the format of write data in the same embodiment. This format differs from the one shown in FIG. 4 in that the 0th bit of each byte BO to B3 is an attribute bit ATR and that the luminance data Y is 4 bits. Similarly to the above embodiment, when displaying an image using luminance data Y and color difference data U and W, attribute bit A
Set TR to "0". When changing the color of some dots (in the case of overwriting), a color code CC is written in place of the luminance data Y of the dot, and the attribute bit ATR is set to "1".

FIG. 12 is a diagram showing the configuration of the RGB data reproducing circuit 40 in this embodiment, and in this figure, the RGB data forming circuit 60 is the same as the circuit configured by the components 49 to 59 in FIG. It is a circuit. In other words, this circuit has a configuration in which a register 62, a color look-up table 63, and a selector 64 are added to the circuit shown in FIG.

Here, the register 62 is a register for reading data at the rising edge of the dot clock DCLK, and the color lookup table 63 is a table for converting the color code CC output from the register 62 into color data R, G, H. Further, when "0" is supplied to the select terminal SE, the selector 64 transfers the color data R, G, B output from the RGB data forming circuit 60 to the terminal T2.
5. Output to T26, T24, and select terminal SE
When "1" is supplied to the terminal T, the color data R, G, B output from the color lookup table 63 is sent to the terminal T.
25. T26. Output to T'24. This selector 64
The above attribute bit A is sent to the select terminal SE of
TR is now supplied.

Therefore, when the attribute bit ATR is "0", "0" is supplied to the select terminal SE of the selector 64, so that the color data R, G, B output from the RGB data forming circuit 60 is In other words, in this case, the operation is the same as that of the circuit shown in Fig. 8.On the other hand, when the attribute bit ATR is "1", the brightness data The color code CC obtained is supplied to the color lookup table 63 via the register 62, where it is converted into color data R, G, H, and this color data R, G, B is sent via the selector 64 to the terminal T25. ．．
T26. It is supplied to T24. As a result, dots are displayed in the color corresponding to the color code CC.

"Effects of the Invention" As explained above, according to the present invention, color difference data U
, W are taken and stored in the memory, so that the memory capacity can be reduced. Further, according to the present invention, since the "red-luminance" color difference data U and the "green-luminance" color difference data W are used, conversion errors are concentrated in blue, and therefore the influence of conversion errors is minimized. It can be held down to 128=.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a circuit diagram showing details of the data conversion circuit 5 in the same embodiment, FIG. 3 is a timing diagram for explaining the operation of the data conversion circuit 5, and FIG. 4 shows the format of data written to the VRAM 21. 5 is a circuit diagram showing details of the write data forming circuit 20 in the same embodiment, FIG. 6 is a timing diagram for explaining the operation of the write data forming circuit 20, and FIG. 7 is a circuit diagram showing the write data forming circuit 20 in the same embodiment. A circuit diagram showing the configuration of the averaging circuit 23 in the circuit 20, FIG. 8 is a circuit diagram showing details of the RGB data reproducing circuit 40 in the same embodiment, and FIG. 9 is a circuit diagram showing the details of the RGB data reproducing circuit 40 in the same embodiment.
The timing diagram for explaining the operation of the VR
A diagram showing another format of AM21 write data,
FIG. 11 is a diagram showing the format of write data in another embodiment of the invention, and FIG. 12 is a block diagram showing the configuration of the RGB data reproducing circuit 40 in the same embodiment. 5... Data conversion circuit, 7... CRT display device, 20... Write data forming circuit, 21...
VRAM, 23.24...Averaging circuit, 40.
...RGB data reproduction circuit.

Claims (2)

[Claims] (1) (a) In a color display device that displays color dots, (b) Color information indicating the color of each dot is divided into luminance data Y, "red-luminance" color difference data U, and "green-luminance" color difference. (c) calculation means for calculating the average value of each of the color difference data U and W for each plurality of dots; (d) the average value of the color difference data U and W and the brightness A color display device comprising: writing means for writing data Y into a memory. (2) (a) In a color display device that displays color dots, (b) color information indicating the color of each dot is the average value of luminance data Y, "red-luminance" color difference data U, and "green −
(c) a conversion means for reading data from the memory and converting the read data into red, green, and blue color data R, G, and B; (d) the aforementioned A color display device comprising: display means for displaying color dots based on color data R, G, and B;