JPH02307172A - Shading circuit - Google Patents

Abstract

PURPOSE:To carry out the 3-dimensional picture display at a high speed and to obtain a man-machine system having the excellent response properties by carrying out simultaneously the display of a vector, a shading operation, and a hidden surface erasing operation respectively in terms of a vector arithmetic. CONSTITUTION:A shading circuit consists of a division value register 5, an adder 6, a register 7, a division value register 8, an adder 9, a register 10, a division value register 11, an adder 12, a register 13, a counter 14, a multiplexer 15, and a RAM 16. Then the luminance or color data is set as each attribute of a 3-dimensional vector. The luminance is distributed in the direction of the 3-dimensional vector in order to secure adaptation regardless of the line pictures or screens. In addition, the luminance data can be obtained in parallel with erasion of a hidden surface carried out by a depth buffer. As a result, a 3-dimensional picture is displayed at a high speed and at the same time the response speed is improved.

Description

[Detailed description of the invention]

[Industrial Application Field] The technique of the present invention is a circuit for obtaining a shading effect, which is applied to a three-dimensional computer graphics display device.

[Comparison with conventional technology]

Traditionally, shading has been mostly achieved through software methods, with little or no hardware involved. The present invention is a luminance interpolation between a starting point and an ending point that also serves as filling in the scanning direction.In the present invention, luminance or color data is set as an attribute of each three-dimensional vector, and accompanying the direction of the three-dimensional vector, It distributes brightness. Therefore, it can be applied to any single line drawing screen, and brightness data can be obtained in parallel with hidden surface removal using the depth buffer. [Industrial Application Effects] The method according to the present invention relates to vector operations. Since vector display, shading, and hidden surface removal can be performed simultaneously, three-dimensional image display can be performed at high speed, and it is effective for constructing a man-machine system with excellent responsiveness. [Embodiment] FIG. 1 shows a principle diagram of a conventional vector generator, showing only one of the x, y, or Z axes. In FIG. 1, circuit 1 divides the lengths of X, Y, and two other coordinate values by the axis that has the longest length between two points. A register loaded with a value below the decimal point, 2 is an adder and 3 is a register. The vector generator adds and accumulates decimal point values in circuit 3 for a number of clocks equal to the length of the longest axis. At the time when the adder Z outputs the carry signal, the counter 4 that has been initially loaded with the starting point coordinate value is incremented. As a result, the output of the counter 4 successively indicates the interpolated meditation value between the two points. In the present invention, when performing shading. The data structure of geometric information and its attributes is shown in Figure 2.
It is assumed that it consists of dimensional coordinate values and their brightness attributes. That is, the commands given to this circuit are the three-dimensional X, Y and zmw values and the brightness attribute at that point. This brightness attribute is. A single color or red, green, blue values, e.g. 1 for every 8 bits.
In the H5V and HLS color models, which may be color data assigned within a word or each element of the HLS color model, V (value) or L (light) is treated as luminance target data. FIG. 3 shows a shading circuit according to the present invention.
In FIG. 3, 5, 7.8, 10.11 and 13 are registers, 6.9 and 12 are adders, 14 is a counter, 15 is a multiplexer, and 16 is a storage element RAM. In explaining the operation of FIG. 3, we will explain the relationship between the data shown in FIG. 21i1 and FIG.
Linear interpolation is performed between them using a series of continuous coordinate points and brightness, and generally, intensity, interpolation,
Shading (Intensity 1ntsrp
This is called "on shading". Starting point of a-dimensional data (X @ Y @ Z @ L *
) and the end point (x tY a Z IL z ) are given in the data format shown in Figure 2. The calculation shown in equation 1 is executed. ΔX electric power ASX = l8
1. In other words, 9th jlF11-14 is 3
Although there are two sets, only one axis is shown in Fig. 3. However, the axis input to the multiplexer 15 is the Z-axis counter. Based on the principle of a vector generator, the coordinate data of each axis for interpolation between two points is the starting point coordinate value (X m Y @ Z @ ) initialized in each counter 14.
From then on, step towards the end point coordinates of The Z coordinate of the address of the image memory is a value that is stored in 2 buffers.The 2 buffers are provided to erase hidden surfaces, and for the data written to the same -xY address on 1 image memory, Write control is performed by comparing the values of x y is luminance data ΔL as in equation (2), (3
) Divide as shown in the formula. Δ5L=lΔL+/ΔMxy (3) Since ΔL is not geometric data, there are values larger than ΔMxy, and ΔSL may include values above the decimal point. (3
), the data above the decimal point in Figure 3 is loaded into register 8, the data below the decimal point is loaded into register 5,
Further, the starting point *L@ of luminance is initially set in the register 10. That is, circuits 5 to 10 are luminance DDA. This DDA is assumed to be stepped by a carry signal of the decimal point arithmetic section of the major axis DDA among the X and Y axis DDAs. Therefore, if any of these two axes has the largest distance among the three axes, the luminance DDA is stepped with a clock equal to the distance between the two points. Equations (2) and (3) are processed simultaneously or sequentially, and their respective circuits are incremented simultaneously after the division and initialization are completed. Second result, brightness register 1
The output of 0 is continuously interpolated from the luminance at the starting point of the x, y coordinates to the luminance at the ending point. This output data is given to the multiplexer 15 and becomes an input to the RAM 16 together with the two-axis interpolated coordinate value output from the Z-axis counter 14. The reason for using a multiplexer is that the Z value is unnecessary when only the shading effect is obtained, and both data are used when obtaining the depth cue effect, making it possible to select one. The brightness data and the zI* coordinate value become the address of the RAM 16. The RAM may be a ROM, in which luminance data is stored along a correction curve (e.g., approximating an α curve) with a visually continuous luminance gradient for the characteristics of the fluorescent material of the television monitor.・The table is memorized. In this RAM table, in the case of a single color depth cue, the Z value is used as an address, and in the table, the above curve function value with 1/Z as a variable is stored, and in the case of color - three primary colors, red,
RAMs are prepared for each of green and blue, and the correction curve values are stored using respective luminance data as addresses. In addition, when serving both as depth cue and shading, the multiplexer 15 passes both the ZJllll target value and luminance data, prepares a RAM whose addresses are the luminance data and two coordinate values, and reads (luminance data) x1/
Data is output from the RAM that stores the brightness correction curve with Z as a variable. The data obtained in this way is D
The data is sequentially written into the image memory as the DA advances. In the color model in the design field, RBG is generally used.
In the present invention, in which the H8V or HLS color model is used, the luminance DDA is V (Val
u a), HLS Modelte targets L (Light). On the other hand, the luminance interpolation data between two points determined by the DDA must be converted to RGB when writing to the image memory or in a look-up table located at the output of the image memory. In the present invention, in the H8V or HLS model, each H (Hue) and 5 (Saturation
n) for the 41st! The address of the storage element RAM 17 shown in 1 is taken as one set of addresses of the other RAM 18, and the luminance interpolation data is set as one set of addresses of the other RAM 18, with the output of the RAM 17 as one set of addresses.
Each RAM stores data based on an RGB conversion formula. The reason for having two stages of RAM is due to capacity issues and access speed issues.Since the brightness interpolation data for other required sH and S changes rapidly in synchronization with DDA, it is necessary to use two stages of RAM. Improve response speed by typing. The R, G, and B signals thus obtained are transferred to the image memory and sequentially written to the addresses indicated by the X and Y axes of the DDA based on the determination of the two buffers. As described above, the present invention calculates interpolated coordinate values between two points of each axis by dividing the other two axes by the axis with the longest distance between two points in a vector generator having a three-dimensional DDA. In addition to having a depth buffer function, it also has two points of X and Y.
The brightness data obtained by dividing the difference at each point on the long axis of the coordinate values is divided, the brightness data is stepped in accordance with the step of the long axis, and the output data of the brightness DDA is used as shading data. do. 3. Explanation of the hour wheel in the figure Figure 1 is a conceptual diagram of the vector generator 1, division value register 2, adder 3, register 4, counter Figure 2 is the vector definition command with luminance information Figure 3 is the present invention Shading circuit 5, division value register 6, adder 7, register 8, division value register 9, adder 10, register 11, division value register 120 . Adder 13, register 14, counter 15, multiplexer 16, RAM Figure 4 shows the luminance/R, G, B conversion circuit 17.1B, RAM related to the present invention.

Claims (1)

[Claims] Divide the distance of the other two axes by the longest axis among the distances of the respective coordinate axes connecting the starting point and end point of the three-dimensional vector consisting of the X, Y, and Z coordinate systems, and divide these divided values into each axis. Vector generator provided (DDA=DIGIT
AL DIFFERE-NCIAL ANALIZER
), and has a 3-axis DDA that interpolates from the 3-dimensional starting point coordinates to the ending point coordinates using a sequence of coordinate points. In a system that uses Z-buffer data to remove hidden surfaces, set brightness data at the start and end points of the vector, find the difference in brightness between these two points, and calculate the difference between two points among the X and Y coordinates. A first means for loading the divided value by dividing the difference value by a value with a large distance therebetween and interpolating up to the end point brightness; and a distance between two points among the X and Y coordinates. The carry signal of the decimal point arithmetic unit of the DDA on the side where
A second means uses the interpolated data obtained by the luminance DDA as a step clock of A, and uses the DDA luminance data as a compensation value as an address of a RAM that stores data for compensating the nonlinear characteristics of the fluorescent material of the monitor. and converting the correction values into pixel data of the image memory in parallel synchronization with the step of the three-axis DDA, and also have third means for controlling writing to the image memory by comparing and determining the Z buffer. shading circuit.