JP2525353Y2 - 半導体装置用回路基板 - Google Patents

半導体装置用回路基板

Info

Publication number
JP2525353Y2
JP2525353Y2 JP1990009482U JP948290U JP2525353Y2 JP 2525353 Y2 JP2525353 Y2 JP 2525353Y2 JP 1990009482 U JP1990009482 U JP 1990009482U JP 948290 U JP948290 U JP 948290U JP 2525353 Y2 JP2525353 Y2 JP 2525353Y2
Authority
JP
Japan
Prior art keywords
tab tape
wiring board
printed wiring
circuit board
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1990009482U
Other languages
English (en)
Japanese (ja)
Other versions
JPH03101529U (US20100223739A1-20100909-C00005.png
Inventor
久夫 新井
憲司 坊野
幸治 今井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chichibu Fuji Co Ltd
Original Assignee
Chichibu Fuji Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chichibu Fuji Co Ltd filed Critical Chichibu Fuji Co Ltd
Priority to JP1990009482U priority Critical patent/JP2525353Y2/ja
Publication of JPH03101529U publication Critical patent/JPH03101529U/ja
Application granted granted Critical
Publication of JP2525353Y2 publication Critical patent/JP2525353Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

Landscapes

  • Wire Bonding (AREA)
JP1990009482U 1990-01-31 1990-01-31 半導体装置用回路基板 Expired - Fee Related JP2525353Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990009482U JP2525353Y2 (ja) 1990-01-31 1990-01-31 半導体装置用回路基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990009482U JP2525353Y2 (ja) 1990-01-31 1990-01-31 半導体装置用回路基板

Publications (2)

Publication Number Publication Date
JPH03101529U JPH03101529U (US20100223739A1-20100909-C00005.png) 1991-10-23
JP2525353Y2 true JP2525353Y2 (ja) 1997-02-12

Family

ID=31513082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990009482U Expired - Fee Related JP2525353Y2 (ja) 1990-01-31 1990-01-31 半導体装置用回路基板

Country Status (1)

Country Link
JP (1) JP2525353Y2 (US20100223739A1-20100909-C00005.png)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03129745A (ja) * 1989-10-16 1991-06-03 Sumitomo Bakelite Co Ltd 半導体装置の実装方法

Also Published As

Publication number Publication date
JPH03101529U (US20100223739A1-20100909-C00005.png) 1991-10-23

Similar Documents

Publication Publication Date Title
JP6496571B2 (ja) 極薄埋め込み型半導体デバイスパッケージおよびその製造方法
JP3619395B2 (ja) 半導体素子内蔵配線基板およびその製造方法
JP5100081B2 (ja) 電子部品搭載多層配線基板及びその製造方法
JP3176307B2 (ja) 集積回路装置の実装構造およびその製造方法
US5631497A (en) Film carrier tape and laminated multi-chip semiconductor device incorporating the same
JP2748768B2 (ja) 薄膜多層配線基板およびその製造方法
JP3838331B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JPH0669402A (ja) プリント基板およびその製造方法
US20140085833A1 (en) Chip packaging substrate, method for manufacturing same, and chip packaging structure having same
JP3951409B2 (ja) Icカードとその製造法
JPH0922963A (ja) 半導体回路素子搭載基板フレームの製造方法
JP4694007B2 (ja) 三次元実装パッケージの製造方法
KR101231286B1 (ko) 부품 내장형 인쇄회로기판 및 그 제조 방법
JP5539453B2 (ja) 電子部品搭載多層配線基板及びその製造方法
JP3930222B2 (ja) 半導体装置の製造方法
JP2833642B2 (ja) 多層配線基板及びその製造方法
JP2525353Y2 (ja) 半導体装置用回路基板
JP2525354Y2 (ja) 半導体装置
JP2784524B2 (ja) 多層電子部品搭載用基板及びその製造法
JPH02164096A (ja) 多層電子回路基板とその製造方法
JPS62114247A (ja) 電子素子用チツプキヤリアの製造法
JP2509095Y2 (ja) 半導体装置
JP3168731B2 (ja) 金属ベース多層配線基板
JPH05327156A (ja) プリント回路基板
JPS6149499A (ja) フレキシブル多層配線基板

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees