JP2521911B2 - Video printer - Google Patents

Description

TECHNICAL FIELD The present invention relates to a video printer.

[Outline of Invention]

The present invention relates to a video printer, and writes a plurality of time-series unit video signals in a plurality of memory areas of a memory in a predetermined order, and time-sequentially writes the plurality of unit video signals written in the plurality of memory areas of the memory. Read along,
A plurality of images corresponding to the read out plurality of unit video signals are printed on a recording medium in a predetermined arrangement in time series, so that a decomposed image of a subject having a relatively fast movement Is obtained quickly and at low cost.

[Conventional technology]

For example, as a means of analyzing the movement of a person who is playing golf or tennis and judging the quality of the form, VT
R, high-speed shooting using a motor drive type high-speed camera, multiple exposure using a strobe of a film-type camera, continuous shooting using an instant camera, etc.

[Problems to be solved by the invention]

However, when a VTR is used, it is not possible to obtain a hard copy immediately from the recorded video signal, and when a camera is used, it takes time to obtain a hard copy and the cost is high. is there.

Therefore, a video printer (Japanese Patent Laid-Open No. 59-226583)
If a hard copy is used, the cost required for the hard copy can be reduced. However, there is a drawback that it takes several seconds to several tens of seconds to obtain one hard copy.

In view of such a point, the present invention intends to propose a video printer that can quickly obtain a separated image of a subject having a relatively fast motion.

[Means for solving problems]

A video printer according to the present invention is a video printer that prints a plurality of images on a recording paper in a predetermined arrangement in time series, and is configured with one screen per field memory for storing a plurality of unit video signals. After multiple field memories and startup operations are performed,
Trigger pulse generating means for generating a write command trigger pulse for instructing the timing of writing the unit video signal to the plurality of field memories, and the horizontal and vertical directions of the unit video corresponding to the unit video signal at each arrival of the write command trigger pulse. Each of the above is thinned out to 1 / n (where n is an integer of 2 or more), and n × n thinned unit video signals per field memory are stored in a predetermined memory area of the field memory.
At the time of recording, writing control means for controlling writing so that unit images are time-sequentially displayed over a plurality of screens, and after completion of writing a plurality of unit image signals in the field memory, the video signals written in the plurality of field memories are A recording control unit that controls the recording unit to sequentially record on the recording medium for each field memory is provided.

[Action]

According to the present invention, each time the write command trigger pulse arrives, the horizontal and vertical directions of the unit image corresponding to the unit image signal are thinned out to 1 / n (where n is an integer of 2 or more) and the field memory is thinned out. In the predetermined memory area, n × n thinned unit video signals per field memory are write-controlled by the write control means so that the unit videos are time-series over a plurality of screens at the time of recording, After writing the multiple unit video signals to the field memory,
To record the video signals written in the plurality of field memories sequentially on the recording medium for each field memory,
The recording control means controls the recording means.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. First, the overall configuration of the video printer will be described with reference to FIG.

(21) is a television camera, which is a composite video signal (composite color video signal or composite monochrome video signal).
(Composite video signal from VTR etc. is also possible) is a video amplifier (22)
Is supplied to the A / D converter (23) through the, and only the video signal portion thereof is converted into, for example, a 4-bit (16 gradations) digital video signal. This digital video signal is a memory (24)
To be written to.

The memory (24) is composed of, for example, four field memories (dynamic RAMs) M _{1 to} M ₄ each having 4 bits. These memories M _{1 to} M ₄ are connected to the memory control circuit (2
The write control section (28a) of 8) controls the writing, and the refresh control section (28b) controls the refresh. The composite video signal from the amplifier (22) is supplied to the sync separation circuit (31), from which the vertical and horizontal sync signals are separated, and this is supplied to the memory control circuit (28).

The video signals read from the memories M _{1 to} M ₄ are supplied to the output switch circuit (25) to be switched and selected, and then supplied to the data converter (26) in accordance with the digital level of the video signals. The pulse width is converted into a pulse width modulated line image signal, which is supplied to the thermal head (27).
The thermal head (27) is composed of, for example, 640 heating resistance elements arranged in one line. And
The roll-shaped heat-sensitive memory paper (32) (FIG. 3) is transferred in the direction orthogonal to the arrangement direction of the heating resistance elements of the head (27) so as to face the heating resistance elements. The output switch circuit (25) is an output control unit (28) of the memory control circuit (28).
c) switching control, and data converter (2
6) and the head (27) are controlled by the print control circuit (29). Further, the memory control circuit (28) is controlled by the print control circuit (29). The memory control circuit (28) also includes a read control unit, but the illustration thereof is omitted here. A commander (30) remotely commands writing to the memory (24).

Next to be described with reference to Figure 2 for the memory M ₁ ~M _4. Each of these memories M _{1 to} M ₄ has memory areas a to d that are divided into four equal parts. Here, the horizontal direction of the video signal (television signal) is the direction orthogonal to the longitudinal direction of the roll-shaped recording paper (32) shown in FIG. 3, and the vertical direction is the longitudinal direction of the roll-shaped recording paper (32). The image is printed to match. Each memory area a of each memory M _{1 to} M ₄
The video signal in the horizontal direction and the vertical direction in the vertical direction is, for example, 1 / d.
It is thinned out to 2 and written respectively.

In this case, the camera (21) is rotated 90 degrees in the imaging plane from the normal use state and used. Therefore,
For example, when a unit image based on the video signal written in the memory M ₁ was printed on the recording paper (32), it was divided into four equal parts of the original one screen P ₁ as shown in FIG. Images (2), (10), (1), and (9) are formed on the screen portions A to D.

Then, in each of the memory areas a to d of the memories M _{1 to} M ₄ ,
As shown in FIG. 2, unit video signals (field signals) (1) to (16) are written in chronological order. That is,
The memory area a~d of memory M _1, unit video signal (2), (10), (1) and (9) are written. In the memory areas a to d of the memory M ₂ , the unit video signal (4),
(12), (3) and (11) are written. In the memory areas a to d of the memory M ₃ , unit video signals (6), (14),
(5) and (13) are written. In the memory areas a to d of the memory M ₄ , unit video signals (8), (16), (7),
(15) is stored.

By doing so, each of the four unit video signals stored in the memories M _{1 to} M ₄ is read out as one video signal, and as shown in FIG. 3, the screens are sequentially displayed on the recording paper (32). P ₁ each screen section C of to P _4, each screen section D of the a and screen P ₁ to P _4, a B, when along the sequence ordered field image in two rows (1) to (16) is printed To be done.

It should be noted that the horizontal direction of the television screen may coincide with the longitudinal direction of the recording paper (32), and the vertical direction thereof may coincide with the direction orthogonal to the longitudinal direction of the recording paper (32). by changing the allocation to each of four memory areas a~d of memory M ₁ ~M ₄ of unit video signal can be an array of print image on the recording paper (32) as in the third FIG.

Next, an example of the memory (24) will be described. The memory (24) used in this embodiment employs a serial-in / serial-out type dynamic RAM. A specific example is shown in FIG. 5 and will be briefly described. FIG. 5 shows the structure of the dynamic RAM of the μPD41221C manufactured by NEC Corporation, which will be described below.

(50) is a memory cell array of 320 rows × 700 columns (224 Kbits). Reference numeral (51) is a 700-bit line buffer, and 700 transfer gates (52) are interposed between the line buffer and the memory cell array (50). The line buffer (51) is controlled by the timing generation circuit (55). The timing generation circuit (55) is supplied with the data transfer / restore control clock signal ▲ ▼ and the refresh control clock signal ▲ ▼.
The data transfer gate (52) is controlled by the read / write timing generation circuit (57). A read / write control signal ▲ ▼ is supplied to the read / write timing generation circuit (57). (59) is a data input / output buffer, to which input data Din is supplied and from which output data Dout is output. 700 gates (54) are interposed between the data input / output buffer (59) and the line buffer (51). (53) is a serial selector for controlling the gate (54). This serial selector (53) includes a timing generation circuit (5
5) and serial control timing generator (5
8) controlled by. A serial control clock signal ▲ ▼ is supplied to the serial control timing generation circuit (with built-in counter) (58).

(60) is a refresh address counter, (56) is a row address counter, and the parallel outputs of both are sequentially passed through an address selector (61), an address input buffer (62) and an address decoder (63) to form a memory cell array. Supplied to (50). The row address counter (56) has
A row counter reset clock signal ▲ ▼, a row counter increment clock signal ▲ ▼ and a row counter decrement clock signal ▲ ▼ are supplied.
The row address counter (56), the refresh address counter (60), the address selector (61), the address input buffer (62) and the address decoder (63) are controlled by the timing generation circuit (55). The read / write timing generation circuit (57) is a timing generation circuit (55)
The serial control timing generation circuit (58) is controlled by the read / write timing generation circuit (57) and the data input / output buffer (59).
Are controlled by a serial control timing generation circuit (58).

Next, the operation of this dynamic RAM will be described with reference to the above-mentioned signals.

Clock signal ▲ ▼ The clock signal ▲ ▼ controls the read / write operation of data of one row between the memory cell array (50) and the line buffer (51) according to the level of the control signal ▲ ▼ (data transfer / Restore cycle).

Control signal ▲ ▼ The control signal ▲ ▼ controls the data transfer / data restore cycle and the serial read / write cycle. The control signal ▲ ▼ determines its operation at the falling edge of the clock signal ▲ ▼ in the case of data transfer / data restore cycle, and the falling edge of the clock signal ▲ ▼ in the case of serial read / write cycle. To be done.

Clock signal ▲ ▼ The clock signal ▲ ▼ controls the serial read / write operation of the line buffer (51).

Clock signal ▲ ▼ Clock signal ▲ ▼ is the clock signal ▲ ▼
Is input during the inactive period, the on-chip refresh by the built-in refresh control circuit is executed.

Clock signals ▲ ▼, ▲ ▼ and ▲ ▼ Clock signals ▲ ▼, ▲ ▼ and ▲ ▼
To the row address counter (56),
Control that row address. Clock signal ▲ ▼ is row address increment (+1), clock signal ▲
▼ performs row address decrement (-1), and clock signal ▲ ▼ performs row address counter reset.

Then, each of the memories M ₁ to M of the memory (24) shown in FIG.
As M ₄ , _four dynamic RAMs shown in FIG. 5 are used.

Next, the memory control unit (28) of the memory control circuit (28) of FIG. 1 when the dynamic RAM of FIG. 5 is used as each of the memories M _{1 to} M ₄ of the memory (24).
The configuration of a) will be described with reference to FIG. Input terminal (7
The clock signal ▲ ▼ described above is supplied to 0).
A sync signal [vertical and horizontal sync signals from the sync separation circuit (31)] is supplied to the input terminal (71). A write command pulse from the commander (30) is supplied to the input terminal (72).

The clock signal ▲ ▼ is supplied to the frequency dividing circuit (73), is synchronized with the synchronizing signal and is frequency-divided, and the frequency-divided output is supplied to the control pulse generating circuit (74). ▲ ▼, control signal ▲ ▼, clock signal ▲ ▼ and clock signal ▲ ▼ are output.

Further, (75) is an allocation control circuit, to which a synchronizing signal is supplied. Further, the write command pulse is supplied to the frequency dividing circuit (76) and divided into 1/2, 1/4, and 1/8, respectively, and the respective frequency division outputs are supplied to the allocation control circuit (75). . And this allocation control circuit (7
Control signals from 5) to each part are output.

(87) to (91) are changeover switches, which have fixed contacts a and b and a movable contact c, respectively, and are switched in conjunction with each other by the output from the allocation control signal (75). When printing one image on both sides of the recording paper (32), the movable contacts c of the changeover switches (87) to (91) are placed on the fixed contact a side and one of the recording paper (32) is moved. When printing four images on the screen, the changeover switch (87) ~
The movable contact c of (91) is switched to the fixed contact b side. Clock signal from input terminal (70) and clock signal from control pulse generator (74)
▼, ▲ ▼, ▲ ▼ and ▲ ▼ are respectively supplied to the fixed contacts a of the changeover switches (88) to (91), and their 1/2 frequency divider (82) and 1/2 thinning gate (83) to (86)
The signal divided by 1/2 by the changeover switch (87)
Is supplied to each fixed contact b of (91). Each clock signal from the movable contacts c of the changeover switches (87) to (91) is changed over by the changeover switch (92), and each memory M ₁
~ M ₄ supplied. And the frequency divider (82), gate (8
3) to (86) and the change-over switches (87) to (91) and (92) are controlled by the allocation control circuit (75).

Next, a specific configuration of the allocation control circuit (75) shown in FIG. 6 will be described with reference to FIG. FIG. 9E-
N shows the waveform of the signal of each part in FIG. The frame synchronization signal VF (FIG. 9F) is supplied to the NOR gate (108), and this frame synchronization signal VF is supplied to another NOR gate (109) through the inverter (110). Vertical sync signal ▲ ▼ (Fig. 9E) is NOR gate (108), (109)
Is supplied to. From these NOR gates (108) and (109), the phases are 180 degrees different from each other, and the frequency is 1/2 the frequency of the vertical synchronizing signal ▲ ▼ (1/2) ▲ ▼ ₁ , (1 /
2) ▲ ▼ ₂ (Fig. 9, G, H) is obtained. A write command pulse (FIG. 9I) is supplied to the D-type flip-flop circuit (101) as a clock signal. "1" is supplied to the D input terminal of the flip-flop circuit (101). The inverted output of the flip-flop circuit (101) is NOR
It is supplied to the gate (106) and the D input terminal of the other flip-flop circuit (103). Flip-flop circuit (10
The signal (1/2) ₂ from the NOR gate (109) is supplied to the clock input terminal of 3). Also, this signal (1 /
2) ▲ ▼ ₂ is supplied to the NOR gate (106) through the inverter (107). The non-inverted output of the flip-flop circuit (103) is the read / write mode signal R / (9th
Figure J).

The inverted output of the flip-flop circuit (103) and the output of the NOR gate (108) are supplied to the NAND gate (112). NA
The output of the ND gate (112) is a flip-flop circuit (101).
Reset input terminal and other flip-flop circuit (10
It is supplied to the clock input terminal of 5). NOR gate (10
The output of 9) is supplied to the reset input terminal of the flip-flop circuit (105) through the inverter (113). The output of the NOR gate (106) is supplied to the clock input terminal of the flip-flop circuit (104), the reset input terminal is supplied with the reset signal ▲ ▼, and the inverted output thereof is supplied to the D input terminal. Then, the inverted output of the flip-flop circuit (104) and the output of the inverter (110)
It is supplied to the EX-OR gate (114). The output of the EX-OR gate (114) and the vertical synchronizing signal () are supplied to the NOR gate (115). The output of the NOR gate (115) is supplied to the gate (85) as a gate signal.

Horizontal sync signal ▲ ▼ is the flip-flop circuit (10
It is supplied to the clock input terminal of 2), the reset signal ▲ ▼ is supplied to its reset input terminal, and its inverted output is supplied to the D input terminal. Then, the inverted output of the flip-flop circuit (102) is supplied to the gate (83) as a gate signal. Flip-flop circuit (10
The inverted output of 5) and the inverted output of the flip-flop circuit (102) are supplied to the NAND gate (116), and the output thereof is supplied to the gate (84) as a gate signal.

The inverted output of the flip-flop circuit (105) is supplied to the clock input terminal of the frequency divider (4-bit counter) (117), and the reset signal is input to its clear signal input terminal.
▼ is supplied. The 4-bit parallel output of the frequency divider (117) is supplied to the changeover switch (92) as a changeover signal and also to a memory changeover display device (not shown). The non-inverted output of the flip-flop circuit (102) and the 1-bit output of the 2 ² digit of the frequency divider (117) are supplied to the EX-OR gate (111), and the output thereof is supplied to the gate (86).
▼ Supplied as a gate signal.

Next, the divided writing of the video signal into the memory of FIG. 5 will be described, but prior to that, in order to facilitate the understanding of the explanation, full writing of the video signal into the memory, partial writing, etc. will be described. First, with reference to FIGS. 8A to 8F, normal full-face writing to the memory will be described. At the timing of [T], control signal ▲
▼ (Fig. 8B) is "1", clock signal ▲
At the fall of ▼ (FIG. 8A), the data of the line buffer (51) is transferred from the memory cell array (50), and the clock signal ▲ ▼ is supplied to the row address counter (56) once, thereby Advance by one line. Serial control timing generator (5
By supplying 640 clock signals ▲ ▼ in the video section of 1 horizontal cycle to 8), input data Din
640 pixel signals are sequentially written in the line buffer (51). After that, when the control signal ▲ ▼ (Fig. 8B) is "0", the video signal of one line is transferred from the line buffer (51) to the memory cell array (50) at the timing of [R] due to the fall of the clock signal ▲ ▼. To transfer. By repeating this 240 circuits per field, field data composed of 640 × 240 pixel data is written in the memory cell array (50). Thereafter, the clock signal ▲ ▼ is supplied to the row address counter (56), and this counter (56) is reset. The memory is refreshed by supplying the clock signal ▲ ▼ to the timing generation circuit (55) while transferring data to the line buffer (51) asynchronously with the writing.

Next, the operation for writing a video signal in the left half of the memory cell array (50) will be described with reference to FIGS. In this case, the clock signal ▲ ▼ (FIG. 8G), the control signal ▲ ▼ (FIG. 8H), the clock signal ▲
▼ (Fig. 8I) and clock signal ▲ ▼ (8th
In Fig. J), the frequencies are both halved as compared with the signals of Figs. 8A, 8B, 8C and 8D, respectively. Clock signal ▲
Only 320 of ▼ are supplied to the serial control timing generation circuit (58) in the video period of one line.
Therefore, every other 320 pixel signals are written in the memory cell array (50) in the time for one line. Then, as shown in FIG. 8H, when the 1st to 320th clock signals ▲ ▼ in one line are generated, the control signal ▲
▼ is set to “0” and the 32nd to 640th clock signals ▲
When ▼ is generated, if it is set to "1", the video signal for one line is written in the left half of the memory cell array (50), and the data on the second line following this is a dummy cycle that advances by the address. , Is not written in the memory cell array (50). Thus 1, 3, 5, ...
..The video signal of the odd-numbered line is the memory cell array (5
It is written in the left half of 0).

The operation for writing a video signal in the right half of the memory cell array (50) is the same as that of the eighth embodiment corresponding to FIGS.
It is easily understood by the drawings K to N, but in this case the eighth
As shown in FIG. L, the polarity of the control signal ▲ ▼ is shown in FIG.
You can reverse the above.

Next, with reference to FIGS. 9A to 9D, the case of writing the video signal in the upper half or the lower half of the memory will be described. FIG. 9A shows the vertical synchronizing signal ▲ ▼. Clock signal ▲
After the row address counter (56) is reset by ▼ (Fig. 9D), the row address counter (56) is reset.
Every other line, clock signal ▲ ▼ (Fig. 9C)
Is supplied, the video signals for 120 lines are written in the memory cell array (50) in one vertical cycle period. The clock signal ▲ ▼ is 24
When the control signal ▲ ▼ is supplied to the 0-row address counter (56) and the control signal ▲ ▼ is set to "1" in the first half and the line address advances to 121 to 240, the control signal ▲ ▼ is set to "0". The video signal is written in the lower half. The clock signal () is supplied to the row address counter (56) every other vertical cycle.

Next, referring to FIGS. 9E to N, the video signal is written in each of the four divided memory areas a to d of the memories M _{1 to} M ₄ of FIG. 1 (FIG. 2) related to FIG. 7. The operation will be described. When a write command pulse is generated from the commander (30) as shown in FIG. 9I, a control signal ▲ ▼ is generated after a predetermined time.
(Fig. 9K) occurs. By moving the clock signal ▲ ▼ supplied to the row address counter (56) for each of the memories M _{1 to} M ₄ , the memory storage area is switched between the upper half and the lower half. The generation of the write command pulse is fixed so that the control signal () will be generated in the second field later. On the other hand, the frame synchronization signal VF (FIG. 9F) is inverted every time a command pulse is generated, and the inverted frame synchronization signal (L in FIG. 9) and the vertical synchronization signal are inverted by the NOR gate (109) (seventh).
(Figure) and take the AND, the clock signal ▲ ▼ is synchronized with the vertical synchronization signal ▲ ▼ before the first field.
Occurs and the clock signal {circle around (2)} occurs in synchronism with the vertical synchronization signal {circle around (2)} immediately before the second field. Since the control signal ▲ ▼ can be generated in the second field, the time of the first field becomes a dummy cycle in the former case, the video signal is written in the lower half of the memory, and the clock signal ▲ in the latter case. Immediately after ▼, the control signal ▲ ▼ is generated, and the video signal is written in the upper half of the memory. Thus, even if a write request comes every other field, the video signal can be written with a predetermined correct allocation.

As shown in FIG. 10, the allocation control circuit of FIG. 7 corresponds to the write command pulse of FIG.
As shown in FIG. D, the supply of the clock signal and the control signal to the memories M _{1 to} M ₄ is controlled in every four cycles of the write command pulse, and the writing area for each of the memories M _{1 to} M ₄ is shown in FIG. B, is switched as shown and C, thereby by sequentially reading the video signal written to each respective entire screen from the memory M ₁ ~M _4, each of the plurality of memory areas of the memory M ₁ ~M ₄ to d The plurality of unit video signals written in the are read out in time series and printed by the printing means as shown in FIG.

If a write request arrives for all fields,
By continuously generating the control signal {circle around (1)} as shown in FIG. 11, continuous writing to the memory becomes easy. This is suitable when the movement of the subject is quite fast.

〔The invention's effect〕

According to the present invention described above, it is possible to obtain a video printer which can quickly, easily and at low cost obtain a decomposed image of an object having a relatively fast motion.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video printer according to the present invention, FIG. 2 is an explanatory diagram of a storage area of a memory, FIGS. 3 and 4 are explanatory diagrams of respective print images, and FIG. FIG. 6 is a block diagram of a memory, FIG. 6 is a block diagram of a write control unit, FIG. 7 is a circuit diagram of an allocation control circuit, and FIGS. 8, 9, 10, and 11 are time charts, respectively. . (24), M _{1 to} M ₄ are memories, a to d are memory areas,
(50) is a memory cell array, (51) is a line buffer,
(28) a memory control circuit (32) is a recording sheet, P ₁ to P ₄ are screen, to D the screen portion (75) is the allocation control circuit.

Claims (1)

(57) [Claims] 1. A video printer for printing a plurality of images on a recording paper in a time-sequentially arranged state, a plurality of one field memory for storing a plurality of unit video signals. Field memory, a trigger pulse generating means for generating a write command trigger pulse for instructing the timing of writing the unit video signal to the plurality of field memories after the start operation, and the arrival of the write command trigger pulse. Each 1 / horizontal and vertical direction of the unit image corresponding to the unit image signal
n (where n is an integer of 2 or more) is thinned out to a predetermined memory area of the field memory, and n × n thinned unit video signals are recorded per field memory over a plurality of screens at the time of recording. Write control means for controlling writing so that the unit video is in time series; and after completion of writing the plurality of unit video signals in the field memory, the video signals written in the plurality of field memories for each field memory. A video printer comprising: a recording control unit that controls the recording unit to sequentially record on a recording medium.