JPS62289072A - Video printer - Google Patents

Abstract

PURPOSE:To quickly obtain the split images of an object with a comparatively quick move by writing and reading plural time-sequential unit video signals in plural memory areas in the required order and printing them on a recording medium in the required array. CONSTITUTION:A composite video signal from a television camera 21 used by rotating by 90 deg. in an image pickup plane from a normal use state is supplied to a memory 4 through an AD converter 23. The memory 24 is composed of field memories M1-M4. An output switching circuit 25 switches and selects a video signal that is written in a memory 24 and read out of it, and supplies said signal to a thermal head 27 through a data converter 26. The time- sequential unit video signals 1-16 are written in the memory areas (a)-(d) in the memories M1-M4, and four unit video signals are read as one video signal. Images 1-16 arrayed in two lines time-sequentially are printed in a recording paper 32.

Description

[Detailed description of the invention] Detailed description of the invention [Industrial application field] The present invention relates to video printers.

[Summary of the invention]

The present invention relates to a video printer that writes a plurality of time-series unit video signals to a plurality of memory areas of a memory in a predetermined order, and writes a plurality of unit video signals written to the plurality of memory areas of the memory in a time-series manner. , and prints a plurality of images corresponding to the plurality of read unit video signals on a recording medium in a predetermined arrangement state along the time series. This allows decomposed images of a certain subject to be obtained quickly and at low cost.

[Conventional technology]

For example, VT is a method for analyzing the movements of people playing golf or tennis and determining the quality of their form.
R, high-speed photography using a motor drive type high-speed photography camera, multiple exposure using a strobe of a film type camera, continuous photography using an instant camera, etc.

[Problem that the invention seeks to solve]

However, when using a VTR, it is not possible to immediately obtain a hard copy from the recorded video signal, and when using a camera, it takes time and is expensive to obtain a hard copy. .

Therefore, if a video printer (Japanese Patent Application Laid-open No. 51-226583, Japanese Patent Application Laid-Open No. 5!J-226584, etc.) is used, the cost required for hard copying can be reduced. However, it has the disadvantage that it takes several seconds to several tens of seconds to obtain one hard copy.

In view of this point, the present invention seeks to propose a video printer that can quickly obtain decomposed images of relatively fast-moving objects.

[Means for solving problems]

The video printer according to the present invention stores a plurality of unit video signals in time series in a plurality of memory areas a of a memory (24).
-d in a predetermined order, and reading means (28) for reading out the plurality of unit video signals written in the plurality of memory areas a-d of the memory (24) in time series. , printing means (27) for printing a plurality of images corresponding to the plurality of unit video signals read out by the reading means (28) onto a recording medium (32) in a predetermined arrangement state in chronological order; It is characterized by having the following.

[Effect]

According to the present invention, a plurality of images corresponding to a plurality of unit video signals are printed on the recording medium (32) in a predetermined arrangement state in chronological order, and a decomposed image of a subject moving relatively quickly is printed. can be obtained quickly.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. First, the overall configuration of a video printer will be described with reference to FIG.

(21) is a TV camera, which receives a composite video signal (
composite color video signal or composite monochrome video signal) (
Composite video signals from a VTR, etc. are also possible) is connected to a video amplifier (22
) is supplied to the A/D converter (23), and only the video signal portion thereof is converted into, for example, a 4-bit (16 gradation) digital video signal. This digital video signal is supplied to the memory (24) and written therein.

This memory (24) includes, for example, four field memories (Guinamink RAM) Ml to M of 4 bits each.
It consists of 4. These memories M.

~M4 is the write control unit (
The write is controlled by the memory 28a), and the refresh is controlled by the refresh control unit (28b). The composite video signal from the amplifier (22) is supplied to the sync separation circuit (31), which separates the vertical and horizontal sync signals, which are then sent to the memory control circuit (2).
8).

The video signals read out from the memories M1 to M4 are supplied to the output switch circuit (25) and are switched and selected.
The signal is supplied to a data converter (26), where it is converted into a pulse width modulated line video signal having a pulse width corresponding to the digital level of the video signal, and this is supplied to a thermal head (27). This thermal head (27) is composed of, for example, 640 heating resistive elements arranged in one row.

Then, a roll of thermal recording paper (32) (FIG. 3) is moved in a direction perpendicular to the arrangement direction of the heat generating resistive elements of the head (27) and facing the heat generating resistive elements.

The output switching circuit (25) is the memory control circuit (28)
Switching control is performed by the output control section (28C) of. The data converter (26) and head (27) are also controlled by a print control circuit (29). Furthermore, the memory control circuit (28) is controlled by the print control circuit (29). The memory control circuit (28) also includes a read control section, but its illustration is omitted here. (30) is a commander that remotely commands writing to memory (24).

Next, the memories M and -M4 will be explained with reference to FIG. These memories M1 to M4 include memory areas a to d divided into four equal parts.

Here, the horizontal direction of the video signal (television signal) is a direction perpendicular to the longitudinal direction of the roll of recording paper (32) shown in FIG. 3, and the vertical direction is the direction of the roll of recording paper (32).
The image is printed so that it matches the longitudinal direction of the image.

The video signal is thinned out by half, for example, in the horizontal and vertical directions and written into each memory area a to d of each memory M1=M4.

In this case, the camera (21) is used after being rotated 90 degrees within the imaging plane from the normal use state. Therefore, for example, when a unit image based on the video signal written in the memory M1 is printed on the recording paper (32), as shown in FIG. Images (2), (10), (1), (
9) is formed.

As shown in FIG. 2, each unit video signal (
Field signals) (1) to (16) are written. That is, unit video signals (2), (10), (1), and (9) are written in memory areas a to d of the memory M1.

Memory areas a to d of memory M2 contain unit video signals (
4), (12), (3), and (11) are written. A unit video signal (
6), (14), (5), and (13) are written. Unit video signals (8), (16), (7), and (15) are stored in the memory area a%d of the memory M4.

By doing this, by reading out each of the four unit video signals stored in the memories M1 to M4Q as one video signal, the recording paper (32
), each screen section C, A of screens P1 to P4 and each screen section of screens P1 to P4 are shown in sequence, and field images (1) to (16) arranged in two lines in chronological order are shown on B. is printed.

Note that the horizontal direction of the television screen may be made to match the longitudinal direction of the recording paper (32), and the vertical direction may be made to match the direction perpendicular to the longitudinal direction of the recording paper (32).
In that case, each 4tl of memories M1 to M4 for unit video signals
By changing the allocation of lil to the memory areas 3aa to 3d, the arrangement of print images on the recording paper (32)l can be made similar to that shown in FIG.

Next, an example of the memory (24) will be explained. The memory (24) used in this embodiment is a serial-in/serial-out type dynamic RAM, a specific example of which is shown in FIG. 5 and will be briefly described. This figure 5 shows μPD4122 IC manufactured by NEC Corporation.
The configuration of the Guinami Soku RAM is shown below, and will be explained below.

(50) is a memory cell array of 320 rows x 700 columns (224 bits). (51) is a 700-bit line buffer, and the memory cell array (50)
700 transfer gates (52) are interposed between the two. This line buffer (51) is controlled by a timing generation circuit (55). This timing generation circuit (55) is supplied with a data transfer/restore control lock signal and a refresh control clock signal. This data transfer gate (52) is controlled by a read/write timing generation circuit (57). A read/write control signal Vfl is supplied to the read/write timing generation circuit (57). (59
) is a data input/output cover sofa, and the input data Din is input to this.
is supplied, and output data Dout is also output from this point. 700 gates (54) are interposed between the data input/output cover sofa (59) and the line buffer (51). (53) is this gate (54
) is a serial selector for controlling. This serial selector (53) is connected to a timing generation circuit (55).
and serial control timing generation circuit (58)
controlled by

Serial control timing generation circuit (counter I
'[) (58) is supplied with a serial control clock signal.

(60) is the refresh address counter, (56)
is a row address counter, and each parallel output of both is supplied to the memory cell array (50) through an address selector (61), an address input cover sofa (62) and an address decoder (63) in sequence. The row address counter (56) includes the row counter center cross signal section ■,
A row counter increment clock signal ``and a row counter decrement clock signal r are supplied.A row address counter (56), a refresh address counter (
60), an address selector (61), an address cover sofa (62) and an address decoder (63) are controlled by a timing generation circuit (55). Lead/
The write timing generation circuit (57) is controlled by the timing generation circuit (55), the serial control timing generation circuit (58) is controlled by the read/write timing generation circuit (57), and the data input/output cover sofa (59) is controlled by the serial control timing generation circuit (58). It is controlled by a control timing generation circuit (58).

Next, the operation of this RAM will be explained in relation to each of the above-mentioned signals.

Clock Signal Amount The clock signal amount is determined by the level of the control signal W1 to transfer one row of data to the memory cell array (5
0) and the line buffer (51) (data transfer/restore cycle)
.

Control Signal W1 Control signal W controls data transfer/data restore cycles and serial read/write cycles. This control signal ffl is applied at the falling edge of the clock signal amount in a data transfer/data restore cycle.
In the case of a serial read/write cycle, each operation is determined by the falling edge of the clock signal (2).

Clock signal amount Clock signal amount is determined by line buffer (51) controls serial read/write operations.

Clock Signal - The clock signal lamp is inputted during the period when the clock signal amount is inactive, so that on-chip refresh is executed by the built-in refresh control circuit.

The row address is controlled by supplying the clock signal ``,'' and the clock signal amount, ``and '' to the row address counter (56).The clock signal ■ is the row address increment (+1), and the clock signal is Row address decrement (-1), the clock signal source performs a row address counter reset.

Then, each memory M of the memory (24) in FIG.
Four of the Guinami Soku RAMs shown in FIG. 5 are used as 1 to M4.

Next, each memory M1 to M4 of the above-mentioned memory (24)
The configuration of the memory control section (28a) of the memory control circuit (28) of FIG. 1 when the Guinami Soku RAM of FIG. 5 is used will now be described with reference to FIG. 6. The above-mentioned black/7 signal E is supplied to the input terminal (70). A synchronization signal [vertical and horizontal synchronization signals from the synchronization separation circuit (31)] is supplied to the input terminal (71).

A write command pulse from the commander (30) is supplied to the input terminal (72).

The clock signal quantity is supplied to the frequency divider circuit (73), synchronized with the synchronization signal and frequency-divided, and the divided output is supplied to the control pulse generation circuit (74), from which the above-mentioned clock signal quantity , control signal ffl, clock signal source and clock signal! is output.

Further, (75) is an allocation control circuit to which a synchronization signal is supplied. Furthermore, the write command pulse is supplied to the frequency dividing circuit (76) to divide the frequency into 1/2.1/4.1/8, respectively.
The frequency is divided into 1, and each frequency-divided output is supplied to the allocation control circuit (75). Control signals are output from this allocation control circuit (75) to each section.

Changeover switches (87) to (91) each have fixed contacts a, b and a movable contact C, and are switched in conjunction with each other by the output from the allocation control signal (75). When printing one image on one screen of the recording paper (32), the movable contacts C of the changeover switches (87) to (91) are placed on the fixed contact a side, and the movable contacts C of the changeover switches (87) to (91) When printing four images on the screen, the movable contacts C of the changeover switches (87) to (91) are respectively switched to the fixed contact side. The clock signal from the input terminal (7o) and the clock signal from the control pulse generation circuit (74), V'; Part 1
/2 frequency divider (82) and ], /2 decimation gate (83)
- (86), the signal whose frequency is divided into 1/2 is supplied to each fixed contact of changeover switches (87) - (91). Each clock signal from the movable contact C of the changeover switches (87) to (91) is switched by the changeover switch (92) to each memory M.

~M4 is supplied. Then, the frequency divider (82), gates (83) to (86), and changeover switches (87) to (
91) and (92) are the allocation control circuit (75)
) controlled by

Next, the specific configuration of the allocation control circuit (75) in FIG. 6 will be described with reference to FIG. 7. Figure 9 E-
N shows the waveforms of the signals at each part in FIG. A frame synchronization signal VF (FIG. 9F) is supplied to a NOR gate (108), and this frame synchronization signal VF is also supplied to another NOR gate (109) through an inverter (110). Vertical synchronization signal VD (Fig. 9E) is NOR game 1
-(10B), (109). These NO
From the R gates (108) and (109), the phase is 1 to each other.
80 degree difference l9, signal whose frequency is 1/2 of the frequency of vertical synchronization signal V'T5 (1/2) VD+, (1/2)
VT)2 ($9 Figures G, H) are obtained.

A write command pulse (FIG. 9I) is supplied to the D-type flip-flop circuit (101) as a clock signal. The D input terminal of this flip-flop circuit (101) has “
1” is supplied. The inverted output of the flip-flop circuit (101) is supplied to the NOR gate (106) and the D input terminal of another flip-flop circuit (103). The clock input terminal of the flip-flop circuit (103) has N
Signal (1/2) from OR gate (109) V″r52
is supplied. Also, this signal (1/2) V'T52 is passed through the inverter (107) to the 7NOR gate (106).
supplied to The non-inverted output of the flip-flop circuit (103) is the read/write mode signal R/VV (9th
Figure J).

Inverted output of flip-flop circuit (103) and NOR
The output of the gate (108) is fed to a NAND gate (112). The output of the NAND gate (112) is supplied to the positive input terminal of the flip-flop circuit (101) and the clock input terminal of another flip-flop circuit (105). The output of the NOR gate (109) passes through the inverter (113) to the flip-flop circuit (105).
is supplied to the reset input terminal of

The output of the NOR game (106) is supplied to the clock input terminal of the flip-flop circuit (104), the reset signal E is supplied to its reset input terminal, and its inverted output is supplied to its D input terminal. Then, the inverting output of the flip-flop circuit (104) and the inverter (1
The output of 10) is fed to the EX-OR gate (114). The output of this EX-OR gate (114) and the vertical synchronization signal VD are supplied to a NOR gate (115).

The output of this NOR gate (115) is supplied to the gate (85) as a wake-up gate signal.

A horizontal synchronizing signal - is supplied to the clock input terminal of the flip-flop circuit (102), a reset signal port is supplied to its reset input terminal, and its inverted output is supplied to the D input terminal. And a flip-flop circuit (102)
The inverted output of is supplied to the gate (83) as a purchase gate signal.

The inverted output of the flip-flop circuit (105) and the inverted output of the flip-flop circuit (102) are supplied to a NAND gate (116), and the output is applied to the gate (84) at V
ff is supplied as a gate signal.

The inverted output of the flip-flop circuit (105) is sent to the frequency divider (
A chronograph input terminal of a 4-bit counter (117) is supplied, and a reset signal π is supplied to its clear signal input terminal. The 4-bit parallel output of the frequency divider (117) is supplied as a switching signal to a changeover switch (92) and also to a memory switching display device (not shown).

The non-inverting output of the flip-flop circuit (102) and the 1-bit output of the 22nd digit of the frequency divider (117) are EX-ORed.
is supplied to the gate (111), and its output is the gate (86).
) is supplied as the r+ gate signal.

Next, dividing writing of a video signal to the memory shown in FIG. 5 will be explained. Prior to that, in order to make the explanation easier to understand, writing of the entire video signal to the memory, partial writing, etc. will be explained. First, the 8th
Referring to Figures AF, a normal full write to memory will be described.

At timing (T), when the control signal 'ii'fl (B in Figure 8) is 11'', the fall of the clock signal (A in Figure 8) causes the line buffer (51) to be transferred from the memory cell array (50). By transferring data to the row address counter (56) and supplying the clock signal ■ once to the row address counter (56), the address is advanced by one line. By supplying 640 clock signal tickets to the serial control timing generation circuit (58) in a video section of one horizontal cycle, 640 pixel signals of the input data Din are sequentially written into the line buffer (51).

Thereafter, when the control signal WT (FIG. 8B) is "0", the fall of the clock signal word causes the line buffer (51) to be transferred from the memory cell array (5) at the timing (R).
Transfer one line of video signal to 0). By repeating this 240 circuits per field, 640X2
Field data consisting of 40 pixel data is written into the memory cell array (50). A clock signal - is then applied to the row address counter (56) to reset this counter (56). Memory refresh is performed asynchronously with such writing by writing to the line buffer (
This is done by supplying the clock signal W to the timing generation circuit (55) while data is being transferred to the timing generator (51).

Next, the operation for writing a video signal into the left half of the memory cell array (50) will be described with reference to FIGS. 8G-J. In this case, the clock signal π (Fig. 8G), the control signal W (Fig. 8H), and the clock signal π (Fig. 8I) are used.
) and clock signal rw, (Fig. 8J) C, respectively No. 8
Compared to the signals in Figures A, B, and C1D, their frequencies are all 1/
It is now 2. Only 320 clock signals are supplied to the serial control timing generation circuit (58) during one line of video period. Therefore, every other 320 pixel signals are written into the memory cell array (50) in the time for one line.

Then, as shown in FIG. 8H, 1 to 32 in one line.
If the control signal W is set to rOJ when the 0th clock signal intensity is generated, and set to "1" when the 321st to 640th clock signal π is generated, the video signal for 1547 minutes will be transferred to the memory cell array (50 ), and the following second line data becomes a dummy cycle that advances by the address, and the memory cell array (50)
is never written to. Thus, ■, 3.5,
The ...th odd line video signal is written into the left half of the memory cell array (50).

The operation when writing a video signal to the right half of the memory cell array (50) is as shown in FIG.
It is easily understood by -N in the figure, but in this case the 8th
As shown in the figure, the polarity of the control signal ffl may be reversed from that in FIG. 8H.

Next, with reference to FIGS. 9A to 9D, a case will be described in which a video signal is written into the upper half or lower half of the memory. 9th
Figure A shows the vertical synchronization signal V""7N.

After the row address counter (56) is reset by the clock signal (FIG. 9D), the clock signal rl [(FIG. 9C) is supplied to the row address counter (56) every other line. ,■12 in the vertical period
The video signal for 0 lines is written into the memory cell array (50). The clock signal ■ is within two vertical periods,
240 rows are supplied to the address counter (56), and the control signal W is set to "1" in the first half of the row address counter (56).
When the line address advances to 0, the control signal W is set to 0.
”, the video signal is written to the lower half of the memory. The previous clock signal is supplied to the row address counter (56) every vertical period.

Next, with reference to FIGS. 9E-N, the following will explain the
The operation of writing a video signal into each of the four divided memory areas ayd of the memories M1 to M4 in FIG. 1 (FIG. 2) will be explained.

When a write command pulse is generated from the commander (30) as shown in FIG. 9I, a control signal n is generated after a predetermined time.
(K in Figure 9) occurs. The clock signal In supplied to the row address counter (56) is moved for each of the memories M1 to M4 to switch the storage area of the memory between the upper half and the lower half. After the write command pulse is generated, the control signal W7. Fix it so that it occurs. On the other hand, the frame synchronization signal VF (FIG. 9F) is inverted every time a write command pulse occurs, and the inverted frame synchronization signal (FIG. 9L) and vertical synchronization signal are passed through a NOR gate (109) (
(Fig. 7) and AND, the clock signal In is synchronized with the vertical synchronization signal V'IN before the first field.
A case in which this occurs and a case in which clock signal corruption occurs in synchronization with the vertical synchronizing signal 'WN immediately before the second field occur alternately. The control signal W1 can be generated by the second
field, so in the former case, the time of the first field becomes a dummy cycle, and the video signal is written in the lower half of the memory, and in the latter case, the control signal W is generated immediately after the clock signal, and the time of the first field is a dummy cycle. The video signal is written in the upper half.

In this way, even if a write request comes for every other field,
Video signals can be written with a predetermined correct allocation.

In the allocation control circuit of FIG. 7, as shown in FIG. 10, in response to the write command pulse of FIG. 10A, every four cycles of the write command pulse as shown in FIG.
The sequential supply of clock signals and control signals to the memories M1 to M4 is controlled, and the write areas for each of the memories M, to M4 are switched as shown in FIGS. By sequentially reading out the video signals written for each full screen, a plurality of unit video signals written in each of the plurality of memory areas a to d of the memories M1 to M4 are read out in chronological order. The printing means prints as shown in FIG.

By generating this, continuous writing to the memory becomes easy. If you do this, the motion of the subject will be
This is suitable when the speed is fast.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a video printer that can quickly and inexpensively obtain decomposed images of relatively fast-moving objects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a video printer according to the present invention, FIG. 2 is an explanatory diagram of a memory storage area 25', FIGS. 3 and 4 are explanatory diagrams of a printed image, and FIG. Figure 5 is a block diagram of the memory, Figure 6 is a block diagram of the write control section, Figure 7 is a circuit diagram of the allocation control circuit, and Figures 8, 9, 10, and 11 are time diagrams. It is a chart. (24), M+ to M4 are memories, a to d are memory areas, (50) is a memory cell array, (51) is a line buffer, (2nd) is a memory control circuit, (32) is a recording paper, P, ~P4 is the screen, A-D is the screen part, (75)
is an allocation control circuit.

Claims (1)

[Scope of Claims] Means for writing a plurality of time-series unit video signals into a plurality of memory areas of a memory in a predetermined order, a means for writing a plurality of unit video signals written into the plurality of memory areas of the memory,
A printer for printing a plurality of images corresponding to the plurality of unit video signals read out by the reading means in a predetermined arrangement state along the time series on a recording medium; A video printer characterized in that it has means.