JPS62288889A - Memory controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a RAM memory control device for storing video signals.

[Summary of the invention]

The present invention is a memory control device for a serial-in/serial-out type RAM having a built-in row (or column) address counter. ) An address clock signal, a row (or column) address reset signal obtained by dividing the vertical synchronization signal of the digital video signal to be written into 1/N,
Digital video signal sampling clock signal l/N
The column (or jte) address signal and the write control signal for selecting writing to N2 memory areas by dividing the RAM into l/N in the horizontal and vertical directions, respectively. By configuring it so that it occurs, the line (also:
Built-in address counter (zero serial in/no real out)
/N4 It is possible to easily write video signals by selecting N2 memory areas obtained by dividing into two.

[Conventional technology]

Recently, a serial-in/serial-out type Guinaminoku R has been developed as a video RAM that has a built-in address counter and can control writing and reading simply by supplying an address clock signal and an address reset signal.
AM is on the market. This has the advantage that the number of external parts is small, the space factor is good because no address bus is required, and refresh operations can be performed asynchronously.

[Problem that the invention seeks to solve]

Since addresses cannot be specified arbitrarily in such RAM, it is not possible to select N2 memory areas obtained by dividing the RAM horizontally and vertically into 1/N and store video signals therein. Ta.

In view of this, the present invention provides a serial-in/serial-out type RAM with a built-in row (or column) address counter.
The present invention attempts to propose a memory control device that can easily write video signals by selecting N2 memory areas obtained by dividing 1/N in the horizontal and vertical directions.

[Means for solving problems]

The present invention is a memory control device for a serial-in/serial-out type RAM (50) that incorporates a row (or column) address counter (56), in which a horizontal synchronization signal of a digital video signal to be written is divided into 1/N. Means (86) for generating a row (or column) address clock signal; and means (85) for generating a row (or column) address reset signal by dividing the vertical synchronization signal of the digital video signal to be written into 1/N. ), a means (82) for generating a column (or row) address signal by dividing the sampling clock signal of the digital video signal by 1/N, and a means (82) for generating a column (or row) address signal by dividing the frequency of the sampling clock signal of the digital video signal by 1/N in the horizontal and vertical directions. It is characterized by having means (73, 74, 75, 76, 84) for generating a write control signal for selecting writing to N2 memory areas obtained by dividing.

[Effect]

According to the present invention, it is possible to select N2 memory areas obtained by dividing the RAM (50) horizontally and vertically into 1/N, and easily write digital video signals therein.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. First, with reference to FIG. 1, the overall configuration of a video printer to which the present invention is applied will be described.

(21) is a TV camera, which receives a composite video signal (
composite color video signal or composite monochrome video signal) (
Composite video signals from a VTR, etc. are also possible) is connected to a video amplifier (22
) is supplied to the A/D converter (23), and only the video signal portion thereof is converted into, for example, a 4-bit (16 gradation) digital video signal. This digital video signal is supplied to the memory (24) and written therein.

This memory (24) has, for example, 41 bits of field memory (Guinamisoku RAM) M1 to M
It consists of 4. Writing to these memories M1 to M→ is controlled by a write control section (28a) of the memory control circuit (28), and refreshing thereof is controlled by a refresh control section (28b) thereof. The composite video signal from the amplifier (22) is supplied to a synchronization separation circuit (31), which separates vertical and horizontal synchronization signals, which are then supplied to the memory control circuit (28).

The video signals read from the memories M1 to N1→ are supplied to the output switching circuit (25) for switching and selection, and then supplied to the data converter (26) to generate pulses corresponding to the digital level of the video signal. The pulse width modulated line video signal is then supplied to the thermal head (27). This thermal head (27) is composed of, for example, 640 heating resistive elements arranged in one row.

Then, a roll of thermal recording paper (32) (FIG. 3) is moved in a direction perpendicular to the arrangement direction of the heat generating resistive elements of the head (27) and facing the heat generating resistive elements.

The output switching circuit (25) is the memory control circuit (28)
Switching control is performed by the output control section (28c) of. The data converter (26) and head (27) are also controlled by a print control circuit (29). Furthermore, the memory control circuit (28) is controlled by the print control circuit (29). The memory control circuit (28) also includes a read control section, but its illustration is omitted here. (30) is a commander that remotely writes data into memory (24).

Next, the memories M1 to M4 will be explained with reference to FIG. These memories M1 to M4 include memory areas aw and d divided into four equal parts.

Here, the horizontal direction of the video signal (television signal) is a direction perpendicular to the longitudinal direction of the roll of recording paper (32) shown in FIG. 3, and the vertical direction is the direction of the roll of recording paper (32).
The image is printed to match the longitudinal direction of the image.

The video signal is thinned out by half, for example, in the horizontal and vertical directions and written into each of the memory areas a to d of the memories M1 to M4, respectively.

In this case, the camera (21) is used after being rotated 90 degrees within the imaging plane from the normal use state. Therefore, for example, when a unit image based on a video signal written in memory M is printed on recording paper (32), the original screen P1 is divided into four equal parts, as shown in FIG. Images (2), (10), (1), (9
) is formed.

As shown in FIG. 2, each unit video signal (
Field signals) (1) to (16) are written. That is, the unit video signals (2), (10), (1), and (9) are corrupted into memory areas a to d of the memory M. Unit video signals (4), (12), (3), and (11) are written in memory areas a to d of the memory M2.

Memory areas a to d of memory M3 contain unit video signals (
6), (14), (5), and (13) are written. Unit video signals (8), (16), (7), and (15) are stored in the memory area a%d of the memory M4.

By doing this, by reading out each of the four unit video signals stored in the memories M, to M4 as one video signal, the recording paper (32) is read out as one video signal, as shown in FIG.
On the top, each screen part C, A of the screen P, -P4 and each screen part of the screen P1 to P→, and in H, field images (1) to (16) arranged in two lines in chronological order are shown. ) will be printed.

Note that the horizontal direction of the television screen may be made to match the longitudinal direction of the recording paper (32), and the vertical direction may be made to match the direction perpendicular to the longitudinal direction of the recording paper (32).
In that case, by changing the allocation to each of the four memory areas b5 a to b5 of memory M+-M→ of unit video No. 45, the arrangement of print images on the recording paper (32) can be changed to the third
It can be done similarly to the figure.

Next, an example of the memory (24) will be explained. The memory (24) used in this video printer is a serial-in/serial-out type RAM, a specific example of which is shown in FIG. 5 and will be briefly described. This figure 5 shows the μPD412 manufactured by NEC Corporation.
The configuration of the 21C dynamic RAM is shown below.
This will be explained.

(50) is a memory cell array of 320 rows and 700 columns (224 bits). (51) is a 700-pin line buffer, and this and memory cell array (50)
700 transfer gates (52) are interposed between the two. This line buffer (51) is controlled by a timing generation circuit (55). This timing generation circuit (55) includes a data transfer/restore i
ji control lock signal and refresh control clock signal are supplied to this data transfer gate (52).
is controlled by a read/write timing generation circuit (57). Read/write timing generation circuit (5
7) is supplied with a read/write control signal W.

(59) is a data input/output cover sofa, to which input data Din is supplied, and from which output data Dou is supplied.
t is output. There are 700 gates (54) between the data input/output cover sofa (59) and line buffer (51).
) is interposed. (53) is this gate (
54). This serial selector (53) is connected to the timing generation circuit (53).
5) and serial control timing generation circuit (5)
8).

A serial control clock signal = is supplied to the serial control timing generation circuit (inside the counter a) (58).

(60) is -, refresh address counter, (56
) is a row address counter, and each parallel output of both is an address selector (61), an address person cover sofa (62)
and an address decoder (63) in order, and are supplied to the memory cell array (50). The row address counter (56) receives a row counter reset clock signal,
A row counter increment clock signal po and a row counter decrement clock signal r are provided. Row address counter (56), refresh address counter (
60), an address selector (61), an address cover sofa (62) and an address decoder (63) are controlled by a timing generation circuit (55). Lead/
The write timing generation circuit (57) is controlled by the timing generation circuit (55), the serial control timing generation circuit (58) is controlled by the read/write timing generation circuit (57), and the data input/output cover sofa (59) is controlled by the serial control timing generation circuit (58). It is controlled by a control timing generation circuit (58).

Next, the operation of this dynamic RAM will be explained in relation to each of the above-mentioned signals.

The clock signal is used to transfer one row of data to the memory cell array (5
0) and the line buffer (51) (data transfer/restore cycle)
.

Control signal W The control signal W controls data transfer/data restore cycles and serial read/write cycles. In a data transfer/data restore cycle, this control signal Vfl is applied at the falling edge of the clock signal.
In the case of a serial read/write cycle, each operation is determined by the falling edge of the clock signal π.

clock signal π The clock signal is in-buffered (51) controls serial read/write operations.

By inputting the clock signal "clock signal =" while the clock signal "-" is inactive, on-chip refresh is executed by the built-in refresh control circuit.

The clock signal BLACK controls its row address by supplying the clock signal BLACK, ``, and the clock signal BLACK, ``, and BLACK'' to the row address counter (56). The row address is decremented (-1), and the clock signal C is used to reset the row address counter.

Then, each memory M of the memory (24) in FIG.
, ~M4, four such dynamic RAMs shown in FIG. 5 are used.

Next, each memory M1 to M of the above-mentioned memory (24)→
The configuration of the memory control section (28a) of the memory control circuit (28) of FIG. 1 when the dynamic RAM of FIG. 5 is used will now be described with reference to FIG. 6. The above-mentioned clock signal π is supplied to the input terminal (70). The input terminal (71) has a synchronization signal [synchronization separation circuit (
31) are supplied. A write command pulse from the commander (30) is supplied to the input terminal (72).

The clock signal π is supplied to the frequency divider circuit (73), synchronized with the synchronization signal, frequency-divided, and the divided output is supplied to the control pulse generation circuit (74), from which the clock signal purchase described above is performed. , a control signal Vff, a clock signal HIGH, and a clock signal HIGH are output.

Further, (75) is an allocation control circuit to which a synchronization signal is supplied. Furthermore, the write command pulse is supplied to the frequency dividing circuit (76) to divide the frequency into 1/2.1/4.1/8, respectively.
The frequency is divided into 1, and each frequency-divided output is supplied to the allocation control circuit (75). Control signals to each section are output from this allocation control word circuit (75).

Changeover switches (87) to (91) each have fixed contacts a, b and a movable contact C, and are switched in conjunction with each other by the output from the allocation control signal (75). When printing one image on one screen of the recording paper (32), the movable contacts C of the changeover switches (87) to (91) are placed on the fixed contact a side, and the movable contacts C of the changeover switches (87) to (91) When printing four images on the screen, the movable contacts C of the changeover switches (87) to (91) are respectively switched to the fixed contact side. The clock signal from the input terminal (70) and the clock signal from the control pulse generation circuit (74) are changed over by switches for W, C, and B (8th).
The signal supplied to each fixed contact a of (9■) and divided in half by its 1/2 frequency divider (82) and 1/2 decimation gates (83) to (86) is sent to the changeover switch ( 87
) to (91). Each clock signal from the movable contact C of the changeover switches (87) to (91) is switched by a changeover switch 7 (92) and supplied to each memory M1 to M→. And the frequency divider (
82), game 1-(83) to (86), and changeover switches (87) to (91) and (92) are controlled by the allocation control circuit (75).

Next, the specific configuration of the allocation control circuit (75) in FIG. 6 will be described with reference to FIG. 7. Figure 9 E~
N shows the waveforms of the signals at each part in FIG. A frame synchronization signal VF (FIG. 9F) is supplied to a NOR game (108), and this frame synchronization signal VF is also supplied to another NOR game (109) through an inverter (110). A vertical synchronizing signal (Fig. 9E) is supplied to NOR gates (108) and (109). These NO
From the R gates (108) and (109), the phase is 1 to each other.
80 degrees different, and the frequency is the vertical synchronization signal V D (7) Frequency (7) 1/2 (R No. (1/2) V
D+, (1/2) Trr5t (Fig. 9 G,
H) l) I* Rah 6° write command pulse (9th
(2) in the figure is supplied to the D-type flip-flop circuit (101) as a clock signal. "1" is supplied to the D input terminal of this flip-flow knob circuit (101). The inverted output of the flip-flop circuit (101) is supplied to the NOR gate (106) and the D input terminal of another flip-flop circuit (103). Flip-flop circuit (10
3) has an NOR gate (109
A signal from the input terminal (1/2 input V D 2 is supplied. Also,
This signal (1/2) is supplied to the NOR gate (106) through the impark (107). The non-inverted output of the flip-flop circuit (103) becomes the read/write mode signal R/VV (FIG. 9J).

Inverted output of flip-flop circuit (l O3) and NO
The output of R gate (108) is NAND gate (112)
supplied to The output of the N A N D gate (112) resets the flip-flop circuit (101).
the clock input terminal of the child and other flip-flop circuits (105). The output of the NOR gate (109) is supplied to the reset input terminal of the flip-flop circuit (105) through the inverter (113).

The output of the NOR gate <106) is supplied to the clock input terminal of the flip-flop circuit (104), and the reset signal [S is supplied to the reset input terminal of the flip-flop circuit (104), and its inverted output is supplied to the D input V)'1 child. will be done.And,
The inverted output of the flip-flop circuit (104) and the output of the inverter (110) are supplied to an EX-OR gate (114). The output of this EX-OR gate (114) and the vertical synchronization signal VD are supplied to a NOR gate (115).

The output of this NOR game 1- (115) is the gate (85)
is supplied as a gate signal to

A horizontal synchronization signal port is fed to the clock input terminal of the flip-flop circuit (lO2), a reset signal port is fed to its reset input terminal, and its inverted output is fed to the D input terminal. And, Furi, Pfrosop circuit (102
) is supplied to the gate (83) as gate signals.

The inverted output of the flip-flop circuit (105) and the inverted output of the flip-flop circuit (lO2) are supplied to the NAND gate (116), and its output is connected to the gate 1-(84).
is supplied as a WT gate signal.

The inverted output of the free-knob flop circuit (105) is supplied to a clock input terminal of a frequency divider (4-bit counter) (117), and a reset signal port is supplied to its clear signal input terminal. The 4-bit parallel output of the frequency divider (117) is supplied as a switching signal to a changeover switch (92) and also to a memory switching display device (not shown).

The non-inverting output of the flip-flop circuit (102) and the 22-digit l-bit output of the frequency divider (117) are EX-ORed.
is supplied to the gate (111), and its output is supplied to the gate (86).
) is supplied as a gate signal.

Next, dividing writing of a video signal to the memory shown in FIG. 5 will be explained. Prior to that, in order to make the explanation easier to understand, writing of the entire video signal to the memory, partial writing, etc. will be explained. First, the 8th
Referring to Figures AF, a normal full write to memory will be described.

At the timing (T), the control signal W (Fig. 8B) changes to "
1", data is transferred from the memory cell array (50) to the line buffer (51) at the falling edge of the clock signal I (FIG. 8A), and the clock signal I is set to 1.
By supplying the circular address counter (56),
Advance the address by one line. By supplying 640 clock signals π to the serial control timing generation circuit (58) in a video section of one horizontal period, 640 pixel signals of the input data Din are sequentially written into the line buffer (51).

Thereafter, when the control signal W (FIG. 8B) is "0", the fall of the clock signal T causes the line buffer (51) to be moved from the memory cell array (5) at the timing (R).
Transfer one line of video signal to 0). By repeating this 240 circuits per field, 640X2
Field data consisting of 40f pixel data is written into the memory cell array (50). Thereafter, the clock signal is supplied to the row address counter (56), and this counter (56) is set. Memory refresh is performed by supplying a clock signal to the timing generation circuit (55) while data is being transferred to the line buffer (51) asynchronously with such writing.

Next, the operation for writing a video signal into the left half of the memory cell array (50) will be described with reference to FIGS. 8G-J. In this case, the clock signals (Fig. 8 G), the control signal Vfl (Fig. 8 H), the clock signal T (Fig. 8 ■), and the clock signal rw, (Fig. 8 J) C, respectively Fig. 8 Compared to the A, B, and C3D signals, their frequencies are all 1.
/2. Only 320 clock signals π are supplied to the serial control timing generation circuit (58) during the video period of line (2). Therefore, 1547
In a time period of 1 minute, every other 320 pixel signals are written to the memory cell array (50).

Then, as shown in FIG. 8H, 1 to 32 in one line.
When the 0th clock signal π is generated, the control signal W1
is set to "0" and set to "L" when the 321st to 640th clock signal π is generated, one line of video signal is written to the left half of the memory cell array (50), and the following two The line row data becomes a dummy cycle that advances by the address, and the memory cell array (50)
is never written to. Thus, 1.3.5,
The ...th odd line video signal is written into the left half of the memory cell array (50).

The operation when writing a video signal to the right half of the memory cell array (50) can be easily understood by -N in FIG. 8, which corresponds to G-J in FIG. As shown in the figure, the polarity of the control signal Vfl is changed to
You should do the opposite.

Next, with reference to FIGS. 9A to 9D, a case will be described in which a video signal is written into the upper half or lower half of the memory. 9th
Figure A shows the vertical synchronization signal VD.

After the row address counter (56) is reset by the clock signal (FIG. 9D), a clock signal (FIG. 9C) is sent to the row address counter (56) every other line.
120 lines of video signals are written into the memory cell array (50) during each vertical cycle period. The clock signal P is 24 times within 2 vertical periods.
0 is supplied to the row address counter (56), the control signal W is set to rlJ in the first half, and when the line address advances from 121 to 240, the control signal W is set to rOJ, and the lower half of the memory is The video signal is written to. A clock signal is provided to the row address counter (56) every vertical period.

Next, with reference to FIG. 9 E=N, the operation of writing the video signal into each of the four divided memory areas aw and d of the memories M1 to M4 in FIG. 1 (FIG. 2), which is related to FIG. explain. When a write command pulse is generated from the commander (30) as shown in FIG. 9I, a control signal W completion (FIG. 9K) is generated after a predetermined time. By moving the clock signal supplied to the row address counter (56) for each memory M, to M4, the storage area of the memory is switched between the upper half and the lower half. It is fixed so that the control signal W is generated in the second field after the write command pulse is generated. On the other hand, the frame synchronization signal VF (FIG. 9F) is inverted every time a write command pulse occurs, and the inverted frame synchronization signal (
Figure 9L) and the vertical synchronization signal are connected to the NOR gate (109).
(Fig. 7), and when A N D is taken, the clock signal 1 is generated in synchronization with the vertical synchronization signal (2) before the first field, and the vertical synchronization signal (2) immediately before the second field is generated. The occurrence of the clock signal and the occurrence of the clock signal synchronously occur alternately. Since the control signal W can be generated in the second field, in the former case, the time of the first field becomes a dummy cycle, and the video signal is written in the lower half of the memory, and in the latter case, the clock signal [ A control signal W is generated immediately after π■, and a video signal is written into the upper half of the memory.

In this way, even if a write request comes for every other field,
Video signals can be written with a predetermined correct allocation.

In the allocation control circuit of FIG. 7, as shown in FIG. 1O, in response to the write command pulse of FIG. 10A, every four cycles of the write command pulse as shown in FIG.
The sequential supply of clock signals and control signals to the memories M1 to M4 is controlled, and the write area for each of the memories M and -M4 is switched as shown in FIGS. 10B and 10C. By sequentially reading out the video signals written for each entire screen from The image is then printed by the printing means as shown in FIG.

Incidentally, when a write request is received for every field, continuous writing to the memory is facilitated by continuously generating the control signal W100 as shown in FIG.

This method is suitable when the subject moves fairly quickly.

In the above-mentioned embodiment, a case has been described in which a RAM containing a row address counter and a column address counter is controlled, but it is also possible to control a RAM containing a column address counter.

〔Effect of the invention〕

According to the present invention described above, a serial-in/serial-out type RAM having a built-in address counter (row or column)
It is possible to obtain a memory control device that can easily write a video signal by selecting N2 memory areas obtained by dividing 1/N in the horizontal and vertical directions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a video printer to which the present invention is applied, FIG. 2 is an explanatory diagram of memory notes and area a, and FIGS. 3 and 4 are explanatory diagrams of printed images, respectively. , FIG. 5 is a block diagram of an example of a memory controlled by the present invention, FIG. 6 is a block diagram of a write control section of an embodiment of the present invention, FIG. 7 is a circuit diagram of an allocation control circuit, and FIG. 9, 10, and 11 are time charts, respectively. (24), Ml~! lc4 is memory, a - d
is a memory area, (50) is a memory cell array, (51)
is a line buffer, (28) is a memory control circuit, (28)
a) is a write control section, (75) is an allocation control circuit, (82) is a 1/2 frequency divider, and (83) to (86) are 1/2 thinning gates.

Claims (1)

[Claims] In a memory control device for a serial-in/serial-out type RAM having a built-in row (or column) address counter, a horizontal synchronization signal of a digital video signal to be written is set to 1/N.
a means for generating a row (or column) address clock signal by dividing the frequency into 1;
/N to generate a row (or column) address reset signal;
/N to generate a column (or row) address signal, and write to N^2 memory areas obtained by dividing the RAM into 1/N horizontally and vertically. A memory control device comprising means for generating a write control signal.