JPS6284672A - Video printer - Google Patents

Abstract

PURPOSE:To minimize the number of line memories and to obtain a high quality print by data processing by equalizing all action timing such as the timing for transferring information stored in a frame memory and the print timing to a vertical synchronizing signal. CONSTITUTION:When a freeze command is outputted from a system controller 6, a synchronizing signal changeover switch 15 is switched to a side (a), and digitized information is written at an address in the frame memory 21 designated by a memory controller 22. Upon the completion of writing, the freeze command is released and the operation becomes readable. The synchronizing signal changeover switch 15 is switched to a side (b), data in the frame memory 21 is read out in real time according to HD and VD outputted by a synchronizing signal generation means 14. When a printing command is issued from the system controller 6, the data outputted from the frame memory 21 is sequentially stored in a line memory part 3, converted into a head drive pulse by a signal conversion means 4, and supplied to a printing means 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a note copying device for video signals, etc., and relates to a video printer suitable for data transmission and data processing.

[Background of the invention]

Conventionally, as a method of printing video images using a line head, a method of printing while intermittently moving the head relative to the screen, as described in Japanese Patent Laid-Open No. 58-126175, has been adopted. was. This method has the advantage that printing time can be minimized because printing is performed regardless of the read timing of the frame memory. However, no consideration was given to the timing of data transfer to the head or the high image quality processing in the case of pseudo frame images.

[Purpose of the invention]

An object of the present invention is to provide a video printer that can stably set data transfer timing and data processing timing, minimize the number of line memories, and obtain prints with good image quality through data processing. .

[Summary of the invention]

The present invention makes it possible to read and write one line of data using only one line memory by aligning all operation timings such as transfer timing and print timing of information stored in the frame memory with the vertical synchronization signal. possible.

Furthermore, take advantage of the gaps in the data transfer period.

Data processing operations for high image quality are also possible.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, 1 is a signal processing section, 2 is a frame memory section,
3 is a line memory section, 4 is a signal converting means, 5 is a printing means, 6 is a system controller, 7 is a digital/analog converting section (hereinafter abbreviated as D/A section), and 8 is a monitor. In addition, the signal processing section 1 is an analog/digital converter 1.
2 (hereinafter abbreviated as A/D converter), synchronous signal separation means 13
．． Synchronous signal generating means 14. It is composed of a synchronization signal changeover switch 15. Frame memo IJ m2 is frame memory 21. It is composed of a frame memory controller 22.

Next, the operation will be explained.

When the freeze command is output from the system controller 6, the synchronization signal changeover switch 15 is switched to the fal side. The video signal input to the signal input terminal ll is A/D'
is sequentially converted into digital information by the converter 12 and output to the frame memory section 2. In this embodiment, the sampling clock is set to approximately 10.8 MHz (93 ns period). Synchronous signal separation means 1 from input video signal
By 3.

The vertical synchronization signal VD and horizontal synchronization signal HD are extracted and supplied to the frame memory controller 22.

The digitized information is written to the address of the frame memory 21 specified by the frame memory controller 22.

When the writing of data to the frame memory 21 is completed, the freeze command is canceled and the read state is entered. The synchronization signal changeover switch 15 is switched to the fbl side, and data in the frame memory 21 is read out in real time in accordance with HD and VD output by the synchronization signal generation means 14. Furthermore, the monitor 8 is connected via the secondary D/A converter 7.
The freeze command is played.

When a print command is issued from the system controller 6, the data output from the frame memory 21 in accordance with the printing order is stored in the line memory section 3 in order, and is converted into a head drive pulse by the signal conversion means 4, and then sent to the print means. 5.

Since one print screen is composed of video signals for one frame and two fields, the odd field signals are projected onto the monitor in the solid line area in Figure 2, and the even field signals are projected in the dashed line area in the same figure, and the print image is also displayed. printed in the same way. The line head in the printing means 5 is the third
As shown in the figure, there are heating elements for K512 dots in the vertical direction, each corresponding to a scanning line in FIG. The relationship between the monitor screen and the print screen is illustrated in FIG. 4. The data printed by the line head is data for one column in the vertical direction on the monitor screen. For this reason, the print image starts printing from the left end of the monitor screen in FIG. 4(a), moves sequentially to the right line, and finishes printing to the right end, completing the printing of one screen. In this embodiment, there are 512 lines.

Next, the operation of the line memory section 3 will be explained.

The configuration of the line memory section 3 is as shown in FIG.

In the figure, 31 is a line memory control; 32 is a line memory control;
3 is a line memory, 33 is a write latch, 34 is a read latch, 35 is a W latch pulse generation counter, 36 is a memory W/R control means, 37 is a print position counter, 38
is a frame synchronization detection unit, 301 and 302 are address switches, 3o3 is a write address counter, 304
is the read address counter. The data output from the frame memory is stored in one vertical line in a write latch (hereinafter abbreviated as W latch) 33.
The data is stored in the line memory 32 via. The data stored in the line memory 32 is transferred to the print signal converting means 4
Reading of data is started by a 1-gradation data transfer start command outputted from the print signal converting means 4 via a read latch (hereinafter abbreviated as R latch) 34.

Here, the main operations of the line memory 32 are shown in FIG.

This will be explained using FIGS. 6 and 7. As shown in FIG. 5, the line memory 32 has two areas, a memory area A and a memory area B, which can store 1947 minutes of print data, and each has a write area and a read area.

In other words, it is assumed that print data for line Hmn is currently stored in memory area B. At this time, the printer prints the 11th line based on the print data read from memory area B. At this time, the memory area person is storing the data of the next line to be printed, that is, the data of the n+1th line, in one row. When the printing of the nth line and the writing of the data of the n+1th line are completed, n+ is transferred from memory area A.
The data of the 1st line is read.

The n+1th line is printed. At this time, memory area B contains the print data of the next line, that is, (
The data on line n+2) is written (.

Memory area A and memory area B alternate.

This means that Read and Write are repeated every 33m5. (See Fig. 6) Next, a detailed explanation of the operation will be given using Fig. 7.

When a print command signal issued from the system controller 6 is input to the print command input terminal 311, the data on the leftmost line of the screen to be printed first is selected from the information in the frame memory 21, and the W/latch 33 is activated. The data is stored in the line memory 32 via the data. By print command signal.

Print position counter 37 is reset to zero. Next, the frame synchronization detector 38 detects the first frame synchronization pulse from the HD and VD, and the print position counter 3
It is input to the CK end of 7 and counts as 1. This count number is 33m until the next frame synchronization pulse is output.
It is held for s.

When the HD pulse is input to the W-latch pulse generation counter 35, the output address value of the print position counter 37 is input as a preset value, and after the preset becomes HDfJ''-Low and the preset is canceled, the input sampling clock is decreased. Therefore, when the count reaches the preset value, a borrow signal, that is, W-
Ratuchinokurus occurs. Currently, the preset value is 1, so when one sampling clock is input after HD is released, the first W.Ratch node will be output. That is, data read out from the frame memory immediately after HD input is latched into the W latch 33. As shown in FIG. 2, the data read from the frame memory is odd field data in the first field and even field data in the next field.
The order of data written to 2 is as shown in FIG. In other words, writing is performed in field units (d in the same figure), and during reading, odd/even fields are read out alternately. (G in the same figure) While the data of the first line is being written into the line memory, no signal is output to the print signal converting means 4.

Writing of data for the first line is complete.

When the next frame synchronization pulse is detected, the print position counter maps by one to 2, and the preset value of the W/latch pulse generation counter 35 also changes to 2. Therefore, a W latch pulse synchronized with the second sampling clock after HD release is generated. 33m
5, the data of the second vertical line is retrieved and written into the line memory 32.

When the second frame synchronization pulse is detected, the first line print start command signal is output from the output terminal 317.
The signal is output to the signal converting means 4 and becomes a standby state. When the internal setting of the print mode is completed in the signal converting means 4, the first one-gradation data transfer start command signal (FIG. 9e) is outputted and inputted to the input terminal 318. When this command signal is input, 512 pieces of print data are output to the signal cost conversion means 4 together with a data transfer lock (FIG. 9f).

Now, assuming that the print represents halftone density with 64 gradations, this data transfer is 1 frame per 33 m5.
c Repeated 64 times. (See Figure 6) For example, if the data transfer lock is set to 3.58MHz, 1
The time required for one data transfer is approximately 150 μs. Here, the relationship between the print screen and the data number is shown.

If you stand up the print screen and divide it into 1 pixel each horizontally, the result will be as shown in Figure 10. In FIG. 10, I)p
+q represents the ninth data from the top of the qth print line.

Assume that data on the nth line is now being printed. In FIG. 1O, the data is Dp, n (1≦p≦512°p is an integer). Assume that this data is stored in memory area B as shown in FIG. At this time, the print position line counter 37 outputs n + 1 as a count value, and the W/launch pulse generation counter 35 outputs n + 1 as a count value.

Since it is set to the preset value n + 1, HDfJ!
- W launch pulse (first
Figure 1 b) is generated. As shown in FIG. 11, the time tl from the HD release to the generation of the W latch pulse is i293ns
n+ 1 ), and this value is constant during l frames 33m5. , W. When the vicinity of the latch pulse generation area is enlarged, it becomes as shown in FIG. 12. The W-latch pulse is output, and the contents of the W-latch data change. Second time W.
Only one latch pulse is issued during the horizontal period.

A W latch pulse is output, and the write operation to the line memory 32 is started to ensure that the desired data is correctly latched. The line memory 32 is used both for writing and reading data, so when a W latch pulse occurs, the data write command to the line memory is sent to the memory W in synchronization with the read timing of the blit data. /R is generated in the phrase control means 36. (Figure 11, 1st
3) Line memory Wr ite signal (13th
When figure d) occurs, the address switch 301:
'(02k-1 each (from bl side (at (til
It is switched to l. Address switch 301 is memory area A shown in FIG.

The memory area B is determined by selecting the LSB output of the address of the print position line counter 37 and the output with the opposite polarity. Address switch 302 is 512
The address of the data is determined, and the write address is determined on the (a) side, and the read address is determined on the tbt side. The address counter 303 is
Something that outputs r ite address.

The Raad address counter 304 outputs a Read address, and is controlled by the line memory control circuit 31.

The timing of inputting data to the line memory 32 will be explained with reference to FIG. It is now assumed that the first gradation data transfer start command signal (a in the figure) is input and data on the nth line is being transferred. The line memory Wr ite signal is output in accordance with the data transfer timing.
Normally, a data transfer lock pulse would appear at the position indicated by the broken line in Figure 13, 1bl, and the data would change in synchronization with this pulse, but because the line memory write signal was output, only one clock pulse was needed. This results in a delay in data transfer. The line memory write signal is output for only one period of data transfer lock pulse, and
The data latched in the latch is written to the line memory.

When the line memory Write signal is released, the address switches 301 and 302 in FIG. 7 are switched to the (b) side, and the print data read mode (FIG. 13 d) is entered.

Repeat the above steps from line 1 to line 512.

By repeating this process, one print screen is obtained.

When the printing of the 511th line is finished and the 512th line is to be printed, the print position line counter 37 outputs a count value of 513. The W-curse generation counter 35 outputs a W-latch pulse in an attempt to read the 513rd data after HD is released, but the 513rd data is not valid data for the print screen. However, this data is stored in the line memory
Even with riteL, the print operation has already finished, so it does not affect the print screen. When printing the 512th line, it may be possible to prevent the generation of W.U.Sochinokurus.

Next, a second embodiment of the line memory section 3 is shown in FIG. In the configuration of FIG. 14, parts having the same functions as those in FIG. 7 are assigned the same reference numerals. In the same figure, 320 is latch A, 321 is latch B, 32
2 is an adder, 323 is a multiplier, 324 is a data switch, 325 is a latch C, 326 is a VBLK detection section, 327
is an AND gate.

Next, the operation will be explained using FIG. 15. Now, the number of horizontal scanning lines is 525 in the l frame time of 33.3 ms.
Of these, only 512 were actually sampled and printed. Therefore, Wr of 6 line memory
525-Fi12 when focusing only on the IT function
= 13 lines, that is, there is a free time of 13H in one frame. To illustrate this, there is a vertical blanking period (hereinafter abbreviated as VBLK) as shown in FIG. 15(b).

The number tc is 6H between even-numbered and odd-numbered fields, and 7H between odd-numbered and even-numbered fields. Currently, printing of the l line is started from the odd field area. The maximum printing time for the l line is set to within 33m5 in total, taking into account the head rest time (Figure 15)), so during the 6H VBLK period between the even field and the odd field, the line Neither write nor read operations are performed on the memory 32. Until now.

The discussion has been based on the premise of printing frame images, but if a signal with movement on the screen, such as a moving image, is input to the video signal input terminal and stored in the frame memory, the monitor screen will, for example, be as shown in Figure 19. As shown, in moving parts, a composite image of solid lines and broken lines appears on the monitor screen.

When a moving image signal is input, one field of the video signal is frozen and stored in a frame memory as a field image. In this case, the frame memory may be a field memory. When the frozen signal is reproduced, data in odd and even fields are read out as the same data. In this case, the state of the monitor screen will be explained using FIG. 16 as an example. In FIG. 16, it is assumed that a boundary between black and white exists diagonally on the screen as shown by a broken line. At this time, in the field image, since the data in the odd and even fields are the same, the monitor screen and print screen appear as shown by solid lines.

As it is, it is visually very unsightly and the quality of the single image is not very good.

The line memory 32 in FIG. 17 stores vertical line data. As described above, there is a 6H VBLK period after writing data to the line memory and before data reading by printing begins. It is possible to improve the image quality by performing some data processing on the vertical data within this time. (Figure 15 (d), (e) time of diagonal #i! portion) Experimentally, the image quality of the print image was obtained by replacing the data of one field with the average value data of the other field data. It has been found to be a marked improvement over non-printed images and to be visually acceptable. An example of this method is shown below.

One embodiment of this is shown in FIG.

In this embodiment, a method is adopted in which the data of the even field is replaced with the average value data of the upper and lower data of the odd field. In other words, data D2 of the 2+16th even field on the screen. are the data of the upper and lower odd fields, that is, the (2n-1)th data Dzn-1 and (2n
+1)th data D2n+x is replaced with average value data. In other words.

D2n=first soil ±'to supervision (1≦n≦2550 is an integer) When n = 256, the above formula yields D513 + Dsu D512 = -, but data for D513 does not exist. In the circuit, the 512th data is not replaced and remains as D512.
We will collect the following data. The operation of one circuit will now be explained.

In FIG. 14, when the print command signal is input, the VD and HD are input first.

A VBLK period is detected in the VBLK detection section 326. After this, when the first frame synchronization signal is generated by the frame synchronization detection section 38, the print position line counter 37, which had been reset by the print command,
counts up by one and outputs l as the address. This value is the W/latch pulse generation counter 35.
is preset as a count number, and the data of the lth line is sequentially written to the line memory via the W latch.

When writing of data for the lth line is completed.

As mentioned above, the VBLK period is 6H. During this time, the data processing described above is performed. (Hereafter referred to as average value interpolation processing).

When entering the average value interpolation processing mode, the line memory control circuit 31 outputs a mode switching signal. As a result,
The W latch pulse generation counter 35 is reset,
During the VBLK period, the W latch pulse is set not to occur.

Further, the AND gate 327 is operated during the average value interpolation process.

It serves to prevent long data transfers from being output.

The line memo IJ W/R control unit 36 causes the line memory to alternately read/write during the average value interpolation process.
A control signal is generated to repeat te (Fig. 18 (
d).

reference).

When the average value interpolation mode is entered, Write completed address address counter 303 ead address counter 304 ,
R latch (34) latch A (320), latch B
(321) All latches C (325) are reset.

When the first CK is received, Read address counter 30
4 is.

Address 1 is output, and data D1 at address 1 is latched into the R latch 34. At this time Wr i
The te address counter 303 remains reset. Latch A (320) contains the data that was transferred to R-latch 34 before the first CK was input manually.
In other words, d latch B (3
21) is the data latched in latch A320.
O is latched. The value of SB of the read address counter 304 is latched in the latch C325, and the value 0 is latched at the odd numbered address, and the value l is latched at the even numbered address. Currently, the read address is 1, which is odd-numbered data, so 0 is latched into latch C (325).

An average value calculation is performed by an adder 322 and a 1/2 multiplier 323. R latch (34) and latch B (32
The average value data of the two output data of 1) is output to the tb+ terminal of the data switch (324).

The data switch 324 selects between the data of the latch A (320) input to the (a) terminal and the average value data input to the (bll terminal) according to the output of the latch C325. When the output of the latch C325 is O, (b) Input data of the terminal h!- is selected, and when it is 1, the input data of the (a) terminal is selected, and the output data is written to the address specified by the Write address counter 303 by the line memory Write signal.

Currently, the write address counter 303 remains reset, and the line memo! No JWrite signal is generated.

When the next clock power is input, the read address counter 304 outputs address 2, and the R latch 34 latches the second data D2. Below, latch A3
20 is the first data Dl, latch B521 is 0
, 1 data is latched in the latch C325. The tb) terminal of the data switch 324 has R.
It is latched B with the latch (34). Now latch C (32
In 5), since the l data is latched, the input data DI on the (a) side is selected and output. At this time,
Write address counter 303 is outputting address l.

A line memory Write signal is generated and the first data D+ is written to address l again.

When the next clock is input, Read address counter 3
04 outputs address 3, and the third data D3 is latched into the R latch 34. U・Nchi A320
contains the second data D2. The latch B521 contains the first data D1. Each latch C325K latches O data. wrile completed dress card dress counter 3
03 s 2 is output.

Data switch 324 indicates that latch C325 is 0%-Dl
-I-D3 is latched, so input data 2 on the +bl side is selected. When the line memo 'JWrite signal is generated, the data of DI+D3 is written to address "2".

This operation is repeated below. A summary of this operation is shown in FIGS. 17 and 18.

When the 512th clock is input, the read address counter 304 outputs address 512, and the 512th data D512 is latched into the R latch.

At this time, latch A contains data Dsn, latch B contains data D510, and latch C contains data 1.
It is being punched. The data switch 324 selects and outputs the input data D511 on the fal side, and writes the data to the memory.
When the signal is generated, data D511 is written to address 511.

The Read address counter stops counting when the address reaches 512. Therefore, even if the 513th clock is generated, the output value of the read address counter 304 remains unchanged. Write address counter 303 is address 51
Outputs 2. Data D512 is sent to the R latch again.
is latched. Data D512 is latched in latch A, data Dso is latched in latch B, and data l is latched in latch C. In the data switch 324 (a)
Select side input data D5】2 and output, line memo 1
When the JWrite signal is generated, data D512 is written to address 512.

By repeating the above operations, the average value interpolation operation is completed.

Once the average value interpolation operation is complete, the data is read and printed. What happens next?

The operation is the same as that in the configuration shown in FIG. As shown in FIGS. 15(d) and 15(e), the line memory 32 having two memories alternately repeats the cycle of Write→average value interpolation→Read and print.

〔Effect of the invention〕

According to the present invention, by aligning all print control signals such as data transfer timing and print timing with the synchronization signal, data writing to and reading from the line memory during printing can be performed using the same memory. It is possible to minimize memory cost. Furthermore, data average value interpolation processing that utilizes the free time after the line memory writing operation is completed makes it possible to improve the image quality by 5, making it possible to obtain good print images.

[Brief explanation of drawings]

FIG. 1 is a program diagram showing one embodiment of the present invention. FIG. 6 is a schematic diagram for explaining the operation of FIG. 1. 7M is a block diagram showing an embodiment of the line memory section in FIG. 1; Figure 5, Figure 6, Figure 8, Figure 9, Figure 1O
11, 121, and 13 are schematic diagrams for explaining the operation of FIG. 7. FIG. 14 is a block diagram showing another embodiment of the line memory section in FIG. 1. 15, 16, 17, 18, and 19 are schematic diagrams for explaining the operation of FIG. 14. DESCRIPTION OF SYMBOLS 1...Signal processing unit, 2...Frame memory unit 3...Line memory unit, 4...Signal conversion means. 5...Printing means, 12...A/D conversion means. 32...Line memory, 33.34...Latch. 37...Print position line counter. 301, 302...Address changeover switch. 303, 304...Address counter. 320, 321, 323, 325...Latch. 322...Adder, 323...1/2 multiplier. 324...Data selection circuit. 326...VBLK detection section.

Claims (1)

[Claims] 1. Analog/digital conversion means that receives a video signal as input, a frame memory that stores the output of the conversion means, a line memory that stores the output of the frame memory, and an output of the line memory. A printer comprising a signal converting means for converting a signal into a signal according to a gradation based on the signal, and a printing means for realizing printing based on the output of the signal converting means, the data output from the frame memory to the line memory. A video device characterized in that it has a write control means for storing data in the line memory, a read control means for reading data from the line memory, and a control means for operating the write control means during a series of operations of the read control means. printer.