JP2510466Y2 - High-density mounting structure - Google Patents
High-density mounting structureInfo
- Publication number
- JP2510466Y2 JP2510466Y2 JP1990061585U JP6158590U JP2510466Y2 JP 2510466 Y2 JP2510466 Y2 JP 2510466Y2 JP 1990061585 U JP1990061585 U JP 1990061585U JP 6158590 U JP6158590 U JP 6158590U JP 2510466 Y2 JP2510466 Y2 JP 2510466Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip component
- soldered
- electrode
- pattern
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【考案の詳細な説明】 〔概要〕 面実装部品を高密度に実装する高密度実装構造に関
し、 面実装部品の実装密度を向上させると共に、部品間の
パターンを一部省略できるようにすることを目的とし、 基板のパターンにチップ部品の裏面電極を半田付け
し、該チップ部品の表面電極に面実装ICのリードを直接
半田付けするようにしてなる高密度実装構造において、
該チップ部品の表面電極の内、面実装ICのリードと半田
付けされる電極の長さを他方の電極の長さより長くする
よう構成する。[Detailed Description of the Invention] [Outline] Regarding a high-density mounting structure for mounting surface-mount components in high density, it is possible to improve the mounting density of the surface-mount components and to partially omit the pattern between the components. For the purpose, in the high-density mounting structure in which the back surface electrode of the chip component is soldered to the pattern of the substrate and the leads of the surface mounting IC are directly soldered to the front surface electrode of the chip component,
Of the surface electrodes of the chip component, the length of the electrode soldered to the lead of the surface mounting IC is longer than the length of the other electrode.
本考案は、面実装部品を高密度に実装する高密度実装
構造に関する。The present invention relates to a high-density mounting structure for mounting surface-mount components at high density.
現在の車両用制御器は高機能化、高性能化が進められ
る一方で、性能向上のためセンサ、アクチュエータ、コ
ンピュータ等を一体化し、さらにはこれらを小型化して
エンジンルームへ収容する傾向にある。ところが、エン
ジンルームは点火装置等のノイズが多く発生するため、
充分にノイズ対策を施す必要がある。While the current vehicle controllers are becoming more sophisticated and have higher performance, there is a tendency to integrate sensors, actuators, computers, etc. for performance improvement, and further miniaturize them to accommodate them in the engine room. However, in the engine room, a lot of noise from the ignition device etc. occurs,
It is necessary to take sufficient noise countermeasures.
第４図は車両用制御器の部分構成図で、１は信号処理
回路を集積化した面実装IC、２は各種センサ信号をIC1
に入力するコネクタ、３はIC・コネクタ間に介在したノ
イズリダクション（NR）回路である。このNR回路３はコ
ンデンサＣと抵抗Ｒを組として構成され、これをIC1の
リード11に対応して複数組設けてある。FIG. 4 is a partial configuration diagram of a vehicle controller. Reference numeral 1 is a surface mount IC in which a signal processing circuit is integrated, and 2 is various sensor signals IC1.
Connector 3 for input to is a noise reduction (NR) circuit interposed between the IC and connector. The NR circuit 3 is composed of a capacitor C and a resistor R as a set, and a plurality of sets are provided corresponding to the lead 11 of the IC1.
NR回路３を面実装タイプにする場合、Ｒはチップ抵
抗、Ｃはチップ磁気コンデンサとなる。この抵抗Ｒの一
端は基板上のパターン31を使用してIC1のリード11に接
続され、また他端はパターン32を使用してコネクタ２の
端子21に接続される。同様にコンデンサＣは入力パター
ン31とアースパターン33の間に接続される。When the NR circuit 3 is a surface mount type, R is a chip resistor and C is a chip magnetic capacitor. One end of this resistor R is connected to the lead 11 of the IC1 using the pattern 31 on the substrate, and the other end is connected to the terminal 21 of the connector 2 using the pattern 32. Similarly, the capacitor C is connected between the input pattern 31 and the ground pattern 33.
NR回路３はコネクタ２の端子21と出力パターン32にと
び込むノイズを軽減できる。しかし、入力パターン31に
混入するノイズの軽減効果は少ないので、この部分は極
力短かい方が良い。The NR circuit 3 can reduce noise that jumps into the terminal 21 of the connector 2 and the output pattern 32. However, since the effect of reducing the noise mixed in the input pattern 31 is small, it is preferable that this portion is as short as possible.
本考案は、この入力パターン31を不要にすることで、
ノイズ軽減効果および実装密度を向上させようとするも
のである。The present invention eliminates the need for this input pattern 31,
It is intended to improve the noise reduction effect and the mounting density.
第１図は本考案の原理図で、１は面実装IC、４は抵抗
ＲやコンデンサＣ等のチップ部品である。IC1は側壁か
ら平坦なリード11を複数本水平に突出させている。これ
に対しチップ部品４は両端に表面から裏面にかかる電極
を有する。説明の便宜上、41を裏面電極、42を側面電
極、43を表面電極と呼ぶが、これは１つの電極の各部で
ある。図面では両端の電極を符号A,Bで区別している。
チップ部品４の両端の表面電極のうち面実装ICのリード
と半田付けされる電極43Aの長さＬ1は、他方の電極43B
の長さＬ2より長い。FIG. 1 is a principle view of the present invention. Reference numeral 1 is a surface mount IC, and 4 is a chip component such as a resistor R and a capacitor C. In the IC1, a plurality of flat leads 11 are horizontally projected from the side wall. On the other hand, the chip component 4 has electrodes extending from the front surface to the back surface at both ends. For convenience of explanation, reference numeral 41 is called a back surface electrode, 42 is called a side surface electrode, and 43 is called a front surface electrode, which is each part of one electrode. In the drawing, the electrodes on both ends are distinguished by the symbols A and B.
Of the surface electrodes on both ends of the chip component 4, the length L 1 of the electrode 43A to be soldered to the lead of the surface mounting IC is the other electrode 43B.
Is longer than the length L 2 .
裏面電極41は基板上のパターンにチップ部品４を半田
付けする際に使用される。このとき側面電極42も盛り上
がった半田に接触して結合強度を高める。表面電極43
は、チップ部品４が例えば抵抗Ｒの場合、その表面の抵
抗体の両端に接続するために使用されるもので、基板側
パターンとの接続には不要である。The back surface electrode 41 is used when the chip component 4 is soldered to the pattern on the substrate. At this time, the side electrodes 42 also come into contact with the raised solder to enhance the bonding strength. Surface electrode 43
When the chip component 4 is, for example, a resistor R, it is used for connecting to both ends of the resistor on the surface thereof, and is not necessary for connection with the board-side pattern.
従って、従来のチップ部品では表面電極43は露出して
いる必要もないが、本考案ではこれをICリード11との間
に半田付けに利用する。この場合、ICリード11に半田付
けする表面電極43Aの長さＬ1を他方の表面電極43Bの長
さＬ2より長くしておくと（Ｌ1＞Ｌ2）、半田付け面積
が増してICリード11との結合強度が高くなる。Therefore, in the conventional chip component, the surface electrode 43 does not need to be exposed, but in the present invention, this is used for soldering with the IC lead 11. In this case, if the length L 1 of the surface electrode 43A to be soldered to the IC lead 11 is made longer than the length L 2 of the other surface electrode 43B (L 1 > L 2 ), the soldering area increases and the IC The bond strength with the lead 11 is increased.
IC1のリード11をチップ部品４の表面電極43Aに直接半
田付けすると、第４図の入力パターン31が不要になるの
で、その分実装密度が向上し、またノイズ軽減効果も改
善される。When the leads 11 of the IC1 are directly soldered to the surface electrodes 43A of the chip component 4, the input pattern 31 shown in FIG. 4 is unnecessary, so that the mounting density is improved and the noise reduction effect is also improved.
第２図は本考案の第１実施例の構成図である。面実装
IC1は複数のリード11a,11b,……を有し、一部のリード1
1aはフォーミングしてパターン35に接続するが、ノイズ
軽減を必要とするリード11bはそのままの形状でチップ
部品４の表面電極43Aに直接半田付けする。FIG. 2 is a block diagram of the first embodiment of the present invention. Surface mount
IC1 has a plurality of leads 11a, 11b, ...
1a is formed and connected to the pattern 35, but the lead 11b that requires noise reduction is directly soldered to the surface electrode 43A of the chip component 4 in the same shape.
このチップ部品４はパターン32とランド（またはパタ
ーン）34上に半田付けされるもので、その様子を（ｂ）
に示す。同図において５は、パターン32,34,35等を表面
に印刷した基板であり、各パターンの必要部品にはクリ
ーム半田６が塗布してある。この基板側の半田６上にチ
ップ部品４を搭載したら、更にその表面電極43A上にも
ディスペンサでクリーム半田６を塗布し、そこにICリー
ド11bを重ねて加熱する。この加熱工程で半田６は溶融
し、チップ部品４は基板５側に半田付けされると同時
に、リード11bとも半田付けされる。このとき基板側の
半田６はチップ部品４の側面に破線で示すように盛り上
がる。The chip component 4 is soldered on the pattern 32 and the land (or pattern) 34, and the state is shown in (b).
Shown in In the figure, reference numeral 5 denotes a substrate having patterns 32, 34, 35 and the like printed on its surface, and cream solder 6 is applied to necessary parts of each pattern. After the chip component 4 is mounted on the solder 6 on the substrate side, the cream solder 6 is further applied to the surface electrode 43A by a dispenser, and the IC lead 11b is overlaid thereon and heated. In this heating process, the solder 6 is melted, and the chip component 4 is soldered to the substrate 5 side, and at the same time, the lead 11b is also soldered. At this time, the solder 6 on the substrate side rises on the side surface of the chip component 4 as indicated by the broken line.
第３図は本考案の第２実施例の構成図である。本例で
はチップ部品４に半田付けするリード11bもフォーミン
グし、その先端をカットしてある。このようにすると、
チップ部品４を更にIC1に近づけることができるので、
ノイズ軽減効果や実装密度も更に改善される。FIG. 3 is a block diagram of a second embodiment of the present invention. In this example, the lead 11b to be soldered to the chip component 4 is also formed and its tip is cut. This way,
Since the chip component 4 can be brought closer to IC1,
The noise reduction effect and mounting density are further improved.
以上述べたように本考案によれば、ノイズリダクショ
ン回路を要する制御器等の基板実装密度を高め、またノ
イズ軽減効果を改善できる利点がある。またチップ部品
の、面実装ICのリードと半田付けされる表面電極の長さ
を、他方の表面電極の長さより長くしたので、半田付け
面積が増してICリードとの結合強度が高くなる。As described above, according to the present invention, there is an advantage that the board mounting density of a controller or the like that requires a noise reduction circuit can be increased and the noise reduction effect can be improved. Further, since the length of the surface electrode of the chip component to be soldered to the surface-mounted IC lead is longer than the length of the other surface electrode, the soldering area is increased and the bonding strength with the IC lead is increased.
第１図は本考案の原理図、 第２図は本考案の第１実施例の構成図、 第３図は本考案の第２実施例の構成図、 第４図は車両用制御器の部分構成図である。 図中、１は面実装IC、４はチップ部品、５は基板、６は
半田、11はリード、41は裏面電極、43は表面電極であ
る。FIG. 1 is a principle diagram of the present invention, FIG. 2 is a configuration diagram of a first embodiment of the present invention, FIG. 3 is a configuration diagram of a second embodiment of the present invention, and FIG. 4 is a portion of a vehicle controller. It is a block diagram. In the figure, 1 is a surface mount IC, 4 is a chip component, 5 is a substrate, 6 is solder, 11 is a lead, 41 is a back electrode, and 43 is a front electrode.
Claims (1)
部品（４）の裏面電極（41）を半田付けし、 該チップ部品の表面電極（43）に面実装IC（１）のリー
ド（11）を直接半田付けするようにしてなる高密度実装
構造において、 該チップ部品の表面電極の内、面実装ICのリードと半田
付けされる電極（43A）の長さ（Ｌ1）を他方の電極（43
B）の長さ（Ｌ2）より長くすることを特徴とする高密度
実装構造。1. A back surface electrode (41) of a chip component (4) is soldered to a pattern (32, 34) of a substrate (5), and a surface mounting IC (1) of a surface mounting electrode (43) of the chip component (4) is soldered. In the high-density mounting structure in which the leads (11) are directly soldered, the length (L 1 ) of the electrodes (43A) to be soldered to the leads of the surface mounting IC among the surface electrodes of the chip component is set. The other electrode (43
A high-density mounting structure characterized by being made longer than the length (L 2 ) of B).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990061585U JP2510466Y2 (en) | 1990-06-11 | 1990-06-11 | High-density mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990061585U JP2510466Y2 (en) | 1990-06-11 | 1990-06-11 | High-density mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0420261U JPH0420261U (en) | 1992-02-20 |
| JP2510466Y2 true JP2510466Y2 (en) | 1996-09-11 |
Family
ID=31589963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990061585U Expired - Fee Related JP2510466Y2 (en) | 1990-06-11 | 1990-06-11 | High-density mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2510466Y2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS646063U (en) * | 1987-06-30 | 1989-01-13 |
-
1990
- 1990-06-11 JP JP1990061585U patent/JP2510466Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0420261U (en) | 1992-02-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |