JP2508612Y2 - リ―ドフレ―ム - Google Patents
リ―ドフレ―ムInfo
- Publication number
- JP2508612Y2 JP2508612Y2 JP1989142186U JP14218689U JP2508612Y2 JP 2508612 Y2 JP2508612 Y2 JP 2508612Y2 JP 1989142186 U JP1989142186 U JP 1989142186U JP 14218689 U JP14218689 U JP 14218689U JP 2508612 Y2 JP2508612 Y2 JP 2508612Y2
- Authority
- JP
- Japan
- Prior art keywords
- mounting surface
- die pad
- back surface
- chip mounting
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000004080 punching Methods 0.000 claims description 8
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 230000000694 effects Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989142186U JP2508612Y2 (ja) | 1989-12-08 | 1989-12-08 | リ―ドフレ―ム |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989142186U JP2508612Y2 (ja) | 1989-12-08 | 1989-12-08 | リ―ドフレ―ム |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0381641U JPH0381641U (enrdf_load_html_response) | 1991-08-21 |
JP2508612Y2 true JP2508612Y2 (ja) | 1996-08-28 |
Family
ID=31689026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989142186U Expired - Fee Related JP2508612Y2 (ja) | 1989-12-08 | 1989-12-08 | リ―ドフレ―ム |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2508612Y2 (enrdf_load_html_response) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61135145A (ja) * | 1984-12-06 | 1986-06-23 | Fujitsu Ltd | リ−ドフレ−ム |
JPS63308358A (ja) * | 1987-06-10 | 1988-12-15 | Mitsui Haitetsuku:Kk | リ−ドフレ−ム |
-
1989
- 1989-12-08 JP JP1989142186U patent/JP2508612Y2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0381641U (enrdf_load_html_response) | 1991-08-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5723899A (en) | Semiconductor lead frame having connection bar and guide rings | |
WO1998052217A3 (en) | Method of forming a chip scale package, and a tool used in forming the chip scale package | |
KR960015827A (ko) | 반도체 장치 및 그 제조방법 | |
EP0989608A3 (en) | Plastic integrated circuit device package and method of making the same | |
KR970077540A (ko) | 칩 사이즈 패키지의 제조방법 | |
JP2001015668A (ja) | 樹脂封止型半導体パッケージ | |
JP2508612Y2 (ja) | リ―ドフレ―ム | |
JPH0783035B2 (ja) | 半導体装置 | |
EP1869699A1 (en) | Leadframe, coining tool, and method | |
JPH0545063B2 (enrdf_load_html_response) | ||
JP2002076234A (ja) | 樹脂封止型半導体装置 | |
JP4570797B2 (ja) | 半導体装置の製造方法 | |
JPH02105450A (ja) | 半導体装置 | |
JPH11260972A (ja) | 薄型半導体装置 | |
JPH0739237Y2 (ja) | 半導体装置 | |
JPH0621304A (ja) | リードフレーム及び半導体装置の製造方法 | |
JPH10200023A (ja) | 半導体装置 | |
JPH0294463A (ja) | 半導体装置 | |
KR0124547Y1 (ko) | 멀티형 리드프레임을 이용한 반도체 장치 | |
JPH06204389A (ja) | 半導体装置及びその製造方法 | |
KR100705249B1 (ko) | 반도체 패키지 제조용 리드프레임 | |
KR940000746B1 (ko) | 반도체장치의 칩 본딩방법 | |
JPH03116767A (ja) | Icのパッケージ | |
JPH043508Y2 (enrdf_load_html_response) | ||
KR100345163B1 (ko) | 볼 그리드 어레이 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |