JP2023544802A5 - - Google Patents
Info
- Publication number
- JP2023544802A5 JP2023544802A5 JP2023521315A JP2023521315A JP2023544802A5 JP 2023544802 A5 JP2023544802 A5 JP 2023544802A5 JP 2023521315 A JP2023521315 A JP 2023521315A JP 2023521315 A JP2023521315 A JP 2023521315A JP 2023544802 A5 JP2023544802 A5 JP 2023544802A5
- Authority
- JP
- Japan
- Prior art keywords
- command
- data
- nvr
- read
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024229142A JP2025041887A (ja) | 2020-10-07 | 2024-12-25 | ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202063088572P | 2020-10-07 | 2020-10-07 | |
| US63/088,572 | 2020-10-07 | ||
| US17/125,927 US11971832B2 (en) | 2020-10-07 | 2020-12-17 | Methods, devices and systems for high speed transactions with nonvolatile memory on a double data rate memory bus |
| US17/125,927 | 2020-12-17 | ||
| PCT/US2021/053916 WO2022076652A1 (en) | 2020-10-07 | 2021-10-07 | Systems for high speed transactions with nonvolatile memory on a double data rate memory bus |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024229142A Division JP2025041887A (ja) | 2020-10-07 | 2024-12-25 | ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2023544802A JP2023544802A (ja) | 2023-10-25 |
| JP2023544802A5 true JP2023544802A5 (https=) | 2024-05-23 |
| JP7612851B2 JP7612851B2 (ja) | 2025-01-14 |
Family
ID=80931357
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023521315A Active JP7612851B2 (ja) | 2020-10-07 | 2021-10-07 | ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム |
| JP2024229142A Pending JP2025041887A (ja) | 2020-10-07 | 2024-12-25 | ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024229142A Pending JP2025041887A (ja) | 2020-10-07 | 2024-12-25 | ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US11971832B2 (https=) |
| JP (2) | JP7612851B2 (https=) |
| CN (1) | CN116324737A (https=) |
| DE (1) | DE112021005295T5 (https=) |
| WO (1) | WO2022076652A1 (https=) |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5474313B2 (ja) | 2008-04-25 | 2014-04-16 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置及びその制御方法 |
| WO2011130007A1 (en) * | 2010-04-14 | 2011-10-20 | Rambus Inc. | Levelization of memory interface for communicating with multiple memory devices |
| US20140325105A1 (en) * | 2013-04-26 | 2014-10-30 | Advanced Micro Devices, Inc. | Memory system components for split channel architecture |
| US20160378366A1 (en) | 2015-06-24 | 2016-12-29 | Intel Corporation | Internal consecutive row access for long burst length |
| US10061645B2 (en) | 2015-06-30 | 2018-08-28 | Qualcomm Incorporated | Memory array and link error correction in a low power memory sub-system |
| US10534540B2 (en) * | 2016-06-06 | 2020-01-14 | Micron Technology, Inc. | Memory protocol |
| US10810144B2 (en) | 2016-06-08 | 2020-10-20 | Samsung Electronics Co., Ltd. | System and method for operating a DRR-compatible asynchronous memory module |
| US10621096B2 (en) * | 2016-09-08 | 2020-04-14 | Seagate Technology Llc | Read ahead management in a multi-stream workload |
| WO2018081746A1 (en) | 2016-10-31 | 2018-05-03 | Intel Corporation | Applying chip select for memory device identification and power management control |
| WO2018232736A1 (zh) | 2017-06-23 | 2018-12-27 | 华为技术有限公司 | 内存访问技术及计算机系统 |
| US10541042B2 (en) | 2018-04-23 | 2020-01-21 | Microsoft Technology Licensing, Llc | Level-crossing memory trace inspection queries |
| US10692560B2 (en) * | 2018-06-06 | 2020-06-23 | Intel Corporation | Periodic calibrations during memory device self refresh |
| TWI727449B (zh) | 2018-10-17 | 2021-05-11 | 旺宏電子股份有限公司 | 非循序頁面連續讀取 |
| US11249678B2 (en) * | 2019-07-26 | 2022-02-15 | Qualcomm Incorporated | Serial memory device single-bit or plurality-bit serial I/O mode selection |
| US11030128B2 (en) * | 2019-08-05 | 2021-06-08 | Cypress Semiconductor Corporation | Multi-ported nonvolatile memory device with bank allocation and related systems and methods |
| US11385829B2 (en) * | 2019-08-05 | 2022-07-12 | Cypress Semiconductor Corporation | Memory controller for non-interfering accesses to nonvolatile memory by different masters, and related systems and methods |
-
2020
- 2020-12-17 US US17/125,927 patent/US11971832B2/en active Active
-
2021
- 2021-10-07 CN CN202180068238.6A patent/CN116324737A/zh active Pending
- 2021-10-07 DE DE112021005295.0T patent/DE112021005295T5/de active Pending
- 2021-10-07 JP JP2023521315A patent/JP7612851B2/ja active Active
- 2021-10-07 WO PCT/US2021/053916 patent/WO2022076652A1/en not_active Ceased
-
2024
- 2024-04-26 US US18/647,048 patent/US12596659B2/en active Active
- 2024-12-25 JP JP2024229142A patent/JP2025041887A/ja active Pending
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