JP7612851B2 - ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム - Google Patents

ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム Download PDF

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Publication number
JP7612851B2
JP7612851B2 JP2023521315A JP2023521315A JP7612851B2 JP 7612851 B2 JP7612851 B2 JP 7612851B2 JP 2023521315 A JP2023521315 A JP 2023521315A JP 2023521315 A JP2023521315 A JP 2023521315A JP 7612851 B2 JP7612851 B2 JP 7612851B2
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command
data
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read
access
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JP2023544802A (ja
JP2023544802A5 (https=
Inventor
ズィットロー クリフォード
ロスナー スティーブン
ファン アントウェルペン ハンス
アンドリュー ウェイトリー モーガン
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Infineon Technologies LLC
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Infineon Technologies LLC
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Priority to JP2024229142A priority Critical patent/JP2025041887A/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
JP2023521315A 2020-10-07 2021-10-07 ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム Active JP7612851B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024229142A JP2025041887A (ja) 2020-10-07 2024-12-25 ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202063088572P 2020-10-07 2020-10-07
US63/088,572 2020-10-07
US17/125,927 US11971832B2 (en) 2020-10-07 2020-12-17 Methods, devices and systems for high speed transactions with nonvolatile memory on a double data rate memory bus
US17/125,927 2020-12-17
PCT/US2021/053916 WO2022076652A1 (en) 2020-10-07 2021-10-07 Systems for high speed transactions with nonvolatile memory on a double data rate memory bus

Related Child Applications (1)

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JP2024229142A Division JP2025041887A (ja) 2020-10-07 2024-12-25 ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム

Publications (3)

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JP2023544802A JP2023544802A (ja) 2023-10-25
JP2023544802A5 JP2023544802A5 (https=) 2024-05-23
JP7612851B2 true JP7612851B2 (ja) 2025-01-14

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JP2023521315A Active JP7612851B2 (ja) 2020-10-07 2021-10-07 ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム
JP2024229142A Pending JP2025041887A (ja) 2020-10-07 2024-12-25 ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム

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JP2024229142A Pending JP2025041887A (ja) 2020-10-07 2024-12-25 ダブルデータレートメモリバス上での不揮発性メモリによる高速トランザクションのためのシステム

Country Status (5)

Country Link
US (2) US11971832B2 (https=)
JP (2) JP7612851B2 (https=)
CN (1) CN116324737A (https=)
DE (1) DE112021005295T5 (https=)
WO (1) WO2022076652A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009266315A (ja) 2008-04-25 2009-11-12 Elpida Memory Inc 半導体記憶装置及びその制御方法
US20130013878A1 (en) 2010-04-14 2013-01-10 Rambus Inc. Levelization of Memory Interface for Communicating with Multiple Memory Devices
US20160378366A1 (en) 2015-06-24 2016-12-29 Intel Corporation Internal consecutive row access for long burst length
JP2018524708A (ja) 2015-06-30 2018-08-30 クアルコム，インコーポレイテッド 低電力メモリサブシステムにおけるメモリアレイおよびリンク誤り訂正
JP2020077451A (ja) 2018-10-17 2020-05-21 旺宏電子股▲ふん▼有限公司 非順次的ページ連続リード

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140325105A1 (en) * 2013-04-26 2014-10-30 Advanced Micro Devices, Inc. Memory system components for split channel architecture
US10534540B2 (en) * 2016-06-06 2020-01-14 Micron Technology, Inc. Memory protocol
US10810144B2 (en) 2016-06-08 2020-10-20 Samsung Electronics Co., Ltd. System and method for operating a DRR-compatible asynchronous memory module
US10621096B2 (en) * 2016-09-08 2020-04-14 Seagate Technology Llc Read ahead management in a multi-stream workload
WO2018081746A1 (en) 2016-10-31 2018-05-03 Intel Corporation Applying chip select for memory device identification and power management control
WO2018232736A1 (zh) 2017-06-23 2018-12-27 华为技术有限公司 内存访问技术及计算机系统
US10541042B2 (en) 2018-04-23 2020-01-21 Microsoft Technology Licensing, Llc Level-crossing memory trace inspection queries
US10692560B2 (en) * 2018-06-06 2020-06-23 Intel Corporation Periodic calibrations during memory device self refresh
US11249678B2 (en) * 2019-07-26 2022-02-15 Qualcomm Incorporated Serial memory device single-bit or plurality-bit serial I/O mode selection
US11030128B2 (en) * 2019-08-05 2021-06-08 Cypress Semiconductor Corporation Multi-ported nonvolatile memory device with bank allocation and related systems and methods
US11385829B2 (en) * 2019-08-05 2022-07-12 Cypress Semiconductor Corporation Memory controller for non-interfering accesses to nonvolatile memory by different masters, and related systems and methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009266315A (ja) 2008-04-25 2009-11-12 Elpida Memory Inc 半導体記憶装置及びその制御方法
US20130013878A1 (en) 2010-04-14 2013-01-10 Rambus Inc. Levelization of Memory Interface for Communicating with Multiple Memory Devices
US20160378366A1 (en) 2015-06-24 2016-12-29 Intel Corporation Internal consecutive row access for long burst length
JP2018524708A (ja) 2015-06-30 2018-08-30 クアルコム，インコーポレイテッド 低電力メモリサブシステムにおけるメモリアレイおよびリンク誤り訂正
JP2020077451A (ja) 2018-10-17 2020-05-21 旺宏電子股▲ふん▼有限公司 非順次的ページ連続リード

Also Published As

Publication number Publication date
DE112021005295T5 (de) 2023-08-31
US20220107908A1 (en) 2022-04-07
CN116324737A (zh) 2023-06-23
US11971832B2 (en) 2024-04-30
US20240345972A1 (en) 2024-10-17
JP2023544802A (ja) 2023-10-25
JP2025041887A (ja) 2025-03-26
WO2022076652A1 (en) 2022-04-14
US12596659B2 (en) 2026-04-07

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