CN116324737A - 在双倍数据速率存储器总线上与非易失性存储器进行高速事务处理的系统 - Google Patents

在双倍数据速率存储器总线上与非易失性存储器进行高速事务处理的系统 Download PDF

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Publication number
CN116324737A
CN116324737A CN202180068238.6A CN202180068238A CN116324737A CN 116324737 A CN116324737 A CN 116324737A CN 202180068238 A CN202180068238 A CN 202180068238A CN 116324737 A CN116324737 A CN 116324737A
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CN
China
Prior art keywords
command
nvr
data
commands
nvm
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Pending
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CN202180068238.6A
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English (en)
Chinese (zh)
Inventor
C·济特劳
S·罗斯纳
H·范安特沃彭
M·A·惠特利
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Infineon Technology Co ltd
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Infineon Technology Co ltd
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Publication of CN116324737A publication Critical patent/CN116324737A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
CN202180068238.6A 2020-10-07 2021-10-07 在双倍数据速率存储器总线上与非易失性存储器进行高速事务处理的系统 Pending CN116324737A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202063088572P 2020-10-07 2020-10-07
US63/088,572 2020-10-07
US17/125,927 US11971832B2 (en) 2020-10-07 2020-12-17 Methods, devices and systems for high speed transactions with nonvolatile memory on a double data rate memory bus
US17/125,927 2020-12-17
PCT/US2021/053916 WO2022076652A1 (en) 2020-10-07 2021-10-07 Systems for high speed transactions with nonvolatile memory on a double data rate memory bus

Publications (1)

Publication Number Publication Date
CN116324737A true CN116324737A (zh) 2023-06-23

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CN202180068238.6A Pending CN116324737A (zh) 2020-10-07 2021-10-07 在双倍数据速率存储器总线上与非易失性存储器进行高速事务处理的系统

Country Status (5)

Country Link
US (2) US11971832B2 (https=)
JP (2) JP7612851B2 (https=)
CN (1) CN116324737A (https=)
DE (1) DE112021005295T5 (https=)
WO (1) WO2022076652A1 (https=)

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5474313B2 (ja) 2008-04-25 2014-04-16 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置及びその制御方法
WO2011130007A1 (en) * 2010-04-14 2011-10-20 Rambus Inc. Levelization of memory interface for communicating with multiple memory devices
US20140325105A1 (en) * 2013-04-26 2014-10-30 Advanced Micro Devices, Inc. Memory system components for split channel architecture
US20160378366A1 (en) 2015-06-24 2016-12-29 Intel Corporation Internal consecutive row access for long burst length
US10061645B2 (en) 2015-06-30 2018-08-28 Qualcomm Incorporated Memory array and link error correction in a low power memory sub-system
US10534540B2 (en) * 2016-06-06 2020-01-14 Micron Technology, Inc. Memory protocol
US10810144B2 (en) 2016-06-08 2020-10-20 Samsung Electronics Co., Ltd. System and method for operating a DRR-compatible asynchronous memory module
US10621096B2 (en) * 2016-09-08 2020-04-14 Seagate Technology Llc Read ahead management in a multi-stream workload
WO2018081746A1 (en) 2016-10-31 2018-05-03 Intel Corporation Applying chip select for memory device identification and power management control
WO2018232736A1 (zh) 2017-06-23 2018-12-27 华为技术有限公司 内存访问技术及计算机系统
US10541042B2 (en) 2018-04-23 2020-01-21 Microsoft Technology Licensing, Llc Level-crossing memory trace inspection queries
US10692560B2 (en) * 2018-06-06 2020-06-23 Intel Corporation Periodic calibrations during memory device self refresh
TWI727449B (zh) 2018-10-17 2021-05-11 旺宏電子股份有限公司 非循序頁面連續讀取
US11249678B2 (en) * 2019-07-26 2022-02-15 Qualcomm Incorporated Serial memory device single-bit or plurality-bit serial I/O mode selection
US11030128B2 (en) * 2019-08-05 2021-06-08 Cypress Semiconductor Corporation Multi-ported nonvolatile memory device with bank allocation and related systems and methods
US11385829B2 (en) * 2019-08-05 2022-07-12 Cypress Semiconductor Corporation Memory controller for non-interfering accesses to nonvolatile memory by different masters, and related systems and methods

Also Published As

Publication number Publication date
DE112021005295T5 (de) 2023-08-31
US20220107908A1 (en) 2022-04-07
US11971832B2 (en) 2024-04-30
US20240345972A1 (en) 2024-10-17
JP2023544802A (ja) 2023-10-25
JP2025041887A (ja) 2025-03-26
WO2022076652A1 (en) 2022-04-14
US12596659B2 (en) 2026-04-07
JP7612851B2 (ja) 2025-01-14

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