TWI799542B - 電子設備及使用ｄｒａｍ之方法 - Google Patents

電子設備及使用ｄｒａｍ之方法 Download PDF

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Publication number
TWI799542B
TWI799542B TW108109166A TW108109166A TWI799542B TW I799542 B TWI799542 B TW I799542B TW 108109166 A TW108109166 A TW 108109166A TW 108109166 A TW108109166 A TW 108109166A TW I799542 B TWI799542 B TW I799542B
Authority
TW
Taiwan
Prior art keywords
dram
electronic apparatus
electronic
Prior art date
Application number
TW108109166A
Other languages
English (en)
Other versions
TW201944257A (zh
Inventor
艾瑞克 麥圖利克
派翠克 飛利浦
馬克 莫尼爾
Original Assignee
美商微晶片科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商微晶片科技公司 filed Critical 美商微晶片科技公司
Publication of TW201944257A publication Critical patent/TW201944257A/zh
Application granted granted Critical
Publication of TWI799542B publication Critical patent/TWI799542B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Dram (AREA)
TW108109166A 2018-04-23 2019-03-18 電子設備及使用ｄｒａｍ之方法 TWI799542B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/959,764 US10620881B2 (en) 2018-04-23 2018-04-23 Access to DRAM through a reuse of pins
US15/959,764 2018-04-23

Publications (2)

Publication Number Publication Date
TW201944257A TW201944257A (zh) 2019-11-16
TWI799542B true TWI799542B (zh) 2023-04-21

Family

ID=66530444

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108109166A TWI799542B (zh) 2018-04-23 2019-03-18 電子設備及使用ｄｒａｍ之方法

Country Status (5)

Country Link
US (1) US10620881B2 (zh)
CN (1) CN112005226A (zh)
DE (1) DE112019002100T5 (zh)
TW (1) TWI799542B (zh)
WO (1) WO2019209678A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI692759B (zh) * 2019-05-15 2020-05-01 瑞昱半導體股份有限公司 同時存取第一動態隨機存取記憶體與第二動態隨機存取記憶體的方法及相關的記憶體控制器
US10998076B1 (en) * 2019-11-01 2021-05-04 Realtek Semiconductor Corporation Signal calibration method used in memory apparatus
JP2022154323A (ja) 2021-03-30 2022-10-13 キオクシア株式会社 半導体記憶装置
WO2022241731A1 (zh) * 2021-05-20 2022-11-24 华为技术有限公司 存储器芯片及其控制方法
CN114153402B (zh) * 2022-02-09 2022-05-03 阿里云计算有限公司 存储器及其数据读写方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6598148B1 (en) * 1989-08-03 2003-07-22 Patriot Scientific Corporation High performance microprocessor having variable speed system clock
US6859399B1 (en) * 2000-05-17 2005-02-22 Marvell International, Ltd. Memory architecture and system and multiport interface protocol
TW200910371A (en) * 2007-04-25 2009-03-01 Micron Technology Inc NAND interface
TW201101327A (en) * 2009-06-25 2011-01-01 Mediatek Inc Flash memory device, memory device and a method for controlling a flash memory device
US20130111122A1 (en) * 2011-10-31 2013-05-02 Futurewei Technologies, Inc. Method and apparatus for network table lookups

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004310547A (ja) * 2003-04-08 2004-11-04 Matsushita Electric Ind Co Ltd 情報処理装置、メモリ、情報処理方法及びプログラム
US20060294295A1 (en) * 2005-06-24 2006-12-28 Yukio Fukuzo DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device
US20100325333A1 (en) 2008-10-14 2010-12-23 Texas Instruments Incorporated Method Allowing Processor with Fewer Pins to Use SDRAM
US8321649B2 (en) * 2011-03-18 2012-11-27 Freescale Semiconductor, Inc. Memory controller address and data pin multiplexing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6598148B1 (en) * 1989-08-03 2003-07-22 Patriot Scientific Corporation High performance microprocessor having variable speed system clock
US6859399B1 (en) * 2000-05-17 2005-02-22 Marvell International, Ltd. Memory architecture and system and multiport interface protocol
TW200910371A (en) * 2007-04-25 2009-03-01 Micron Technology Inc NAND interface
TW201101327A (en) * 2009-06-25 2011-01-01 Mediatek Inc Flash memory device, memory device and a method for controlling a flash memory device
US20130111122A1 (en) * 2011-10-31 2013-05-02 Futurewei Technologies, Inc. Method and apparatus for network table lookups

Also Published As

Publication number Publication date
WO2019209678A1 (en) 2019-10-31
US20190324686A1 (en) 2019-10-24
DE112019002100T5 (de) 2021-01-14
US10620881B2 (en) 2020-04-14
TW201944257A (zh) 2019-11-16
CN112005226A (zh) 2020-11-27

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