JP2023541730A - パッケージング構造及びその製造方法 - Google Patents

パッケージング構造及びその製造方法 Download PDF

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Publication number
JP2023541730A
JP2023541730A JP2021578142A JP2021578142A JP2023541730A JP 2023541730 A JP2023541730 A JP 2023541730A JP 2021578142 A JP2021578142 A JP 2021578142A JP 2021578142 A JP2021578142 A JP 2021578142A JP 2023541730 A JP2023541730 A JP 2023541730A
Authority
JP
Japan
Prior art keywords
layer
solder resist
conductive circuit
circuit
packaging structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021578142A
Other languages
English (en)
Japanese (ja)
Inventor
凱 朱
新 谷
樺 繆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shennan Circuit Co Ltd
Original Assignee
Shennan Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shennan Circuit Co Ltd filed Critical Shennan Circuit Co Ltd
Publication of JP2023541730A publication Critical patent/JP2023541730A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)
  • Containers And Plastic Fillers For Packaging (AREA)
JP2021578142A 2021-08-16 2021-09-23 パッケージング構造及びその製造方法 Pending JP2023541730A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN202110937129.5 2021-08-16
CN202110937129.5A CN115706017A (zh) 2021-08-16 2021-08-16 一种封装机构及其制备方法
PCT/CN2021/119973 WO2023019684A1 (zh) 2021-08-16 2021-09-23 一种封装机构及其制备方法

Publications (1)

Publication Number Publication Date
JP2023541730A true JP2023541730A (ja) 2023-10-04

Family

ID=85180370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021578142A Pending JP2023541730A (ja) 2021-08-16 2021-09-23 パッケージング構造及びその製造方法

Country Status (4)

Country Link
JP (1) JP2023541730A (zh)
CN (1) CN115706017A (zh)
TW (1) TWI790880B (zh)
WO (1) WO2023019684A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117156730B (zh) * 2023-10-31 2024-01-26 江苏普诺威电子股份有限公司 嵌入式封装基板及其制作方法、堆叠封装结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587882A (en) * 1995-08-30 1996-12-24 Hewlett-Packard Company Thermal interface for a heat sink and a plurality of integrated circuits mounted on a substrate
EP2287897A3 (en) * 1996-05-27 2011-11-02 Dai Nippon Printing Co., Ltd. Circuit member for semiconductor device, semiconductor device using the same, and process for producing said circuit member and said semiconductor device
TWI355054B (en) * 2008-05-16 2011-12-21 Unimicron Technology Corp Method for fabricating a packaging substrate
US20140295623A1 (en) * 2013-03-29 2014-10-02 Kinsus Interconnect Technology Corp. Method of packaging a chip and a substrate
CN103268871B (zh) * 2013-05-20 2015-11-18 江苏长电科技股份有限公司 超薄高密度多层线路芯片正装封装结构及制作方法
CN106486382B (zh) * 2015-08-28 2019-06-18 碁鼎科技秦皇岛有限公司 封装基板、封装结构及其制作方法
TWI582921B (zh) * 2015-12-02 2017-05-11 南茂科技股份有限公司 半導體封裝結構及其製作方法
CN112086417B (zh) * 2020-10-28 2021-02-12 广东佛智芯微电子技术研究有限公司 一种高效散热的多芯片3d堆叠封装结构及封装方法
CN112928028A (zh) * 2021-01-22 2021-06-08 广东佛智芯微电子技术研究有限公司 一种具有嵌入式线路的板级芯片封装方法及其封装结构

Also Published As

Publication number Publication date
TW202310092A (zh) 2023-03-01
WO2023019684A1 (zh) 2023-02-23
CN115706017A (zh) 2023-02-17
TWI790880B (zh) 2023-01-21

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