JP2023125724A - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP2023125724A
JP2023125724A JP2022029986A JP2022029986A JP2023125724A JP 2023125724 A JP2023125724 A JP 2023125724A JP 2022029986 A JP2022029986 A JP 2022029986A JP 2022029986 A JP2022029986 A JP 2022029986A JP 2023125724 A JP2023125724 A JP 2023125724A
Authority
JP
Japan
Prior art keywords
layer
pad
insulating layer
wiring board
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2022029986A
Other languages
English (en)
Japanese (ja)
Other versions
JP2023125724A5 (https=
Inventor
輝 田中
Teru Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2022029986A priority Critical patent/JP2023125724A/ja
Priority to US18/169,441 priority patent/US12550762B2/en
Publication of JP2023125724A publication Critical patent/JP2023125724A/ja
Publication of JP2023125724A5 publication Critical patent/JP2023125724A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2022029986A 2022-02-28 2022-02-28 配線基板及びその製造方法 Pending JP2023125724A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2022029986A JP2023125724A (ja) 2022-02-28 2022-02-28 配線基板及びその製造方法
US18/169,441 US12550762B2 (en) 2022-02-28 2023-02-15 Interconnect substrate and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2022029986A JP2023125724A (ja) 2022-02-28 2022-02-28 配線基板及びその製造方法

Publications (2)

Publication Number Publication Date
JP2023125724A true JP2023125724A (ja) 2023-09-07
JP2023125724A5 JP2023125724A5 (https=) 2024-11-21

Family

ID=87761209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022029986A Pending JP2023125724A (ja) 2022-02-28 2022-02-28 配線基板及びその製造方法

Country Status (2)

Country Link
US (1) US12550762B2 (https=)
JP (1) JP2023125724A (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7711870B2 (ja) * 2021-10-19 2025-07-23 新光電気工業株式会社 配線基板及びその製造方法
JP2023125724A (ja) 2022-02-28 2023-09-07 新光電気工業株式会社 配線基板及びその製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003229512A (ja) * 2002-02-01 2003-08-15 Nec Toppan Circuit Solutions Toyama Inc 半導体チップ搭載用基板およびその製造方法と半導体装置およびその製造方法
JP2011129808A (ja) * 2009-12-21 2011-06-30 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2013073994A (ja) * 2011-09-27 2013-04-22 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2018060922A (ja) * 2016-10-05 2018-04-12 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
JP2021052104A (ja) * 2019-09-25 2021-04-01 イビデン株式会社 プリント配線板およびその製造方法
JP2022108485A (ja) * 2021-01-13 2022-07-26 イビデン株式会社 配線基板

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006013118A (ja) 2004-06-25 2006-01-12 Shinko Electric Ind Co Ltd 可撓性回路基板及びその製造方法
US20080093109A1 (en) * 2006-10-19 2008-04-24 Phoenix Precision Technology Corporation Substrate with surface finished structure and method for making the same
JP5214139B2 (ja) 2006-12-04 2013-06-19 新光電気工業株式会社 配線基板及びその製造方法
JP5026400B2 (ja) 2008-12-12 2012-09-12 新光電気工業株式会社 配線基板及びその製造方法
JP5502624B2 (ja) 2010-07-08 2014-05-28 新光電気工業株式会社 配線基板の製造方法及び配線基板
KR101897013B1 (ko) * 2011-12-08 2018-10-29 엘지이노텍 주식회사 인쇄회로기판 및 이의 제조 방법
TWI525769B (zh) 2013-11-27 2016-03-11 矽品精密工業股份有限公司 封裝基板及其製法
CN108076584B (zh) * 2016-11-15 2020-04-14 鹏鼎控股(深圳)股份有限公司 柔性电路板、电路板元件及柔性电路板的制作方法
US10347507B2 (en) * 2017-09-29 2019-07-09 Lg Innotek Co., Ltd. Printed circuit board
US12033932B2 (en) 2020-07-28 2024-07-09 Gerald Ho Kim Thermal and electrical interface for flip-chip devices
JP7700986B2 (ja) * 2021-10-19 2025-07-01 新光電気工業株式会社 配線基板及びその製造方法
JP2023125724A (ja) 2022-02-28 2023-09-07 新光電気工業株式会社 配線基板及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003229512A (ja) * 2002-02-01 2003-08-15 Nec Toppan Circuit Solutions Toyama Inc 半導体チップ搭載用基板およびその製造方法と半導体装置およびその製造方法
JP2011129808A (ja) * 2009-12-21 2011-06-30 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2013073994A (ja) * 2011-09-27 2013-04-22 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2018060922A (ja) * 2016-10-05 2018-04-12 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
JP2021052104A (ja) * 2019-09-25 2021-04-01 イビデン株式会社 プリント配線板およびその製造方法
JP2022108485A (ja) * 2021-01-13 2022-07-26 イビデン株式会社 配線基板

Also Published As

Publication number Publication date
US20230275015A1 (en) 2023-08-31
US12550762B2 (en) 2026-02-10

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