JP2022551657A5 - - Google Patents

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Publication number
JP2022551657A5
JP2022551657A5 JP2022521598A JP2022521598A JP2022551657A5 JP 2022551657 A5 JP2022551657 A5 JP 2022551657A5 JP 2022521598 A JP2022521598 A JP 2022521598A JP 2022521598 A JP2022521598 A JP 2022521598A JP 2022551657 A5 JP2022551657 A5 JP 2022551657A5
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JP
Japan
Prior art keywords
range
silicon
layer
silicon wafer
arsenic
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JP2022521598A
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English (en)
Japanese (ja)
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JP2022551657A (ja
JP7651565B2 (ja
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Priority claimed from PCT/US2020/054588 external-priority patent/WO2021071955A1/en
Publication of JP2022551657A publication Critical patent/JP2022551657A/ja
Publication of JP2022551657A5 publication Critical patent/JP2022551657A5/ja
Priority to JP2025040194A priority Critical patent/JP2025090768A/ja
Application granted granted Critical
Publication of JP7651565B2 publication Critical patent/JP7651565B2/ja
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JP2022521598A 2019-10-07 2020-10-07 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法 Active JP7651565B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025040194A JP2025090768A (ja) 2019-10-07 2025-03-13 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201962911827P 2019-10-07 2019-10-07
US201962911835P 2019-10-07 2019-10-07
US201962911843P 2019-10-07 2019-10-07
US62/911,827 2019-10-07
US62/911,835 2019-10-07
US62/911,843 2019-10-07
PCT/US2020/054588 WO2021071955A1 (en) 2019-10-07 2020-10-07 Silicon-on-insulator substrate including trap-rich layer and methods for making thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025040194A Division JP2025090768A (ja) 2019-10-07 2025-03-13 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法

Publications (3)

Publication Number Publication Date
JP2022551657A JP2022551657A (ja) 2022-12-12
JP2022551657A5 true JP2022551657A5 (https=) 2023-10-17
JP7651565B2 JP7651565B2 (ja) 2025-03-26

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ID=75274993

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Application Number Title Priority Date Filing Date
JP2022521598A Active JP7651565B2 (ja) 2019-10-07 2020-10-07 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法
JP2025040194A Pending JP2025090768A (ja) 2019-10-07 2025-03-13 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法

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JP2025040194A Pending JP2025090768A (ja) 2019-10-07 2025-03-13 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法

Country Status (4)

Country Link
US (3) US11145537B2 (https=)
EP (1) EP4042486A4 (https=)
JP (2) JP7651565B2 (https=)
WO (1) WO2021071955A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113948446B (zh) * 2021-09-28 2025-01-24 苏州华太电子技术股份有限公司 半导体工艺以及半导体结构
US12566343B2 (en) * 2023-11-10 2026-03-03 HyperLight Corporation Thin film lithium-containing photonics wafer having a trap-rich substrate

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798081A (en) 1972-02-14 1974-03-19 Ibm Method for diffusing as into silicon from a solid phase
US6127285A (en) * 1997-02-28 2000-10-03 Dallas Instruments Incorporated Interlevel dielectrics with reduced dielectric constant
JP2007019170A (ja) * 2005-07-06 2007-01-25 Fuji Electric Holdings Co Ltd 部分ｓｏｉ基板、部分ｓｏｉ基板の製造方法、及び、ｓｏｉ基板
JP5057804B2 (ja) 2007-03-12 2012-10-24 株式会社東芝 半導体装置
FR3024587B1 (fr) 2014-08-01 2018-01-26 Soitec Procede de fabrication d'une structure hautement resistive
US10312134B2 (en) * 2014-09-04 2019-06-04 Globalwafers Co., Ltd. High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
DE102015211087B4 (de) 2015-06-17 2019-12-05 Soitec Verfahren zur Herstellung eines Hochwiderstands-Halbleiter-auf-Isolator-Substrates
US10622247B2 (en) * 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
US9991155B2 (en) * 2016-09-30 2018-06-05 GlobalFoundries, Inc. Local trap-rich isolation
US10276371B2 (en) * 2017-05-19 2019-04-30 Psemi Corporation Managed substrate effects for stabilized SOI FETs
US20190273028A1 (en) 2018-03-02 2019-09-05 Globalfoundries Inc. Device structures formed with a silicon-on-insulator substrate that includes a trap-rich layer

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