JP7651565B2 - トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法 - Google Patents

トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法 Download PDF

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JP7651565B2
JP7651565B2 JP2022521598A JP2022521598A JP7651565B2 JP 7651565 B2 JP7651565 B2 JP 7651565B2 JP 2022521598 A JP2022521598 A JP 2022521598A JP 2022521598 A JP2022521598 A JP 2022521598A JP 7651565 B2 JP7651565 B2 JP 7651565B2
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layer
range
silicon
thickness
silicon wafer
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JP2022551657A5 (https=
JP2022551657A (ja
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ボウマン，ロン
フランクリン，マーク
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CROCKETT, Addison
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CROCKETT, Addison
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/16—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a liquid phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Formation Of Insulating Films (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
JP2022521598A 2019-10-07 2020-10-07 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法 Active JP7651565B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025040194A JP2025090768A (ja) 2019-10-07 2025-03-13 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201962911827P 2019-10-07 2019-10-07
US201962911835P 2019-10-07 2019-10-07
US201962911843P 2019-10-07 2019-10-07
US62/911,827 2019-10-07
US62/911,835 2019-10-07
US62/911,843 2019-10-07
PCT/US2020/054588 WO2021071955A1 (en) 2019-10-07 2020-10-07 Silicon-on-insulator substrate including trap-rich layer and methods for making thereof

Related Child Applications (1)

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JP2025040194A Division JP2025090768A (ja) 2019-10-07 2025-03-13 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法

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JP2022551657A JP2022551657A (ja) 2022-12-12
JP2022551657A5 JP2022551657A5 (https=) 2023-10-17
JP7651565B2 true JP7651565B2 (ja) 2025-03-26

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JP2025040194A Pending JP2025090768A (ja) 2019-10-07 2025-03-13 トラップリッチ層を含むシリコン・オン・インシュレーター基板およびその作製方法

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US (3) US11145537B2 (https=)
EP (1) EP4042486A4 (https=)
JP (2) JP7651565B2 (https=)
WO (1) WO2021071955A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113948446B (zh) * 2021-09-28 2025-01-24 苏州华太电子技术股份有限公司 半导体工艺以及半导体结构
US12566343B2 (en) * 2023-11-10 2026-03-03 HyperLight Corporation Thin film lithium-containing photonics wafer having a trap-rich substrate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227084A (ja) 2007-03-12 2008-09-25 Toshiba Corp 半導体装置
JP2017011262A (ja) 2015-06-17 2017-01-12 ソイテックＳｏｉｔｅｃ 高抵抗率半導体オンインシュレータ基板の製造方法
JP2017532758A (ja) 2014-08-01 2017-11-02 ソイテック 無線周波アプリケーションの構造
US20180337043A1 (en) 2017-05-19 2018-11-22 Psemi Corporation Managed Substrate Effects for Stabilized SOI FETs

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US3798081A (en) 1972-02-14 1974-03-19 Ibm Method for diffusing as into silicon from a solid phase
US6127285A (en) * 1997-02-28 2000-10-03 Dallas Instruments Incorporated Interlevel dielectrics with reduced dielectric constant
JP2007019170A (ja) * 2005-07-06 2007-01-25 Fuji Electric Holdings Co Ltd 部分ｓｏｉ基板、部分ｓｏｉ基板の製造方法、及び、ｓｏｉ基板
US10312134B2 (en) * 2014-09-04 2019-06-04 Globalwafers Co., Ltd. High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
US10622247B2 (en) * 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
US9991155B2 (en) * 2016-09-30 2018-06-05 GlobalFoundries, Inc. Local trap-rich isolation
US20190273028A1 (en) 2018-03-02 2019-09-05 Globalfoundries Inc. Device structures formed with a silicon-on-insulator substrate that includes a trap-rich layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227084A (ja) 2007-03-12 2008-09-25 Toshiba Corp 半導体装置
JP2017532758A (ja) 2014-08-01 2017-11-02 ソイテック 無線周波アプリケーションの構造
JP2017011262A (ja) 2015-06-17 2017-01-12 ソイテックＳｏｉｔｅｃ 高抵抗率半導体オンインシュレータ基板の製造方法
US20180337043A1 (en) 2017-05-19 2018-11-22 Psemi Corporation Managed Substrate Effects for Stabilized SOI FETs

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WO2021071955A1 (en) 2021-04-15
US20240297070A1 (en) 2024-09-05
US20210104430A1 (en) 2021-04-08
EP4042486A4 (en) 2023-09-06
US11894261B2 (en) 2024-02-06
US12557613B2 (en) 2026-02-17
US11145537B2 (en) 2021-10-12
JP2022551657A (ja) 2022-12-12
JP2025090768A (ja) 2025-06-17
US20210407850A1 (en) 2021-12-30
EP4042486A1 (en) 2022-08-17

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