JP2022546472A - コンピュータデバイス及びその製造方法 - Google Patents
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Abstract
Description
特定のタイプのコンピュータがGraphcore社によって最近開発されており、これは、インテリジェントプロセッシングユニット(IPU)と呼ばれ、例えば米国特許出願公開第15/886009号明細書に記載されている。
ここで、Cは、容量であり、Iは、電流であり、Vは、電圧であり、及びFは、クロック周波数である。これは、推定される合計オンダイ容量のおよそ2.5%である。
E=0.5LI2
ここで、Lは、実効インダクタンスであり、Iは、チップによって引き込まれる電流である。
だけ大きくすることが可能であり、したがって、クロック周波数は、11%だけ大きくすることが可能である。性能は、クロック周波数に比例するため、性能も11%だけ向上させることが可能である。
Claims (25)
- コンピュータ構造であって、
計算動作を実行するように構成されたコンピュータ回路類が形成される第1のシリコン基板であって、自己支持深さ及び対向面を有する第1のシリコン基板と、
複数の分布容量ユニットが形成される第2のシリコン基板であって、前記第1のシリコン基板の前記対向面と重なって位置する対向面を有し、前記対向面間で構造の深さ方向に延在して配置されたコネクタのセットを介して前記第1のシリコン基板に接続され、前記第2のシリコン基板の前記対向面は、前記第1のシリコン基板の前記対向面の平面寸法に一致する平面寸法を有する、第2のシリコン基板と、
を含み、
前記第2のシリコン基板は、前記コンピュータ構造を電源電圧に接続するための複数のコネクタ端子が配置される外側表面を有し、前記第2のシリコン基板は、前記第1のシリコン基板よりも小さい深さを有する、コンピュータ構造。 - 前記第1及び第2のシリコン基板の前記対向面は、1つ又は複数の接合層によって接合される、請求項1に記載のコンピュータ構造。
- コネクタは、前記第2のシリコン基板を通して前記第1のシリコン基板まで延在して、前記コネクタ端子と前記第1のシリコン基板との間に電気接続を提供するシリコン貫通ビアを含む、請求項1又は2に記載のコンピュータ構造。
- 各分布容量ユニットは、予め決められた数の0.1~1.5nFの範囲の容量を有するキャパシタブロックを含む、請求項1に記載のコンピュータ構造。
- 前記予め決められた数は、10~20である、請求項4に記載のコンピュータ構造。
- 各分布容量ユニットは、5~30nFの範囲の容量を有する、請求項4又は5に記載のコンピュータ構造。
- 分布容量ユニットの総平面面積は、前記第1のシリコン基板の総平面面積の少なくとも80%であり、前記複数の分布容量ユニットの容量は、0.5μF/mm2~3μF/mm2の範囲である、請求項1~6のいずれか一項に記載のコンピュータ構造。
- 前記第1のシリコン基板は、400μm~1000μmの深さを有する、請求項1~7のいずれか一項に記載のコンピュータ構造。
- 前記第2のシリコン基板は、10μm未満の非自己支持深さを有する、請求項1~8のいずれか一項に記載のコンピュータ構造。
- 前記分布容量ユニットは、規則的なアレイ状に配置され、各分布容量ユニットは、電源電圧コネクタ端子及びアースコネクタ端子に接続される、請求項1~9のいずれか一項に記載のコンピュータ構造。
- 各コネクタ端子は、4つの異なる分布容量ユニットに接続される、請求項10に記載のコンピュータ構造。
- 前記コネクタのセットは、前記コネクタ端子と軸方向に位置合わせされた前記第1及び第2のシリコン基板間に接続を提供する、請求項1~11のいずれか一項に記載のコンピュータ構造。
- 各分布容量ユニットは、2つの禁止領域を含み、前記禁止領域は、それぞれのコネクタ端子の場所にあり、前記禁止領域及び前記キャパシタブロックは、等しいサイズである、請求項4に記載のコンピュータ構造。
- 各キャパシタブロックは、六角形アレイ状に配置されたトレンチキャパシタのアレイを含み、各トレンチキャパシタは、6つの隣接するトレンチキャパシタを有し、各トレンチキャパシタは、その隣接するトレンチキャパシタから等距離に位置する、請求項4又は5に記載のコンピュータ構造。
- 前記シリコン貫通ビアは、前記分布容量ユニットの前記禁止領域に提供される、請求項3又は13に記載のコンピュータ構造。
- 前記コンピュータ回路類は、実行ユニット及びローカルメモリをそれぞれ有する複数の処理ユニットを含み、複数の処理ユニットは、並行して計算するように構成される、請求項1に記載のコンピュータ構造。
- 前記コンピュータ回路類は、バルク同期並列プロトコルに従って動作するように複数の処理ユニットを制御するように構成された同期回路類を含む、請求項16に記載のコンピュータ構造。
- 前記コンピュータ回路類は、前記処理ユニットの動作を制御するために接続されたクロックを含む、請求項16又は17に記載のコンピュータ構造。
- コンピュータ構造を製造する方法であって、
計算動作を実行するように構成されたコンピュータ回路類を含む第1のシリコン基板であって、自己支持深さを有する第1のシリコン基板を提供することと、
複数の分布容量ユニットを含む第2のシリコン基板を提供することと、
前記第1のシリコン基板の対向面を前記第2のシリコン基板の対向面に接合することであって、前記対向面は、重なって位置し、前記対向面は、一致する平面寸法を有することと、
前記第2のシリコン基板を薄化することであって、前記第2のシリコン基板は、前記第1のシリコン基板よりも小さい深さを有することと、
前記第2のシリコン基板の外側表面上において、前記コンピュータ構造を電源電圧に接続するための複数のコネクタ端子を提供することと、
を含む方法。 - 前記第2のシリコン基板を薄化した後、前記第2のシリコン基板にシリコン貫通ビアを形成して、前記コネクタ端子と前記第1のシリコン基板との間に接続を提供することをさらに含む、請求項19に記載の方法。
- 前記第2のシリコン基板は、10μm未満の深さに薄化され、それにより、前記第2のシリコン基板は、非自己支持深さを有する、請求項19又は20に記載の方法。
- 前記第1のシリコン基板は、700μm~800μmの深さを有する、請求項13~15のいずれか一項に記載の方法。
- 前記分布容量ユニットは、規則的なアレイで配置され、前記方法は、各分布容量ユニットを電源電圧コネクタ端子及びアースコネクタ端子に接続することを含む、請求項19~22のいずれか一項に記載の方法。
- 各分布容量ユニットは、予め決められた数のキャパシタブロック及び2つの禁止領域を含み、前記禁止領域は、前記2つのコネクタ端子の場所にあり、前記禁止領域及び前記キャパシタブロックは、等しいサイズである、請求項23に記載の方法。
- 前記禁止領域の場所に前記シリコン貫通ビアを形成することを含む、請求項20又は24に記載の方法。
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